TW201308451A - 用於減緩介金屬化合物成長之方法 - Google Patents
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Abstract
本發明係有關於一種用於減緩介金屬化合物成長之方法,步驟包含:(i)製備一基板元件,包括在一基板上電鍍至少一金屬墊層,接著在該金屬墊層上電鍍至少一很薄的一薄銲料,進行適當的熱處理製程;(ii)在該基板元件上再鍍上適當厚度的銲料;其中,該薄銲料經過適當的熱處理後,會與金屬墊之金屬反應形成一薄的介金屬化合物,因此可以在之後的迴銲製程抑制介金屬化合物的生成速率之效果,藉以減緩微小接點銲料與金屬墊上的金屬反應變成介金屬化合物。一旦介金屬化合物成長速率能被減緩,錫晶鬚(Sn whisker)的成長也可以被抑制。
Description
本發明係有關於一種用於減緩介金屬化合物成長之方法,特別是一種用於減緩銲錫與金屬墊層形成介金屬化合物之方法。此外,本發明又有關於一種覆晶接合的結構。
半導體技術及封裝的發展趨勢是密度越來越高,且接點(interconnects)越來越小,目前覆晶銲錫接點的尺寸(直徑)約為100微米(μm)。習知的覆晶銲錫接點,參照圖1、圖2A、圖2B,係在一矽(Si)板(11)鍍上一厚度5微米的銅(Cu)金屬墊層(12);之後在該銅金屬層(12)鍍上一厚度3微米的鎳(Ni)金屬層(13);及在該鎳金屬層鍍上厚度約70至100微米的銲錫(14),形成一含有微銲錫接點之半導體晶片元件(1);接著進行覆晶程序,將該元件(1)與矽板(21)上鍍有銅金屬墊層(22)、鎳金屬層(23)之元件(2)接合。通常對於很小的接點而言,例如3D IC中的微銲錫接點(microbumps)(參照圖1B),接點的總厚度(bump height)約為20微米,而銲錫厚度僅有約數微米至10微米,上下端的銅或鎳金屬墊層(under-bump-metallization,UBM)總厚度各約8微米。當接點製程完成或是經過10次迴銲測試後,或是在使用一段時間後,銲錫接點將會全部轉換成諸如Cu-Sn、Ni-Sn或是Cu-Ni-Sn之類的介金屬化合物接點,已發現這類介金屬化合物性質較脆,因此會嚴重影響銲錫接點的機械性質,例如元件若用於可攜式產品,當掉落或撞擊到後,接點有可能會斷裂。近年,改善上述問題的解決方式係在微銲錫接點(microbumps)再鍍上一層鎳作為擴散阻障層,但是這種方式的成本較高,且由於鎳的應力較大,對接點的機械性質也有負面的影響。
銲錫是封裝領域最常用的銲料,早期封裝業者係以共晶錫鉛銲錫與銅或鎳金屬在熔融狀態下(例如溫度約220℃)進行接合。然而,共晶錫鉛銲錫會與銅發生反應,而生成如Cu3Sn及/或Cu6Sn5之類的介金屬化合物。由於含鉛材料係有害環境,因此隨著環保意識的重視,此類共晶鉛銲錫材料已被禁止用作覆晶接點之銲料,進而以無鉛銲錫取代。
目前較常使用的無鉛銲錫,例如錫銀、錫銀銅等等,它們的熔點通常比習知的共晶錫鉛銲錫的熔點高約50℃,也就是說,使用無鉛銲錫係需要在約250℃至260℃之更高溫度下進行接合。但是,大部分的無鉛銲錫與銅鎳的反應更快,會形成更厚的例如Cu-Sn化合物。雖然銲錫本身的機械性質較佳,能夠吸收整個結構體的應力,但是反應所產生的Cu-Sn化合物的機械性質比較差(例如較脆),因此,若是形成較厚的Cu-Sn化合物,當整個結構體受到應力時,容易從Cu-Sn化合物脆斷而破壞整個結構體。
銅及錫的反應很快,甚至在室溫下就會反應,習知技術並無法減緩或控制如Cu6Sn5之類的介金屬之形成。一般,在尺寸較大的銲錫接點,如覆晶銲錫接點,生成介金屬化合物會形成接點,並不會影響接點的機械性質,但是對於很小的接點而言,例如3D IC製程中的微銲錫接點(microbumps),銲錫體積僅約為覆晶銲錫接點的一百分之一而已,當接點製程完成或是經過多次(例如10次)迴銲測試後,或是在使用一段時間後,銲錫接點將會全部轉換成Cu-Sn介金屬化合物接點,由於此介金屬化合物性質較脆,因此會嚴重影響到接點的機械性質。
目前的解決方式,通常係在微銲錫接點再鍍上一層鎳作為擴散阻障層,但是這種方式的成本較高,且由於鎳的應力較大,對接點的機械性質有負面的影響。
另一種習知技術,是利用濺鍍(sputtering)的方法共濺鍍銅與鎳,但這種方法並無法鍍上厚的膜,成本更高,此外,因為無鉛銲錫與銅及鎳的反應速率比含鉛銲錫快很多,這種方法亦無法適用於無鉛銲錫。
先前技術中,如美國專利USP 6,716,738 B2(公告日期:2004年4月6日)揭示「藉電鍍製造覆晶相互接的多層UBM之方法(Method of fabricating multilayered UBM for flip chip interconnections by electroplating)」,此專利係藉由調整電鍍得到的金屬層,變成Cu-Ni金屬層來控制鍍得之金屬層的應力與金屬層的成分,其利用鎳作為反應阻障層,以減緩銅、鎳與銲錫反應形成的化合物厚度。這種利用阻障層之缺點在於同時鍍銅與鎳金屬層,製程複雜且成分不易控制,及金屬層的應力也不容易控制,因此穩定性不佳,會影響良率,此外,銅也會跟銲錫反應。
美國專利USP 6,602,777(公告日期:2003年8月5日)揭示「控制銲錫接點之介金屬化合物形成之方法(Method for controlling the formation of intermetallic compound in solder joints)」,此專利係藉由調整銲錫中的銅濃度來控制銲錫與鎳金屬層形成的介金屬(intermetallic compound)種類,例如(Cu1-xNix)6Sn5,或是(Ni1-yCuy)3Sn4。然而,這種方法並無法控制銅與銲錫生成的介金屬化合物之厚度。
中華民國專利I338344(公告日期:2011年3月1日)揭示「具有銲料凸塊以抑制介金屬化合物成長之半導體晶片及其製造方法」,此專利係利用滲入銲料凸塊的穿透層材料,改變銲料凸塊成為多成份之銲料凸塊,以抑制化合物的成長。這篇專利係改變銲錫成分以抑制介金屬化合物(IMC)的成長,但是對抑制Cu-Sn化合物的反應卻是很有限。
公開文獻,「藉由和帶銅的Sn(Cu)銲錫反應減緩在Ni(P)基板上之Ni3P晶層成長」(“Retarding growth of Ni3P crystalline layer in Ni(P) substrate by reacting with Cu-bearing Sn(Cu) solders),S.J. Wang,C.Y. Liu,Scripta Materialia 49(2003) 813-818),此文獻係藉由調整Sn-Cu銲錫中的銅濃度來控制該銲錫與鎳的反應,以抑制Ni3P相的生成,但是其並無法抑制Cu-Sn或Ni-Sn化合物的成長。
為避免上述習知技術之問題及缺點,本發明之發明人因此提出利用控制形成銲錫與銅之介金屬化合物之厚度,也就是說,銲錫與銅在接合之前能夠快速地先反應產生介金屬化合物(如Sn-Cu化合物),而於進行接合後使該藉金屬化合物的厚度成長減緩。
本發明之一目的在於提供一種用於減緩介金屬化合物成長之方法,包含步驟:
(i)製備一基板元件,包括:
(i-1)在一基板上電鍍至少一金屬墊層,
(i-2)在該金屬墊層上電鍍至少一薄銲料,接著進行熱處理製程,以製得一基板元件;此熱處理可以是液態下的迴銲製程或是固態時效製程。
(ii)在該基板元件上再鍍上一適當厚度的銲錫。
本發明特別適合用於減緩封裝中銲錫與銅金屬墊層之介金屬化合物的形成,如上述本發明之方法,在進行晶片接合前,在基板上的金屬墊層先鍍上一層很薄的薄銲料,經過熱處理製程,該薄銲料會與金屬墊層的金屬先行反應,因而改變了所生成的介金屬化合物的形態與種類。接著進行後續的覆晶對接製程,由於在接合前該很薄的薄銲料已與金屬墊層的金屬生成一很薄的介金屬化合物,在接合後會產生抑制該接點(或凸塊)之介金屬化合物的生成速率之效果。
根據本發明之方法,參照圖3,在一基板上電鍍一金屬墊層(步驟,S201),接著在該金屬墊層上電鍍一薄銲料(步驟,S301),然後進行高溫熱處理製程,得到一基板元件,其中,該薄銲料經過高溫熱處理後,與金屬墊層的金屬會反應形成一薄介金屬化合物(步驟,S401)。之後在再鍍上適當厚度的銲錫(步驟,S501)將步驟S101、201、301、401、501所製得的一基板元件可以作後續接合製程(步驟,S600)。
本發明之方法中,該薄銲料與金屬墊層之金屬反應形成的介金屬化合物均具有隔離的功能,可減少金屬墊層之金屬原子透過介金屬化合物與銲料反應的通道,讓金屬墊層的金屬與銲料凸塊隔離,依此即能有效地抑制接點區域的介金屬化合物之成長。當半導體元件(例如半導體晶片)進行覆晶接合製程時,由於基板上的金屬墊層與銲料之間會先形成一介金屬化合物,在接合後可減少金屬墊層中的金屬原子滲入銲料接點,因此,當接合後再進行迴銲或多次迴銲程序之後,會有減少銲料接點之介金屬化合物形成的效果,另一方面,金屬墊層的金屬原子消耗也會減少。
本發明之另一目的在於提供一種覆晶接合或是銲錫介面的結構,包含:
(A)一基板元件,含有:
(A-1)一基板,
(A-2)至少一金屬墊層,該金屬墊層係電鍍形成於該基板上,
(A-3)至少一薄銲料,該薄銲料係電鍍於該金屬墊層上;
(A-4)於該基板元件再鍍上一適當厚度的銲錫層;其中,(A)一基板元件可以與其它基板元件呈現覆晶接合,經過迴銲程序,得到一覆晶接合的結構,其特徵在於所述該薄銲料在接合之前與金屬墊層之金屬形成一連續層狀或是接近連續層之薄介金屬化合物。
本發明之結構中,所形成之一薄介金屬化合物係具有隔離金屬墊層的金屬與銲料接點(或凸塊)之功能,因此能有效地抑制接點區域的介金屬化合物之成長。
本發明中,電鍍金屬墊層或銲料之方法不特別限制,可為此技術領域中習用電鍍技術,例如:電鍍銅可使用硫酸銅溶液;電鍍錫銀銲錫可使用Sn2P2O7及AgI之溶液。
本發明中,使用的基板不特別限制,根據本發明之一具體實施,該基板可為半導體晶片、矽晶片、高分子或玻璃。
本發明中,使用的金屬墊層的金屬材料不特別限制,根據本發明之一具體實施,該金屬材料可為銅、鎳、金或其合金,較佳為銅。本發明之金屬墊層的厚度範圍為約數微米至100微米。
本發明中,使用的銲料不特別限制,根據本發明之一具體實施,該銲料可為無鉛銲料,較佳為無鉛銲錫。
根據本發明之一具體實施,所述薄銲料厚度不超過4微米,較佳為2微米。本發明中,接合後,銲料接點的總厚度不超過100微米,較佳為20微米。
本發明之用於減緩介金屬化合物成長之方法,尤其適合應用於3D IC產業領域(例如3D IC封裝技術)、中央處理器(CPU)、手機、影像處理晶片、動態隨機存取記憶體(DRAM)等產品。
以下將對本發明更詳細的描述,所提出的具體實施例及圖式係用於進一步說明本發明,而不意欲用於限制本發明的技術範圍。
首先,製備一電鍍有一薄銲料之試片“2-μm-SnAg/銅墊層的試片”。
製備電鍍有很薄的一薄銲料之試片“2-μm-SnAg試片”,與電鍍有薄的第二薄銲料之試片“19-μm-SnAg試片”。
參照圖4A,製備一電鍍有一薄銲料之試片“2-μm-SnAg試片”。
首先,準備一矽晶片作為一第一基板(31),其上電鍍有一厚度5微米的第一銅金屬墊層(Cu UBM)(321、322、32n,以下本文稱為“32”);接著,在該第一銅金屬墊層(32)上電鍍一層厚度2微米的SnAg無鉛銲料(331、332、33n,以下本文稱為“33”),在260℃溫度下進行迴銲(reflowing),歷時10分鐘左右,該無鉛銲料經過260℃迴銲及冷卻之後,會與銅金屬反應而形成一很薄的第一薄Cu-Sn介金屬化合物(Cu-SnIMC)(未標示),依此得到“2-μm-SnAg試片”。
參照圖4B,製備一電鍍有較厚銲料之試片“19-μm-SnAg試片”。
準備另一矽晶片作為一第二基板(41),在該第二基板(41)電鍍上另一厚度20微米之第二銅金屬墊層(Cu UBM)(421、422、423,以下本文稱為“42”);接著,在該第二銅金屬墊層(42)上電鍍一厚度19微米的SnAg無鉛銲料(431、432、43n,以下本文稱“43”),在260℃溫度下進行迴銲(reflowing),歷時1-10分鐘左右,該無鉛銲料經過260℃迴銲及冷卻之後,會形成較厚之Cu-Sn介金屬化合物(Cu-Sn IMC)(未標示),依此得到“19-μm-SnAg試片”。
上述製程中,鍍上很薄的銲料之第一銲料(33)在進行後續接合程序之前,會先與銅金屬墊層之銅金屬反應形成薄Cu-Sn介金屬化合物,該Cu-Sn介金屬化合物可減少銅原子透過Cu-Sn介金屬化合物與無鉛銲料反應的通道,讓第一銅金屬墊層(32、42)與銲料接點(或凸塊)隔離。
本實施例中,利用掃描式電子顯微鏡(SEM)檢測該結構之橫截面圗,讓該結構於260℃溫度下再進行迴銲程序,歷時5分鐘及10分鐘,以進行銲料接點之測試。
參照圖5A、5B,試片為“2-μm-SnAg試片”,圖5A是剛製備後及圖5B是迴銲10分鐘後的掃描式電子顯微鏡之橫截面圗。可清楚觀察到,當迴銲10分鐘後,上方的無鉛銲錫幾乎全部反應成Cu-Sn介金屬化合物。而且其結構呈現層狀結構。此層狀結構Cu-Sn介金屬化合物即是用來接下來接合製程中減緩銅擴散到銲料的阻障層。
參照圖6A、6B、6C,試片是在“2-μm-SnAg試片”迴銲10分鐘後,再鍍上厚約20微米的銲料,再迴銲1、5、及10分鐘後的掃描式電子顯微鏡之橫截面圗。可以看出即使迴銲10分鐘後,Cu-Sn介金屬化合物仍幾乎維持層狀結構。因此,Cu-Sn介金屬化合物之間的通道變少,因此銅原子要擴散進入銲錫內反應變得較困難。
另一方面,測試結果顯示,若沒有使用此方法,Cu-Sn介金屬化合物會成長較快。參照圖7A、7B、7C,此試片是在“19-μm-SnAg試片”迴銲1、5、及10分鐘後的掃描式電子顯微鏡之橫截面圗。可以看出Cu-Sn介金屬化合物會明顯隨著迴銲時間增加而增厚的情況產生。而且型貌呈現半圓形形狀,因此銅原子容易從Cu-Sn介金屬化合物中間之通道擴散進入銲錫內反應。所以Cu-Sn介金屬化合物會明顯隨著時間增加而增厚。
參照圖8,此圖顯示量測到之Cu-Sn介金屬化合物厚度隨著迴銲時間增加的關係。可觀察到經過預先經過迴銲10分鐘的“2-μm-SnAg試片”端之Cu-Sn介金屬化合物較不會隨著時間增加而有明顯地增厚的情況產生,當迴銲10分鐘後,觀察到厚度的增加只約0.2微米;但是19-μm-SnAg試片”迴銲迴銲10分鐘後,Cu-Sn介金屬化合物增加約1.6微米。因此可證實,根據本發明之方法,在接合前先在金屬墊鍍上一薄銲料,確可達到抑制Cu-Sn介金屬化合物厚度成長的效果,同時銅金屬墊層與銲料凸塊隔離,也讓銅金屬層的消耗厚度明顯地減少。
此外,針對本發明之用於減緩介金屬化合物成長之方法,探討其可達到抑制Cu-Sn介金屬化合物增厚之效果的機制,主要歸因於下列因素:
(1)當接合前,沒有在金屬墊層先鍍上一很薄的銲料時,生成的Cu-Sn介金屬化合物(例如Cu6Sn5化合物)是類似半球型的形狀。如圖7A所示之迴銲1分鐘後“19-μm-SnAg試片”端的Cu-Sn化合物的形狀,該“19-μm-SnAg試片”係已利用蝕刻液,蝕刻掉剩餘的銲料,可觀察到生成的Cu-Sn介金屬化合物形狀,在半球型Cu6Sn5之間有許多的通道(channels),可以讓底下的銅持續擴散到銲錫內部反應。
再者,當接合前,在金屬墊層先鍍上一很薄的銲料時,如上述本發明之方法,觀察到“2-μm-SnAg試片”,經過10分鐘的迴銲過程後,生成的Cu6Sn5或是Cu3Sn化合物是類似層狀結構,而且幾乎沒有通道,此乃是因為銲錫只有2微米厚,經過10分鐘的迴銲過程後,銲錫幾乎全部消耗完,Cu6Sn5間的通道也就關閉起來。因此,當“2-μm-SnAg試片”再鍍上銲料時,在“2-μm-SnAg試片”的Cu-Sn反應就很明顯地被抑制。
(2)因為鍍上的銲錫很薄,例如只有2微米厚,經過10分鐘的迴銲過程後,銲錫幾乎全部消耗完,Cu6Sn5化合物也可能全部或部分轉變成層狀結構的Cu3Sn化合物,下方的銅要擴散到銲錫內反應較不容易,因此Cu-Sn反應就很明顯地被抑制。依此,可抑制Cu-Sn化合物厚度增厚。
藉由上述具體實施例可證實,根據本發明之方法確能有效地減緩介金屬化合物厚度的成長。一旦介金屬化合物成長速率能被減緩,錫晶鬚(Sn whisker)的成長也可以被抑制。因此本發明也可以應用於抑制錫晶鬚的成長。
本發明可在不偏離本發明之範疇的情況下,以多種形式實現,上述實施例僅係為了方便說明而舉例而已,應理解的是(除非另有指明)本發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。
31...第一基板
32...第一銅金屬墊層
33...無鉛銲料
41...第二基板
42...第二銅金屬墊層
43...無鉛銲料
IMC...介金屬化合物
圖1係描述習知的覆晶銲錫接點之示意圖。
圖2A係描述習知的覆晶銲錫接點剖面之掃描式電子顯微鏡影像圖(cross-sectional scanning electron microscope(SEM) image)。
圖2B係描述習知的20微米覆晶微銲錫接點剖面之掃描式電子顯微鏡影像圖。
圖3係描述描述根據本發明之方法流程圖。
圖4A係描述根據本發明之方法,基板元件鍍有很薄銲料之具體實施示意圖。
圖4B係描述根據本發明之方法,基板元件鍍有較薄銲料之具體實施示意圖。
圖5A係根據本發明之方法,在5微米厚的銅銲墊鍍上2微米銲料後之電子顯微鏡橫截面圗。
圖5B係根據本發明之方法,在5微米厚的銅銲墊鍍上2微米銲料後且經過260℃迴銲10分鐘後之電子顯微鏡橫截面圗。
圖6A描述根據本發明之方法,2-μm-SnAg試片”在260℃迴銲10分鐘後,再鍍上20微米銲料,再於260℃迴銲1分鐘後之電子顯微鏡橫截面圗。
圖6B描述根據本發明之方法,2-μm-SnAg試片”在260℃迴銲10分鐘後,再鍍上20微米銲料,再於260℃迴銲5分鐘後之電子顯微鏡橫截面圗。
圖6C描述根據本發明之方法,2-μm-SnAg試片”在260℃迴銲10分鐘後,再鍍上20微米銲料,再於260℃迴銲10分鐘後之電子顯微鏡橫截面圗。
圖7A”19-μm-SnAg試片”在260℃迴銲1分鐘後之電子顯微鏡橫截面圗。
圖7B”19-μm-SnAg試片”在260℃迴銲5分鐘後之電子顯微鏡橫截面圗。
圖7C”19-μm-SnAg試片”在260℃迴銲10分鐘後之電子顯微鏡橫截面圗。
圖8量測之介面Cu-Sn化合物的厚度,在260℃,隨著迴銲時間增加之變化圖。
31...第一基板
32...第一銅金屬墊層
33...無鉛銲料
Claims (10)
- 一種用於減緩介金屬化合物成長之方法,包含步驟:(i) 製備一基板元件,包括:(i-1)在一基板上電鍍至少一金屬墊層,(i-2)在該金屬墊層上電鍍至少一薄銲料,接著進行熱處理製程,以製得一基板元件;再鍍上適當厚度之銲錫。(ii) 將此元件與其它元件作後續接合製程,其中,該薄銲料在經過高溫熱處理後,在覆晶對接之前,與金屬墊層之金屬反應形成一薄介金屬化合物。
- 如申請專利範圍第1項之方法,其中該基板為半導體晶片、矽晶片。
- 如申請專利範圍第1項之方法,其中該金屬墊層之金屬為銅。
- 如申請專利範圍第1項之方法,其中該銲料為無鉛銲錫。
- 如申請專利範圍第1項之方法,其中該薄銲料之厚度不超過4微米。
- 一種覆晶接合的結構,包含(A)一基板元件,該基板元件含有:(A-1)一基板,(A-2)至少一金屬墊層,該金屬墊層係電鍍形成於該基板上,(A-3)至少一薄銲料,該薄銲料係電鍍於該金屬墊層上;及經過熱處理後,再鍍上適當厚度之銲料;其中,(A)一基板元件,經過熱處理程序,其特徵在於所述第一薄銲料在接合之前與金屬墊層之金屬形成一連續層薄介金屬化合物。
- 如申請專利範圍第6項之結構,其中該基板為半導體晶片或矽晶片。
- 如申請專利範圍第6項之結構,其中該金屬墊層之金屬為銅。
- 如申請專利範圍第6項之結構,其中該銲料為無鉛銲錫。
- 如申請專利範圍第6項之結構,其中該第一薄銲料之厚度不超過4微米。
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US9227257B2 (en) | 2012-04-24 | 2016-01-05 | Seagate Technology Llc | Laser subassembly metallization for heat assisted magnetic recording |
TWI572436B (zh) * | 2014-12-19 | 2017-03-01 | 中原大學 | 一種銲接結構及其製造方法 |
DE102016103585B4 (de) * | 2016-02-29 | 2022-01-13 | Infineon Technologies Ag | Verfahren zum Herstellen eines Package mit lötbarem elektrischen Kontakt |
JP6042577B1 (ja) * | 2016-07-05 | 2016-12-14 | 有限会社 ナプラ | 多層プリフォームシート |
US10388627B1 (en) * | 2018-07-23 | 2019-08-20 | Mikro Mesa Technology Co., Ltd. | Micro-bonding structure and method of forming the same |
US10347602B1 (en) * | 2018-07-23 | 2019-07-09 | Mikro Mesa Technology Co., Ltd. | Micro-bonding structure |
CN110026705A (zh) * | 2019-03-08 | 2019-07-19 | 南昌大学 | 一种增强Sn基钎料/Kovar合金互连焊点可靠性的镀层及其制备工艺 |
WO2023039786A1 (zh) * | 2021-09-16 | 2023-03-23 | 京东方科技集团股份有限公司 | 阵列基板及其检测方法、发光装置 |
CN114226901B (zh) * | 2021-12-31 | 2023-03-31 | 北京工业大学 | 一种多双孪晶组和细小晶粒构成的多晶结构焊点生成方法 |
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JPH11307565A (ja) * | 1998-04-24 | 1999-11-05 | Mitsubishi Electric Corp | 半導体装置の電極およびその製造方法ならびに半導体装置 |
JP3910363B2 (ja) * | 2000-12-28 | 2007-04-25 | 富士通株式会社 | 外部接続端子 |
JP4656275B2 (ja) * | 2001-01-15 | 2011-03-23 | 日本電気株式会社 | 半導体装置の製造方法 |
US6602777B1 (en) | 2001-12-28 | 2003-08-05 | National Central University | Method for controlling the formation of intermetallic compounds in solder joints |
TW558821B (en) * | 2002-05-29 | 2003-10-21 | Via Tech Inc | Under bump buffer metallurgy structure |
US6716737B2 (en) | 2002-07-29 | 2004-04-06 | Hewlett-Packard Development Company, L.P. | Method of forming a through-substrate interconnect |
TWI261330B (en) * | 2005-05-06 | 2006-09-01 | Via Tech Inc | Contact structure on chip and package thereof |
DE102005051857A1 (de) | 2005-05-25 | 2007-02-22 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | UBM-PAD, Lötkontakt und Verfahren zur Herstellung einer Lötverbindung |
JP4742844B2 (ja) * | 2005-12-15 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR100859641B1 (ko) | 2006-02-20 | 2008-09-23 | 주식회사 네패스 | 금속간 화합물 성장을 억제시킨 솔더 범프가 형성된 반도체칩 및 제조 방법 |
JP4939891B2 (ja) * | 2006-10-06 | 2012-05-30 | 株式会社日立製作所 | 電子装置 |
JP2009054790A (ja) * | 2007-08-27 | 2009-03-12 | Oki Electric Ind Co Ltd | 半導体装置 |
JP4724192B2 (ja) * | 2008-02-28 | 2011-07-13 | 株式会社東芝 | 電子部品の製造方法 |
JP5067481B2 (ja) | 2008-05-02 | 2012-11-07 | 富士通株式会社 | 配線基板およびその製造方法、電子装置の製造方法 |
JP2009283628A (ja) * | 2008-05-21 | 2009-12-03 | Tamura Seisakusho Co Ltd | 半導体素子実装方法 |
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JP5922523B2 (ja) | 2016-05-24 |
KR20130018542A (ko) | 2013-02-25 |
TWI430377B (zh) | 2014-03-11 |
US8835300B2 (en) | 2014-09-16 |
US20130037940A1 (en) | 2013-02-14 |
CN102931107A (zh) | 2013-02-13 |
KR101424095B1 (ko) | 2014-07-28 |
CN102931107B (zh) | 2016-02-10 |
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