WO2023039786A1 - 阵列基板及其检测方法、发光装置 - Google Patents

阵列基板及其检测方法、发光装置 Download PDF

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Publication number
WO2023039786A1
WO2023039786A1 PCT/CN2021/118687 CN2021118687W WO2023039786A1 WO 2023039786 A1 WO2023039786 A1 WO 2023039786A1 CN 2021118687 W CN2021118687 W CN 2021118687W WO 2023039786 A1 WO2023039786 A1 WO 2023039786A1
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WIPO (PCT)
Prior art keywords
light
conductive pad
layer
conductive
substrate
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PCT/CN2021/118687
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English (en)
French (fr)
Inventor
汤海
高亮
翟明
秦建伟
车晓盼
马光和
Original Assignee
京东方科技集团股份有限公司
合肥京东方星宇科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方星宇科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180002555.8A priority Critical patent/CN116137932A/zh
Priority to PCT/CN2021/118687 priority patent/WO2023039786A1/zh
Publication of WO2023039786A1 publication Critical patent/WO2023039786A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate, a detection method thereof, and a light emitting device.
  • Mini LED Mini Light Emitting Diode, sub-millimeter light-emitting diode
  • Micro LED Micro Light Emitting Diode, micro-light-emitting diode
  • the welding process of the above two kinds of LED chips is an important step in the preparation of these two types of display products.
  • the problem of virtual welding is very easy to occur, resulting in poor conduction between the LED chip and the backplane, which in turn affects the quality of the display products. decline.
  • an array substrate including:
  • the substrate comprising a plurality of first light-transmitting regions
  • the first conductive layer includes a plurality of conductive pad groups, and the conductive pad group includes at least one conductive pad;
  • the orthographic projection area of the conductive pad on the substrate overlaps with the first light-transmitting region; the transmittance of the part of the substrate located in the first light-transmitting region is greater than or equal to the first default value.
  • the first preset value is greater than or equal to 50%.
  • the area of the overlapping region accounts for at least half of the area of the orthographic projection of the conductive pad on the substrate.
  • the edge of the orthographic projection area of the conductive pad on the substrate is located within the first light-transmitting area.
  • the material of the part of the substrate located in the first light-transmitting region includes a light-transmitting material, and/or, the part of the substrate located in the first light-transmitting region includes a hollow structure.
  • At least two of the first light-transmitting regions are arranged in communication to form a second light-transmitting region.
  • the orthographic projection area of part of the conductive pad group on the substrate overlaps with the second light-transmitting area.
  • the substrate further includes a plurality of third light-transmitting regions;
  • the first conductive layer further includes a plurality of wires, and the wires are electrically connected to the conductive pad;
  • part of the third light-transmitting area and part of the first light-transmitting area are arranged in communication, and/or, part of the third light-transmitting area and part of the second light-transmitting area Connectivity settings.
  • the base includes a substrate and a second conductive layer on the substrate, the second conductive layer is insulated from the first conductive layer;
  • the second conductive layer includes a plurality of driving lines arranged along the first direction and extending along the second direction; the orthographic projection of the third light-transmitting region on the substrate falls into two adjacent A region between orthographic projections of the drive lines on the substrate.
  • At least part of the third light-transmitting regions are arranged along the first direction and extend along the second direction.
  • the distance between the contour of the orthographic projection of the light-transmitting region on the first conductive layer and the conductive pad ranges from 0-200 ⁇ m.
  • a plurality of conductive pad groups are arranged in an array, and the conductive pads include a metal layer and a connection layer on the metal layer; the array substrate also includes a plurality of components, one The components are electrically connected to the same set of conductive pads;
  • connection layer is located between the metal layer and the component, and the metal layer is connected to the component through the connection layer;
  • connection layer includes an intermetallic compound, and the intermetallic compound
  • the morphology is at least one of block structure, shell structure, dendritic structure or rice grain structure.
  • the intermetallic compound includes Cu 6 Sn 5 , Cu 3 Sn, Ni 3 Sn 4 , (Cu, Ni) 6 Sn 5 , (Ni, Cu) 3 Sn 4 or Ag 3 Sn any one or more of them.
  • the array substrate further includes a solder layer, the solder layer is located between the solder pin of the component and the conductive pad, and the solder layer includes a solder material;
  • the intermetallic compound has a rice grain structure.
  • the array substrate further includes a solder layer, the solder layer is located between the solder pin of the component and the conductive pad, and the solder layer includes a solder material;
  • the intermetallic compound has one or more of a block structure, a shell structure or a dendritic structure.
  • the base includes a substrate, and a buffer layer, a second conductive layer, a first insulating layer, a first planar layer, and a second insulating layer that are sequentially stacked on the substrate;
  • the materials of the buffer layer, the first insulating layer, the first flat layer and the second insulating layer are all light-transmitting materials
  • the material of the part of the second conductive layer located in the light-transmitting region is a light-transmitting material, or the part of the second conductive layer located in the light-transmitting region is a hollow structure.
  • an embodiment of the present application provides a light emitting device, including the above-mentioned array substrate.
  • the embodiment of the present application provides a detection method
  • the array substrate includes a plurality of components, one component is electrically connected to each of the conductive pads in the same group of conductive pads, and the The methods described include:
  • the parameter information includes the area of the orthographic projection of the connection layer of the conductive pad on the substrate and the area of the orthographic projection of each solder leg of the component on the substrate ;
  • the determining whether the connection between the component and the conductive pad is poor according to the parameter information of each of the conductive pads in the target image includes:
  • connection layer of at least one of the conductive pads on the substrate in the conductive pad group is smaller than the second predetermined area of the orthographic projection of the solder pin on the substrate value, it is determined that the connection between the component and the conductive pad is poor.
  • the parameter information includes a qualified template image for connecting the component to the conductive pad
  • the determining whether the connection between the component and the conductive pad is poor according to the parameter information of each of the conductive pads in the target image includes:
  • FIG. 1 is a SEM comparison diagram of qualified soldering and virtual soldering between pads and components in a related art provided in an embodiment of the present application.
  • FIGS. 2a-2d are schematic structural views of four different array substrates provided by the embodiment of the present application.
  • 3a-10b are schematic structural views of sixteen types of array substrates illustrating the positional relationship between the welding area and the light-transmitting area provided by the embodiment of the present application;
  • Figure 11a- Figure 11c is a schematic diagram of the principle of the formation process of the connection layer provided by the embodiment of the present application.
  • Figure 11d- Figure 11e are schematic diagrams of two kinds of characteristic topography of the connection layer provided by the embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another array substrate provided in the embodiment of the present application.
  • Fig. 13a is a morphological characteristic diagram of poor pad welding provided by the embodiment of the present application.
  • Fig. 13b is a topographic characteristic diagram of qualified pad welding provided by the embodiment of the present application.
  • Figures 14a-16b are schematic structural views of six different array substrates provided by the embodiments of the present application.
  • FIG. 17 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 18 is a flow chart of a method for preparing an array substrate provided by an embodiment of the present application.
  • FIG. 19 is a flowchart of a method for detecting an array substrate provided by an embodiment of the present application.
  • plural means two or more; the orientation or positional relationship indicated by the term “upper” is based on the orientation or positional relationship shown in the drawings, It is only for the convenience of describing the present application and simplifying the description, but does not indicate or imply that the structures or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
  • both Mini LED and Micro LED light-emitting devices are fixed in the substrate by welding. Whether it is a light-emitting device in the light-emitting substrate or a light-emitting device in the backlight substrate, if one of the light-emitting devices is soldered or poorly welded, and it is not timely If the problem is found and repaired, the light-emitting device cannot emit light during use after the packaging process is completed, and the substrate may be scrapped, which will result in huge cost losses. Therefore, rapid and accurate detection of false soldering, and timely repairs, It is an important step in the entire Mini/Micro LED process route to ensure that each light-emitting device is soldered qualified.
  • Figure 1 shows the SEM (Scanning Electron Microscope, scanning electron microscope) image of the light-emitting device in the related art at the welding position. It can be seen that one pad (Pad) is welded to a solder leg of the component and is qualified (OK), while False welding (NG) between another pad (Pad) and another solder leg of the component.
  • SEM Sccanning Electron Microscope, scanning electron microscope
  • an array substrate as shown in FIG. 2a, including:
  • a substrate 1 the substrate 1 includes a plurality of first light-transmitting regions T1;
  • the first conductive layer 2 includes a plurality of conductive pad groups W, and the conductive pad group W includes at least one conductive pad (such as H1, H2 in FIG. 2a);
  • the orthographic projection area of the conductive pad on the substrate 1 overlaps with the first light-transmitting region T1; the transmittance of the portion of the substrate 1 located in the first light-transmitting region T1 is greater than or equal to a first preset value.
  • the first preset value is greater than or equal to 50%.
  • the first preset value may include 50%, 55%, 60%, 70%, 80%, and 85%, which may be determined according to different product designs and transmittance requirements, and there is no limitation here.
  • the overlapping area between the orthographic projection area of the conductive pad on the substrate 1 and the first transparent region T1 means that the orthographic projection area of the conductive pad on the substrate 1 at least partially overlaps with the first transparent region T1 . It can be understood that if the orthographic projection area of the conductive pad on the substrate 1 overlaps with the first light-transmitting area T1 , there is no limitation on the size of the overlapping area, which can be determined according to the requirements of different products.
  • the first conductive layer 2 includes a conductive pad group W
  • the conductive pad group W includes a third conductive pad H3, a fourth conductive pad H4, a fifth conductive pad H5 and a sixth conductive pad.
  • Pad H6 wherein the orthographic projection area of each conductive pad in the same conductive pad group W on the substrate 1 overlaps with the same first light-transmitting area T1 respectively.
  • the conductive pad may be a pad.
  • the area of the overlapping area accounts for at least half of the area of the orthographic projection area of the conductive pad on the substrate 1 .
  • the back of each conductive pad can be leaked through the first light-transmitting region T1, so as to facilitate the observation of the back of the conductive pad through the back detection technology to determine whether there is a bad problem in the conductive pad; in the subsequent process, the conductive When the pad is connected to the component 3, it is also convenient to judge whether there is a poor connection between the component 3 and the conductive pad through the back detection technology.
  • Poor connection conditions include poor soldering, such as poor soldering, damaged or corroded conductive pads, and other bad problems.
  • half of the orthographic projection of some conductive pads on the substrate 1 may overlap with the first light-transmitting region T1, and part of the conductive pads on the substrate 1 may More than half of the area of the orthographic projection overlaps with the first transparent area T1. The details can be determined according to the actual situation.
  • the area of the overlapping area accounts for at least half of the area of the orthographic projection area of the conductive pads (such as H1 and H2 in FIG.
  • the region T1 leaks at least half of the backside of each conductive pad, thereby improving the accuracy of determining whether there is a poor connection between the component 3 and the conductive pad in the backside detection technology.
  • the first light-transmitting region T1 may also pass through The portion on the back side of the conductive pad leaked from the region T1 determines whether there is a poor connection between the component 3 and the conductive pad.
  • this situation is rare and not universal.
  • the conductive pad set W includes at least one conductive pad.
  • the conductive pad set W includes two conductive pads ( H1 , H2 ) as an example.
  • each conductive pad group W corresponds to a component 3, and the number of conductive pads included in each conductive pad group W can be determined according to the number of solder feet included in the components 3 electrically connected to the conductive pad group W .
  • the component 3 includes a component body 31, a first soldering leg 32 and a second soldering leg 33; correspondingly, the conductive pad group W includes a first conductive pad H1 and a second conductive pad H1. Pad H2; the first soldering leg 32 is electrically connected to the first conductive pad H1, and the second soldering leg 33 is electrically connected to the second conductive pad H2.
  • the embodiments of the present application do not limit the shape of the orthographic projection of the first light-transmitting region T1 on the first conductive layer 1 .
  • the shape of the orthographic projection of the first light-transmitting region T1 on the first conductive layer 1 can be roughly any one of strip, rectangle, square, rhombus, circle, semicircle or triangle. Can be other shapes, specifically can be designed according to actual needs.
  • the base 1 may include a substrate 100, a buffer layer 101, a second conductive layer 102, a first insulating layer 103, a first flat layer 104, and a second insulating layer 105 as shown in FIG. 14a;
  • the base 1 may include a substrate 100 and a buffer layer 101 as shown in FIG. 16a; the specific structure of the base 1 may be determined according to actual conditions, and is not limited here.
  • the first conductive layer 2 is used to form a conductive pattern.
  • the conductive pad may be a pad.
  • the material of the first conductive layer 2 may include any one of copper, aluminum, nickel, molybdenum and titanium or a combination of several metals arranged in layers.
  • the first conductive layer 2 may include a molybdenum-nickel-titanium alloy (MoNiTi) layer (or a molybdenum-niobium alloy layer (MoNb)), a copper metal layer and a copper-nickel alloy (CuNi) (or a nickel-gold layer ( NiAu)), molybdenum-nickel-titanium or molybdenum-niobium alloy layer can increase the nucleation density of copper metal grains in the electroplating process, and the copper-nickel alloy or nickel-gold layer can prevent the oxidation of copper metal.
  • the nickel-gold layer includes two film layers of a nickel sub-layer and a gold layer. In practical applications, the nickel sub-layer can be set in direct contact with the copper metal layer, or the gold layer can also be set in direct contact with the copper metal layer. The actual situation is determined, and there is no limitation here.
  • the thickness range of the molybdenum-nickel-titanium alloy layer in the first conductive layer 2 can be
  • the thickness can be or
  • the thickness of the first conductive layer 2 can range from 0.3 ⁇ m to 10 ⁇ m, for example, the thickness can be 0.3 ⁇ m, 0.5 ⁇ m, 0.6 ⁇ m, 0.9 ⁇ m, 2.7 ⁇ m, 3.6 ⁇ m, 4 ⁇ m, 4.5 ⁇ m, 5 ⁇ m , 6.5 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m or 10 ⁇ m.
  • the array substrate may only include one conductive layer as shown in Figure 16a and Figure 16b, at this time, the thickness of the first conductive layer 2 It can be 2.7 ⁇ m, 3.6 ⁇ m, 4 ⁇ m, 4.5 ⁇ m, 5 ⁇ m, 6.5 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m or 10 ⁇ m.
  • the transmittance of the part of the substrate 1 located in the first light-transmitting regions T1 is greater than or equal to the first preset value, thus, from The part of the substrate 1 located in the first light-transmitting region T1 can see the back of each conductive pad in the first conductive layer 2, and then detect possible defective problems of the conductive pads through the back detection technology, intercept the array substrate with defective problems and conduct Repairs to improve product reliability.
  • the edges of the orthographic projection areas of the conductive pads (such as H1 and H2 in FIG. 2 a ) on the substrate 1 are located within the first light-transmitting area T1 . It can be understood that the area of the orthographic projection of the conductive pad on the substrate 1 is smaller than the area of the first light-transmitting region T1 . In this way, the complete backside of the conductive pad can be observed through the first light-transmitting region T1, thereby improving the accuracy of observation.
  • the material of the part of the substrate 1 located in the first transparent region T1 includes a transparent material, and/or, the part of the substrate 1 located in the first transparent region T1 includes a hollow structure.
  • the above scenario includes three cases:
  • the first type as shown in FIG. 2b, the material of the part of the substrate 1 located in the first light-transmitting region T1 includes a light-transmitting material.
  • the first light-transmitting region T1 may be marked as L1.
  • the part of the substrate 1 located in the first light-transmitting region T1 is a hollow structure.
  • the first transparent Light zone T1 may be labeled K1.
  • the third type is that the material of the part of the substrate 1 located in the first transparent region T1 includes a transparent material, and the part of the substrate 1 located in the first transparent region T1 also includes a hollow structure.
  • the substrate 1 shown in FIG. 2c includes a light-transmitting layer 11 and a light-shielding layer 12.
  • the material of the light-transmitting layer 11 located in the first light-transmitting region T1 is a light-transmitting material, and the light-shielding layer 12 is located in the first light-transmitting region.
  • the part of T1 is a hollow structure, and the hollow structure of the part of the light-shielding layer 12 located in the first light-transmitting region T1 is marked as K2 here.
  • the entire layer of the light-transmitting layer 11 may be made of light-transmitting materials.
  • the light-transmitting material may be silica gel, ultraviolet curing glue, silicon nitride or silicon oxide.
  • the transmittance of the part of the substrate 1 located in the first light-transmitting regions T1 is greater than or equal to the first preset value, thus, from The part of the substrate 1 located in the first light-transmitting region T1 can see the back of each conductive pad in the first conductive layer 2, and then detect possible defective problems of the conductive pads through the back detection technology, intercept the array substrate with defective problems and conduct Repairs to improve product reliability.
  • At least two first light-transmitting regions T1 are arranged in communication to form a second light-transmitting region T2 .
  • the first conductive layer 2 includes a first conductive pad group W1, a second conductive pad group W2 and a seventh wiring 27, and the first conductive pad group W1 and the second conductive pad group W2 are respectively It is electrically connected to the seventh wiring 27; wherein, the orthographic projection of the first conductive pad group W1 on the substrate 1 falls into one first light-transmitting region T1, and the orthographic projection of the second conductive pad group W2 on the substrate 1 falls into another A first light-transmitting area T1, the two first light-transmitting areas T1 are connected to form a second light-transmitting area T2, so that the first conductive pad group W1, the second conductive pad group W2 and the seventh wiring 27 are on the substrate 1 The orthographic projections on all fall into the same second light-transmitting region T2.
  • the plurality of first light-transmitting regions T1 are connected so that the orthographic projections of the plurality of conductive pad groups W and the components 3 connected to the conductive pad groups W on the substrate 1 fall into the connected In the second light-transmitting region T2 formed by a plurality of first light-transmitting regions T1.
  • the orthographic projection area of a part of the conductive pad group W on the substrate 1 overlaps with the second light-transmitting area T2 .
  • the substrate 1 further includes a plurality of third light-transmitting regions T3;
  • the first conductive layer 2 further includes a plurality of traces, and the traces are electrically connected to the conductive pads;
  • the orthographic projection area of at least part of the traces on the substrate 1 overlaps with the third light-transmitting area T3.
  • overlap and overlap area both mean at least partial overlap.
  • part of the third light-transmitting region T3 and part of the first light-transmitting region T1 are arranged in communication, and/or, part of the third light-transmitting region T3 and part of the second light-transmitting region T3 Zone T2 connectivity settings.
  • the scenario includes three scenarios:
  • part of the third light-transmitting region T3 is communicated with part of the first light-transmitting region T1.
  • the first conductive layer 2 includes the first wiring 21, the second wiring 22 and the conductive pad group W, and the conductive pad group W includes the first conductive pad H1 and the second conductive pad H2 ;
  • part of the third light-transmitting area T3 and part of the first light-transmitting area T1 are connected to form a light-transmitting area marked as T1+T3 in FIG. 3a and FIG. 3b.
  • the orthographic projections of the first conductive pad H1 and the second conductive pad H2 on the substrate 1 both fall into the first light-transmitting area T1; At least partially overlapping, the orthographic projection of the second wiring 22 on the substrate 1 at least partially overlaps with the third light-transmitting region T3.
  • the orthographic projection of the components 3 on the substrate 1 falls within the first light-transmitting region T1 .
  • the first conductive layer 2 includes the first wiring 21, the second wiring 22 and the conductive pad group W, and the conductive pad group W includes the first conductive pad H1 and the second conductive pad H2 ;
  • part of the third light-transmitting area T3 and part of the first light-transmitting area T1 are connected to form a light-transmitting area marked as T1+T3 in FIG. 4a and FIG. 4b whose projected shape is rectangular.
  • the orthographic projections of the first conductive pad H1 and the second conductive pad H2 on the substrate 1 both fall into the first light-transmitting area T1; Partially overlapping, the orthographic projection of the second wiring 22 on the substrate 1 partially overlaps with the third light-transmitting region T3; the orthographic projection of the component 3 on the substrate 1 falls within the first light-transmitting region T1.
  • the first conductive layer 2 includes the first wiring 21, the second wiring 22 and the conductive pad group W, and the conductive pad group W includes the first conductive pad H1 and the second conductive pad H2 ;
  • part of the third light-transmitting area T3 and part of the first light-transmitting area T1 are connected to form a light-transmitting area marked as T1+T3 in FIG. 5a and FIG. 5b whose projected shape is rectangular.
  • the orthographic projection of the first conductive pad H1 on the substrate 1 partially overlaps the first light-transmitting region T1
  • the orthographic projection of the second conductive pad H2 on the substrate 1 partially overlaps the first light-transmitting region T1
  • the first The orthographic projection of the wiring 21 on the substrate 1 partially overlaps the third light-transmitting area T3, and the orthographic projection of the second wiring 22 on the substrate 1 partially overlaps the third light-transmitting area T3
  • the component 3 is on the substrate 1
  • the orthographic projection on is partially overlapped with the first transparent region T1.
  • the first conductive layer 2 includes the first wiring 21, the second wiring 22 and the conductive pad group W, and the conductive pad group W includes the first conductive pad H1 and the second conductive pad H2 ;
  • part of the third light-transmitting area T3 and part of the first light-transmitting area T1 are connected to form a light-transmitting area marked as T1+T3 in FIG. 6a and FIG. 6b whose projected shape is polygonal.
  • the orthographic projections of the first conductive pad H1 and the second conductive pad H2 on the substrate 1 both fall into the first light-transmitting area T1; At least partially overlapping, the orthographic projection of the second wiring 22 on the substrate 1 at least partially overlaps the third light-transmitting region T3; the orthographic projection of the component 3 on the substrate 1 falls within the first light-transmitting region T1.
  • the first conductive layer 2 includes the third wiring 23, the fourth wiring 24, the fifth wiring 25, the sixth wiring 26 and the conductive pad group W, the conductive pad group W Including the third conductive pad H3, the fourth conductive pad H4, the fifth conductive pad H5 and the sixth conductive pad H6; in a local area of the array substrate, part of the third light transmission area T3 and part of the first light transmission area T1 are arranged in communication, A light-transmitting region whose projected shape is rectangular as marked as T1+T3 in FIG. 7a and FIG. 7b is formed.
  • the orthographic projections of the third conductive pad H3, the fourth conductive pad H4, the fifth conductive pad H5 and the sixth conductive pad H6 on the substrate 1 all fall into the first light-transmitting area T1, and the third wiring 23 and the sixth conductive pad
  • the orthographic projections of the fifth wiring 25 on the substrate 1 overlap at least partially with the respective third light-transmitting regions T3, and the orthographic projections of the fourth wiring 24 and the sixth wiring 26 on the substrate 1 overlap with the third light-transmitting regions T3 respectively. It partially overlaps with the third light-transmitting region T3.
  • the orthographic projection of the component 3 on the substrate 1 falls within the first light-transmitting region T1.
  • the first conductive layer 2 includes the third wiring 23, the fourth wiring 24, the fifth wiring 25, the sixth wiring 26 and the conductive pad group W, the conductive pad group W Including the third conductive pad H3, the fourth conductive pad H4, the fifth conductive pad H5 and the sixth conductive pad H6; in a local area of the array substrate, part of the third light transmission area T3 and part of the first light transmission area T1 are arranged in communication, A light-transmitting region whose projected shape is a rectangle marked as T1+T3 in FIG. 9a and FIG. 9b is formed.
  • the orthographic projections of the third conductive pad H3, the fourth conductive pad H4, the fifth conductive pad H5 and the sixth conductive pad H6 on the substrate 1 all fall into the first light-transmitting area T1, and the third wiring 23, the The orthographic projections of the four wires 24 , the fifth wire 25 and the sixth wire 26 on the substrate 1 partially overlap with the third light-transmitting region T3 respectively.
  • the orthographic projection of the component 3 on the substrate 1 falls within the first light-transmitting region T1.
  • the first conductive layer 2 includes the third wiring 23, the fourth wiring 24, the fifth wiring 25, the sixth wiring 26 and the conductive pad group W, the conductive pad group W Including the third conductive pad H3, the fourth conductive pad H4, the fifth conductive pad H5, and the sixth conductive pad H6; in a local area of the array substrate, part of the third light-transmitting region T3 and part of the first light-transmitting region T1 are arranged in communication, A light-transmitting region whose projected shape is rectangular as marked as T1+T3 in FIG. 10a and FIG. 10b is formed.
  • the orthographic projections of the third conductive pad H3, the fourth conductive pad H4, the fifth conductive pad H5 and the sixth conductive pad H6 on the substrate 1 all fall into the first light-transmitting area T1, and the third wiring 23, the The orthographic projections of the fourth wiring 24 and the fifth wiring 25 on the substrate 1 at least partially overlap the third light-transmitting region T3; the orthographic projections of the sixth wiring 26 on the substrate 1 partially overlap the third light-transmitting region T3 stack.
  • the orthographic projection of the component 3 on the substrate 1 falls within the first light-transmitting region T1.
  • the projection shapes of the first wiring 21 and the second wiring 22 on the substrate 1 are both strip shapes; or, referring to FIG. 6a and FIG. 6b As shown, the projection shapes of the first wiring 21 and the second wiring 22 on the substrate 1 are L-shaped.
  • the second trace 22 includes a partial line segment 222 extending in the vertical direction and a line segment 221 extending in the horizontal direction.
  • the structures of the first trace 21 and the second trace 22 are similar, and the projection shapes of the two are All are L-shaped.
  • the first routing 21 and the second routing 22 may both include two intersecting line segments, and the intersection angle may be determined according to actual conditions, which is not limited here.
  • part of the third light-transmitting region T3 and part of the second light-transmitting region T2 are arranged in communication.
  • the second conductive layer 2 includes the eighth wiring 28, the first conductive pad group W1 and the second conductive pad group W2;
  • the orthographic projection on 1 falls into a first light-transmitting area T1, and the orthographic projection of the second conductive pad group W2 on the substrate 1 falls into another first light-transmitting area T1, and the two first light-transmitting areas T1 are connected.
  • the second light transmission area T2 is formed; the orthographic projection of the eighth wiring 28 on the substrate 1 falls into the third light transmission area T3, and the third light transmission area T3 and the second light transmission area T2 are connected.
  • part of the third light-transmitting region T3 is connected to part of the first light-transmitting region T1 , and part of the third light-transmitting region T3 is connected to part of the second light-transmitting region T2 .
  • the orthographic projection of the first conductive pad group W1 on the substrate 1 falls into a first light-transmitting region T1, and the second conductive pad group W2 on the substrate 1
  • the orthographic projection falls into another first light-transmitting area T1, and the two first light-transmitting areas T1 are connected to form the second light-transmitting area T2;
  • T3 is partially overlapped, and the third light-transmitting area T3 is connected to the second light-transmitting area T2;
  • the orthographic projection of the third conductive pad group W3 on the substrate 1 falls into a first light-transmitting region T1
  • the orthographic projection of the ninth wiring 29 on the substrate 1 falls into the third light-transmitting region T3 Partially overlapping; the first light-transmitting region T1 is communicated with the third light-transmitting region T3.
  • the light-transmitting region with a larger size can be manufactured, and the problem of high difficulty in the preparation process caused by the too small size of the light-transmitting region is avoided.
  • Fig. 3a, Fig. 4a, Fig. 5a, Fig. 6a, Fig. 7a, Fig. 8a, Fig. 9a, and Fig. 10a are respectively eight kinds of front views from the array substrate;
  • Fig. 3b is a back view corresponding to Fig. 3a
  • Fig. 4b is a back view corresponding to Fig. 4a
  • Fig. 5b is a back view corresponding to Fig. 5a
  • Fig. 6b is a back view corresponding to Fig. 6a
  • Fig. 7b is a back view corresponding to Fig.
  • Figure 8b is a rear view corresponding to Figure 8a
  • Figure 9b is a rear view corresponding to Figure 9a
  • Figure 10b is a rear view corresponding to Figure 10a.
  • At least part of the back surface of the conductive pad can be leaked, and other structures around the conductive pad can also be leaked.
  • other structures here may include traces, drive lines or components 3 connected to the conductive pads.
  • all the small-sized light-transmitting regions are connected together to form a whole light-transmitting region T. It can be understood that all the film layers in the substrate 1 are made of light-transmitting materials. make.
  • the array substrate may include two conductive layers as shown in Figure 14a, Figure 14b, Figure 15a and Figure 15b, the first conductive layer Layer 2 and the second conductive layer 102 (or 1021 ) together constitute a conductive pattern.
  • the first conductive layer 2 is arranged closer to the component 3 than the second conductive layer 102 (or 1021), at this time, the thickness of the first conductive layer 2 can be 0.3 ⁇ m, 0.5 ⁇ m, 0.6 ⁇ m or 0.9 ⁇ m, 2.7 ⁇ m ⁇ m, 3.6 ⁇ m, 5 ⁇ m.
  • the base 1 includes a substrate 100 and a second conductive layer 102 located on the substrate 100, and the second conductive layer 102 is insulated from the first conductive layer 2;
  • the second conductive layer 102 includes a plurality of driving lines arranged along the first direction and extending along the second direction; the orthographic projection of the third light-transmitting region T3 on the substrate 100 falls into the two adjacent driving lines on the substrate. The area between orthographic projections on 100.
  • the driving lines can be divided into a first driving line (VLED), a second driving line (GND) and a third driving line (PWR).
  • VLED first driving line
  • GND second driving line
  • PWR third driving line
  • At least part of the third light-transmitting regions T3 are arranged along the first direction and extend along the second direction.
  • the first direction may be a vertical direction or a column direction
  • the second direction may be a horizontal direction or a row direction; of course, the first direction may also be a horizontal direction or a row direction, and the second direction may also be a vertical direction or a column direction.
  • the material of the second conductive layer 102 may include any one of copper, aluminum, nickel, molybdenum and titanium or a combination of several metals arranged in layers.
  • the second conductive layer 102 may include a molybdenum-niobium alloy layer, a copper metal layer, and a protective layer that are sequentially stacked.
  • the protective layer may include a copper-nickel alloy (CuNi), a nickel-gold layer, or an indium oxide layer. Any of tin (Indium Tin Oxide, referred to as ITO).
  • the molybdenum-niobium alloy layer plays the role of improving the adhesion between the copper metal and the film layer near the substrate, and the protective layer plays the role of preventing the oxidation of the copper metal.
  • the thickness range of the second conductive layer 102 may be 0.5-10 ⁇ m, for example, the thickness may be 0.5 ⁇ m, 1 ⁇ m, 1.8 ⁇ m, 2.7 ⁇ m or 10 ⁇ m.
  • the material of the second conductive layer 102 may include a light-transmitting material, such as indium tin oxide (ITO).
  • ITO indium tin oxide
  • the second conductive layer when the material of the second conductive layer is opaque, the second conductive layer is marked as 102, such as the marks in Figure 14a and Figure 15a; when the material of the second conductive layer When light is transmitted, the second conductive layer is marked as 1021, such as the marks in Fig. 14b and Fig. 15b.
  • the distance between the contour of the orthographic projection of the light-transmitting region T on the first conductive layer 2 and the conductive pad is in the range of 0-200 ⁇ m.
  • the light transmission area T may include any one or more of the first light transmission area T1 , the second light transmission area T2 and the third light transmission area T3 .
  • the material of the part of the base 1 located in the light-transmitting region T includes a light-transmitting material, and/or, the part of the substrate located in the light-transmitting region T includes a hollow structure.
  • the light transmission area T mentioned in this application refers to any one of the first light transmission area T1, the second light transmission area T2 and the third light transmission area T3; or, the first light transmission area T1, A region formed by multiple communication arrangements in the second light-transmitting region T2 and the third light-transmitting region T3.
  • the first light-transmitting area T1 overlaps with the orthographic projection area of the conductive pad on the substrate 1; at least two first light-transmitting areas T1 are connected to form a second light-transmitting area T2; the third light-transmitting area T3 and The orthographic projection areas of some traces on the substrate 1 overlap.
  • the contour of the orthographic projection of the light-transmissive region T on the first conductive layer 2 falls between the conductive pads.
  • the distance between them is 0 ⁇ m.
  • the contour of the orthographic projection of the light-transmissive region T on the first conductive layer 2 and the conductive pad The distance is greater than 0 ⁇ m and less than or equal to 200 ⁇ m.
  • the contour of the orthographic projection of the light-transmitting region (T1+T3) on the first conductive layer 2 surrounds the outer contour of the third conductive pad H3, and the light-transmitting region is on the first conductive layer.
  • the direct distance d1 between the contour of the orthographic projection on 2 and the third conductive pad H3 is greater than 0 ⁇ m and less than or equal to 200 ⁇ m; for example, d1 can be 10 ⁇ m, 30 ⁇ m, 50 ⁇ m, 100 ⁇ m, 150 ⁇ m or 200 ⁇ m.
  • the projected contour of the light-transmitting region (T1+T3) on the first conductive layer 2 surrounds the outer contour of the first conductive pad H1, and the light-transmitting region is on the first conductive layer 2.
  • the distance d2 between the contour of the orthographic projection and the first conductive pad H1 along the horizontal direction is greater than 0 ⁇ m and less than or equal to 200 ⁇ m; the contour of the orthographic projection of the light-transmitting region on the first conductive layer 2 is along the vertical direction to the first
  • the distance d2 between the conductive pads H1 is greater than 0 ⁇ m and less than or equal to 200 ⁇ m.
  • the array substrate further includes a plurality of components 3 , and one component 3 is electrically connected to the same group W of conductive pads.
  • the components 3 may include any one or more of light-emitting devices, sensor devices, micro-drive chips or other types of devices. It can be understood that the number of different types of devices is different, or, Different types of devices have different array arrangement densities.
  • the light emitting device may be a submillimeter light emitting diode (Mini Light Emitting Diode, English abbreviation is Mini LED) or a micro light emitting diode (Micro Light Emitting Diode, English abbreviation is Micro LED), which is not limited here.
  • Mini LED Mini Light Emitting Diode
  • Micro LED Micro Light Emitting Diode
  • the plurality of components 3 may all be blue-emitting submillimeter light-emitting diodes or miniature light-emitting diodes, or the plurality of components 3 may include three types of light-emitting diodes that emit red light, green light, and blue light or tiny light-emitting diodes.
  • a component 3 may include at least one soldering foot, a set of conductive pad groups W may include at least one conductive pad, and the soldering legs of the component 3 and the conductive pads of the conductive pad group W are electrically connected.
  • a component 3 including three solder feet can be electrically connected to a conductive pad group W including two conductive pads; it can be understood that a component 3 corresponds to a group of conductive pads W, but the component 3
  • the number of soldering feet in the component 3 can be the same as the number of conductive pads in the conductive pad group W, or the number of soldering legs in the component 3 can be different from the number of conductive pads in the conductive pad group W, which can be determined according to actual conditions.
  • a plurality of conductive pad groups are arranged in an array, as shown in FIG. 11c, the conductive pad includes a metal layer 202 and a connection layer 203 on the metal layer 202;
  • connection layer 203 is located between the metal layer 202 and the component 3, and the metal layer 202 is connected to the component 3 through the connection layer 203;
  • connection layer 203 includes an intermetallic compound (IMC, Intermetallic Compound), and the form of the intermetallic compound is At least one of block-like structure M1 as shown in FIG. 11e , shell-like structure, dendritic structure or rice grain-like structure M2 as shown in FIG. 11d .
  • IMC Intermetallic Compound
  • solder layer 201 shown in FIG. 11a by printing the solder layer 201 shown in FIG. 11a on the first conductive layer 2, referring to FIG. 11b, the solder layer 201 is melted and diffused by heating, and the melted solder layer 201 wets the first A part of the conductive layer 2 is diffused with the material of the first conductive layer 2. During the solder reflow process, the interface between the solder layer 201 and the second conductive layer 2 forms a connection layer 203 as shown in FIG. 11c.
  • the intermetallic compound includes Cu 6 Sn 5 , Cu 3 Sn , Ni 3 Sn 4 , (Cu, Ni) 6 Sn 5 , (Ni, Cu) 3 Sn 4 or Ag 3 Sn Any one or more.
  • (Cu, Ni) 6 Sn 5 is a material with Cu 6 Sn 5 as the main component, in which, some copper (Cu) atoms in Cu 6 Sn 5 are replaced by nickel (Ni) atoms;
  • (Ni, Cu) 3 Sn 4 is a material mainly composed of Ni 3 Sn 4 , wherein part of nickel (Ni) atoms in Ni 3 Sn 4 are replaced by copper (Cu) atoms.
  • the material of the metal layer 202 includes copper (Cu)
  • the material of the solder layer 201 includes SnAg or SnAgCu.
  • the soldering layer 201 can be prefabricated on each soldering leg of the component 3 , or can also be printed on each conductive pad.
  • the conductive pad in order to observe the form of the intermetallic compound of the connection layer 203 through the light-transmitting region when detecting from the back, to determine whether the connection between the conductive pad and the component is poor, the conductive pad (or the first conductive layer 2)
  • the thickness range along the direction perpendicular to the substrate 1 can be 0.3 ⁇ m-5 ⁇ m.
  • the thickness of the metal layer 202 is relatively thin, which will not block the form of the intermetallic compound in the connection layer 203, so that the user can detect through the back Technically and accurately judge the connection status between the component 3 and each conductive pad.
  • the thickness of the conductive pad (or the first conductive layer 2 ) along the direction perpendicular to the substrate 1 can be 0.3 ⁇ m, 0.5 ⁇ m, 0.6 ⁇ m, 0.7 ⁇ m, 0.8 ⁇ m, 0.9 ⁇ m, 1.0 ⁇ m, 1.5 ⁇ m, 1.8 ⁇ m , 2.0 ⁇ m, 2.5 ⁇ m, 2.7 ⁇ m, 3.6 ⁇ m, 4.5 ⁇ m or 5 ⁇ m.
  • the array substrate further includes a soldering layer, the soldering layer is located between the soldering feet of the component and the conductive pad, and the soldering layer includes a soldering material;
  • the morphology of the intermetallic compound (IMC) is a rice grain structure M2 as shown in Fig. 11d.
  • the array substrate further includes a soldering layer, the soldering layer is located between the soldering feet of the component and the conductive pad, and the soldering layer includes a soldering material;
  • the morphology of the intermetallic compound (IMC) is one or more of a bulk structure M1, a conchoidal structure, or a dendritic structure as shown in Fig. 11e kind.
  • the welding material may be solder.
  • the material of the suppression layer includes nickel (Ni) and/or gold (Au).
  • the rice grain structure M2 presented by the intermetallic compound (IMC) is related to the crystal growth process of the solder material and the material of the second conductive layer
  • the bulk structure M1 presented by the intermetallic compound (IMC) is related to the solder material, the second conductive layer
  • the material of the two conductive layers is related to the crystal growth process of the material of the inhibiting layer; due to the above two cases, the crystal forms of the crystals generated in the connection layer 203 are different, and/or the sizes of the crystals are different, resulting in the formation of the connection layer 203
  • the intermetallic compounds (IMCs) exhibit different morphologies.
  • the block structure may be a gap formed between a part of the connection layer 203 and a part of the metal layer 202, so that a block-like cavity structure appears in the X-ray image; Alternatively, it may also be a crystal cluster aggregate formed by the intermetallic compound in the connection layer 203, so that the bulk structure M1 as shown in FIG. 11e may also appear under a microscope.
  • the base 1 includes a substrate 100, and a buffer layer 101, a second conductive layer 102, a first insulating layer 103, a first flat layer 104, and a second insulating layer 105 that are sequentially stacked on the substrate 100; wherein, The materials of the buffer layer 101, the first insulating layer 103, the first flat layer 104 and the second insulating layer 105 are all light-transmitting materials; the material of the part of the second conductive layer 102 located in the light-transmitting region T is a light-transmitting material, or, The part of the second conductive layer 102 located in the light-transmitting region T is a hollow structure.
  • the materials of the other film layers in the substrate 1 except the second conductive layer 102 are all light-transmitting materials, and the second conductive layer 102 is located in the light-transmitting region T. Some are openworked.
  • the array substrate shown in FIG. 14a is a cross-sectional view along the A1A2 direction in FIG. 6a.
  • the array substrate shown in FIG. 15a is a cross-sectional view along the B1B2 direction in FIG. 4a.
  • materials of all film layers in the substrate 1 are light-transmitting materials.
  • the base 1 includes a substrate 100 and a buffer layer 101, and the array substrate includes only one conductive layer (first conductive layer 2), the first conductive layer Layer 2 is used to form a conductive pattern.
  • materials of all film layers in the substrate 1 are light-transmitting materials.
  • the array substrate further includes a third insulating layer 106 and a second flat layer 107 on the first conductive layer 2, wherein the third insulating layer 106 and the second flat layer
  • the orthographic projection of the layer 107 on the substrate 1 does not overlap with the orthographic projection of the conductive pad group W on the substrate 1 .
  • the third insulating layer 106 and the second planar layer 107 are provided with an opening area, the opening area exposes the area of the conductive pad group W, and the component 3 is located in the opening area and is electrically connected with the conductive pad group W.
  • the array substrate further includes a reflective layer 108, the reflective layer 108 is located on the second planar layer 107 except for the opening area, and the positive surface of the reflective layer 108 on the substrate 1
  • the projection and the orthographic projection of the component 3 on the substrate 1 do not overlap each other, and the orthographic projection of the reflective layer 108 on the substrate 1 is located within the orthographic projection of the second flat layer 107 on the substrate 1 .
  • the component device 3 includes at least a light emitting device.
  • the material of the reflective layer 108 may include any one or a combination of white ink, silicon-based white glue, or reflective sheet.
  • the array substrate further includes an auxiliary reflection part 109, the auxiliary reflection part 109 is located at the side wall of the reflection layer 108 close to the component 3, and the orthographic projection of the auxiliary reflection part 109 on the substrate 1 is the same as that of the reflection layer 108 on the substrate 1.
  • the orthographic projections on are partially overlapped. In this way, through the joint action of the reflective layer 108 and the auxiliary reflective portion 109, the amount of light output from the array substrate in a direction perpendicular to the plane where the substrate 1 is located can be further increased, thereby improving the light output efficiency of the array substrate.
  • the material of the auxiliary reflective part 109 includes silicon-based white glue, and the color of the silicon-based white glue is white, so that the color of the auxiliary reflective part 109 is roughly the same as that of the reflective layer 108, so as to ensure that the reflectivity of the auxiliary reflective part 109 to light is close to The reflectivity of the reflective layer 108 to light.
  • the array substrate further includes a plurality of packaging units 4 corresponding to the components 3, the orthographic projections of the packaging units 4 on the substrate 1 cover the orthographic projections of the components 3 on the substrate 1, and the packaging units 4 on the substrate The orthographic projection on 1 partially overlaps the orthographic projection of the reflective layer 108 on the substrate 1 .
  • each packaging unit 4 wraps a component 3 .
  • the encapsulation unit 4 plays the role of encapsulation and protection for the components 3, it can also further adjust the light-emitting device included in the components 3 by designing its surface shape away from the substrate 1, for example, making it have a convex lens-like surface. Light angle.
  • the embodiment of the present application provides a light emitting device, as shown in FIG. 17 , including the above array substrate 400 .
  • the light emitting device can be used as a backlight device, or can also be used as a display device. Specifically, if the multiple components 3 in the light emitting device include light emitting devices that emit light of a single color, the above light emitting device can be used as a backlight device; if the multiple components 3 in the light emitting device include light emitting devices that emit light of different colors Devices, such as three light-emitting devices that emit red light, green light and blue light, then the above-mentioned light-emitting device can be used as a display device.
  • the array substrate further includes a light emitting film 406 .
  • the array substrate further includes a plurality of support pillars 401, and the plurality of support pillars 401 are used to support a plurality of optical films 406.
  • the optical film 406 includes a diffusion plate 402, a quantum dot The film 403, the diffusion sheet 404 and the composite film 405, wherein the diffusion plate 402 and the diffusion sheet 404 can improve the light shadow generated by the array substrate and improve the display quality of the light emitting device.
  • the quantum dot film 403 converts the blue light into white light under the excitation of the blue light emitted by the light-emitting device in the array substrate, which can improve the utilization rate of light energy of the array substrate 400 .
  • the composite film 405 is used to increase the brightness of the light emitted from the diffusion sheet 404.
  • the multiple components 3 in the light emitting device include a light emitting device that emits light of a single color, and the above light emitting device can be used as a backlight device as an example for illustration.
  • a display panel 407 is provided on the light emitting side of the light emitting device, and a display device as shown in FIG. 17 can be formed.
  • each first light-transmitting region T1 includes a light-transmitting material and/or a hollow structure, since the substrate 1 is located in the first light-transmitting region
  • the transmittance of the part of T1 is greater than or equal to the first preset value, so that part of the backside of each conductive pad can be seen from the part of the substrate 1 located in the first light-transmitting region T1, which can be directly determined by backside detection technology
  • the poor connection between each conductive pad and the component 3 can be directly determined through the back detection technology, and the array substrate with poor connection can be intercepted and repaired to improve the reliability of the product sex.
  • the embodiment of the present application provides a method for preparing an array substrate, which is applied to prepare the above-mentioned array substrate, as shown in FIG. 18 , the method includes:
  • the substrate 1 includes a plurality of first light-transmitting regions T1.
  • the material of the part of the substrate 1 located in the first transparent region T1 includes a transparent material, and/or, the part of the substrate 1 located in the first transparent region T1 includes a hollow structure.
  • the light-transmitting material may be silica gel, ultraviolet curing glue, silicon nitride or silicon oxide.
  • the first conductive layer 2 includes a plurality of conductive pad groups W, the conductive pad group W includes at least one conductive pad, and the orthographic projection area of the conductive pad on the substrate 1 is the same as the first conductive pad group W.
  • the first preset value is greater than or equal to 50%.
  • the first preset value may include 50%, 55%, 60%, 70%, 80%, and 85%, which may be determined according to different product designs and transmittance requirements, and there is no limitation here.
  • the overlapping area between the orthographic projection area of the conductive pad on the substrate 1 and the first transparent region T1 means that the orthographic projection area of the conductive pad on the substrate 1 at least partially overlaps with the first transparent region T1 . It can be understood that if the orthographic projection area of the conductive pad on the substrate 1 overlaps with the first light-transmitting area T1 , there is no limitation on the size of the overlapping area, which can be determined according to the requirements of different products.
  • the conductive pad may be a pad.
  • the area of the overlapping area accounts for at least half of the area of the orthographic projection area of the conductive pad on the substrate 1 .
  • the area of the overlapping area accounts for at least half of the area of the orthographic projection area of the conductive pads (such as H1 and H2 in FIG.
  • the region T1 leaks at least half of the backside of each conductive pad, thereby improving the accuracy of determining whether there is a poor connection between the component 3 and the conductive pad in the backside detection technology.
  • step S902 after forming the first conductive layer 2 on the substrate 1, the method further includes:
  • the component 3 includes a component body 31, a first soldering leg 32 and a second soldering leg 33; correspondingly, the conductive pad group W includes a first conductive pad H1 and a second conductive pad H1. Pad H2; the first soldering leg 32 is electrically connected to the first conductive pad H1, and the second soldering leg 33 is electrically connected to the second conductive pad H2.
  • the array substrate further includes a soldering layer 201, and the soldering layer 201 is located between the components 3 and the first conductive layer 2;
  • solder layer 201 shown in FIG. 11a by printing the solder layer 201 shown in FIG. 11a on the conductive pad, referring to FIG. 11b, the solder layer 201 is melted and diffused by heating, and the melted solder layer 201 wets the first conductive layer 2. , and diffuse with the material of the first conductive layer 2, during the process of reflow soldering, the interface between the soldering layer 201 and the second conductive layer 2 forms a connection layer 203 as shown in Figure 11c, thereby completing the soldering.
  • each first light-transmitting region T1 includes a light-transmitting material and/or a hollow structure.
  • the transmittance of the part of the light zone T1 is greater than or equal to the first preset value, so that part of the backside of each conductive pad can be seen from the part of the substrate 1 located in the first light-transmitting zone T1, and then can be detected through the backside detection technology. Directly determine the bad condition of each conductive pad. After the production of the component 3 is completed, the poor connection between each conductive pad and the component 3 can be directly determined through the back detection technology, and the array substrate with poor connection can be intercepted and repaired to improve the product. reliability.
  • the embodiment of the present application provides a detection method.
  • the array substrate includes a plurality of components 3, and one component 3 is electrically connected to each conductive pad in the same group of conductive pads W, as shown in FIG. 19 ,
  • the method includes:
  • the target image refers to the image collected from the back of the array substrate through the first light-transmitting region T1, including at least one conductive pad; it can be understood that the target image is the part of the first conductive layer 2 that contains the conductive pad , and the image shows the topography of each conductive pad away from the surface of the component 3 .
  • Figures 13a and 13b show two different target images.
  • the target image is obtained through detection and shooting of AOI (Automated Optical Inspection, automatic optical inspection) equipment, of course, it can also be other equipment, and the embodiment of the application uses AOI equipment as an example for illustration.
  • AOI Automatic Optical Inspection, automatic optical inspection
  • Poor connection may include poor soldering, and poor soldering includes problems such as false soldering of conductive pads, damaged conductive pads, and corrosion of conductive pads.
  • the parameter information includes the area of the orthographic projection of the connection layer 203 of the conductive pad on the substrate 1 and the area of the orthographic projection of each solder leg of the component 3 on the substrate 1 .
  • the parameter information includes a qualified template image for connecting the component 3 to the conductive pad.
  • AOI inspection will be performed on the front of the array substrate to determine the accuracy of the fixed position of each component 3; together, and then carry out the above-mentioned AOI back detection process.
  • the target image is collected from the back of the array substrate through the light-transmitting first light-transmitting region T1, according to the shape of the intermetallic compound in the connection layer 203 of each conductive pad in the target image Determine whether the components 3 and the conductive pads are poorly connected by using the appearance characteristics and the expansion area of the connection layer 203 relative to the solder pins of each component 3, which solves the problem in the related art that the poor connection of the array substrate cannot be accurately intercepted through AOI front detection .
  • a lighting test is also performed, and some array substrates with poor connections are further repaired according to the lighting test structure.
  • a lighting test is also performed, and some array substrates with poor connections are further repaired according to the lighting test structure.
  • one component 3 is correspondingly connected to one conductive pad group W, wherein, the number of solder feet included in the component 3 and the number of conductive pads included in the conductive pad group W same.
  • the parameter information includes the area of the orthographic projection of the connection layer 203 of the conductive pad on the substrate 1 and the area of the orthographic projection of each solder leg of the component 3 on the substrate 1;
  • S802 according to the parameter information of each conductive pad in the target image, determine whether the connection between the component and the conductive pad is poor, specifically including:
  • connection layer of at least one conductive pad in the conductive pad group on the substrate is smaller than the second preset value compared with the area of the orthographic projection of the solder pin on the substrate, determine the connection between the component and the conductive pad bad.
  • the soldering material of the soldering layer 201 is positioned on each conductive pad (pad) in the first conductive layer 2 Part of the melting and diffusion occurs, and further forms the connection layer 203 as shown in Figure 11c. Since the welding material will diffuse, the size of the actually formed connection layer 203 is consistent with the size of the diffusion region of the welding material during the welding process. In practical applications, the welding material will spread around the area where the solder fillet is located, so the actual area of the formed connection layer 203 will be larger than the area of the contact surface between each solder fillet and the solder material.
  • Figures 13a and 13b show two different target images.
  • Fig. 13a is the target image of virtual welding
  • Fig. 13b is the target image of qualified welding.
  • FIG. 13a the block structure of the interlayer compound of the connection layer 203 formed in the solder-affected zone M of the first conductive pad H1 is not obvious, and the connection layer 203 in the solder-affected zone M is expanded outwards.
  • the range is very small, indicating that the melting and diffusion effect of the solder material is not good when heated, and it can be determined that there is a problem of poor soldering between the pad corresponding to the first conductive pad H1 and the component 3 .
  • Fig. 13a is the target image of virtual welding
  • Fig. 13b is the target image of qualified welding.
  • connection layer 203 in the welding-affected zone M presents a massive structure, and the area of the welding-affected zone M is relatively large, and the outward expansion traces of the connection layer 203 in the welding-affected zone M are obvious. It can be determined that the welding between the pad corresponding to the first conductive pad H1 and the component 3 is qualified.
  • connection layer 203 is located in the weld-affected zone M, and the connection layer 203 is a part showing a block structure in FIG. 13a and FIG. 13b .
  • the above-mentioned second preset value may include 30%, 35%, 40%, 45% or 50%.
  • the second preset value may also include other values, which may be specifically determined according to the type of welding material, welding temperature and welding time, which is not limited here.
  • connection layer 203 corresponding to each solder leg of the component 3 is 30% larger than the design size area of the solder leg, it is confirmed that the soldering of the component 3 is qualified.
  • connection layer 203 when the size of the connection layer 203 is 20 ⁇ m, 30 ⁇ m, 40 ⁇ m, 50 ⁇ m, 80 ⁇ m or 100 ⁇ m larger than the size of the solder fillets, it is determined that one of the solder fillets of the component is qualified for soldering.
  • each connecting layer 203 is expanded 40um outward compared with each welding leg, and the diameter of the connecting layer 203 can be 130um , confirm that the LED chip welding is qualified.
  • the detection method of the present application is aimed at products in which the number of soldering legs of the component 3 is the same as the number of conductive pads of the conductive pad group W, and each soldering leg is electrically connected to each conductive pad in one-to-one correspondence.
  • the number of soldering feet of the component 3 is different from the number of conductive pads of the conductive pad group W, the number of conductive pads that need to be connected to the soldering legs of the component 3 in each conductive pad group W can be determined according to the actual situation , and then by a method similar to the detection method of the present application, judge the welding condition of each conductive pad connected to the soldering leg of the component 3, and then judge whether there is a problem of poor connection between the component 3 and each conductive pad.
  • the parameter information includes a qualified template image for connecting components and conductive pads
  • the template image and the target image were taken at the same shooting magnification.
  • S802 according to the parameter information of each conductive pad in the target image, determining whether the connection between the component 3 and the conductive pad is poor includes:
  • connection layer 203 when the welding is qualified, an intermetallic compound is formed in the connection layer 203, and the intermetallic compound presents one or more of a block structure M1, a rice grain structure M2, a shell structure or a dendritic structure.
  • the intermetallic compound presents one or more of a block structure M1, a rice grain structure M2, a shell structure or a dendritic structure.
  • the connection layer 203 of each conductive pad in the target image forms a characteristic topography with a block structure M1
  • the connection layer 203 expands
  • the area meets the requirements
  • the similarity between the target image and the template image is greater than or equal to the third preset value, indicating that the corresponding component 3 is qualified for welding with the conductive pad.
  • the connection layer 203 of each conductive pad in the target image does not form a characteristic topography with a block structure, or the formed area with a characteristic topography of a block structure is small (as shown in FIG. 13 a )
  • the target When the similarity between the image and the template image is less than the third preset value, it indicates that the corresponding component 3 is poorly welded to the conductive pad.
  • the third preset value may be 40%, 45% or 50%.
  • the target image is collected from the back of the array substrate through the light-transmitting first light-transmitting region T1, according to the shape of the intermetallic compound in the connection layer 203 of each conductive pad in the target image Determine whether the components 3 and the conductive pads are poorly connected by using the appearance characteristics and the expansion area of the connection layer 203 relative to the solder pins of each component 3, which solves the problem in the related art that the poor connection of the array substrate cannot be accurately intercepted through AOI front detection .
  • the position of the conductive pad is directly repaired by the repair equipment; when a damage to the conductive pad is detected, manual inspection is required again to determine the damaged area, and when the damaged area is less than or equal to the first
  • four preset values it can be considered that the damage does not affect the normal use of the array substrate, and when the damaged area is greater than the fourth preset value, the array substrate is scrapped.
  • the fourth preset value may include 5%, 10%, 15% or 20%.

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Abstract

本申请提供了一种阵列基板及其检测方法、发光装置，涉及显示技术领域，该阵列基板包括：基底，所述基底包括多个第一透光区；位于所述基底上的第一导电层；所述第一导电层包括多个导电垫组，所述导电垫组包括至少一个导电垫；其中，所述导电垫在所述基底上的正投影区域与所述第一透光区存在交叠区；所述基底位于所述第一透光区的部分的透过率大于或者等于第一预设值。本申请提供的阵列基板，通过基底位于第一透光区的部分可以看到各导电垫的背面，从而可以通过背面检测技术直接观测导电垫是否存在不良的问题，便于后续进行修改，进而提高产品的可靠性。

Description

阵列基板及其检测方法、发光装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其检测方法、发光装置。
背景技术
随着显示技术的快速发展，Mini LED(Mini Light Emitting Diode，次毫米发光二极管)和Micro LED(Micro Light Emitting Diode，微发光二极管)的显示产品引起人们广泛的关注。上述两种LED芯片的焊接过程是制备这两类显示产品的重要步骤，然而，LED芯片的焊接过程中极易出现虚焊问题，造成LED芯片与背板的导通不良，进而造成显示产品品质下降。
发明内容
本申请的实施例采用如下技术方案：
一方面，本申请的实施例提供了一种阵列基板，包括：
基底，所述基底包括多个第一透光区；
位于所述基底上的第一导电层；
所述第一导电层包括多个导电垫组，所述导电垫组包括至少一个导电垫；
其中，所述导电垫在所述基底上的正投影区域与所述第一透光区存在交叠区；所述基底位于所述第一透光区的部分的透过率大于或者等于第一预设值。
在本申请的一些实施例中，所述第一预设值大于或者等于50％。
在本申请的一些实施例中，所述交叠区的面积占所述导电垫在所述基底上的正投影区域的面积的至少一半。
在本申请的一些实施例中，所述导电垫在所述基底上的正投影区域的边缘位于所述第一透光区以内。
在本申请的一些实施例中，所述基底位于所述第一透光区的部分的材料包括透光材料，和/或，所述基底位于所述第一透光区的部分包括镂空结构。
在本申请的一些实施例中，至少两个所述第一透光区连通设置并构成第二透光区。
在本申请的一些实施例中，部分所述导电垫组在所述基底上的正投影区域与所述第二透光区存在交叠。
在本申请的一些实施例中，所述基底还包括多个第三透光区；所述第一导电层还包括多条走线，所述走线和所述导电垫电连接；
其中，至少部分所述走线在所述基底上的正投影区域与所述第三透光区存在交叠。
在本申请的一些实施例中，部分所述第三透光区和部分所述第一透光区连通设置，和/或，部分所述第三透光区和部分所述第二透光区连通设置。
在本申请的一些实施例中，所述基底包括衬底和位于所述衬底上的第二导电层，所述第二导电层和所述第一导电层绝缘设置；
其中，所述第二导电层包括沿第一方向排布且沿第二方向延伸的多条驱动线；所述第三透光区在所述衬底上的正投影落入相邻的两个所述驱动线在所述衬底上的正投影之间的区域。
在本申请的一些实施例中，至少部分所述第三透光区沿所述第一方向排布，且沿所述第二方向延伸。
在本申请的一些实施例中，透光区在所述第一导电层上的正投影的轮廓到所述导电垫之间的距离范围为0-200μm。
在本申请的一些实施例中，多个所述导电垫组阵列排布，所述导电垫包括金属层和位于所述金属层上的连接层；所述阵列基板还包括多个元器件，一个所述元器件与同一组所述导电垫组电连接；
其中，所述连接层位于所述金属层和所述元器件之间，且所述金属层通过所述连接层与所述元器件连接；所述连接层包括金属间化合物，所述金属间化合物的形态呈块状结构、贝壳状结构、树枝形结构或米粒状结构中的至少一种。
在本申请的一些实施例中，所述金属间化合物包括Cu 6Sn 5、Cu 3Sn、Ni 3Sn 4、(Cu、Ni) 6Sn 5、(Ni、Cu) 3Sn 4或Ag 3Sn中的任意一种或多种。
在本申请的一些实施例中，所述阵列基板还包括焊接层，所述焊接层位于所述元器件的焊脚和所述导电垫之间，所述焊接层包括焊接材料；
在所述焊接层和所述导电垫直接接触的情况下，所述金属间化合物的形态呈米粒状结构。
在本申请的一些实施例中，所述阵列基板还包括焊接层，所述焊接层位于所述元器件的焊脚和所述导电垫之间，所述焊接层包括焊接材料；
在所述焊接层和所述导电垫之间设置有抑制层的情况下，所述金属间化合物的形态呈块状结构、贝壳状结构或树枝形结构中的一种或多种。
在本申请的一些实施例中，所述基底包括衬底、以及位于所述衬底上依次层叠设置的缓冲层、第二导电层、第一绝缘层、第一平坦层和第二绝缘层；
其中，所述缓冲层、第一绝缘层、第一平坦层和第二绝缘层的材料均为透光材料；
所述第二导电层位于所述透光区的部分的材料为透光材料，或，所述第二导电层位于所述透光区的部分为镂空结构。
另一方面，本申请的实施例提供了一种发光装置，包括如上所述的阵列基板。
再一方面，本申请的实施例提供了一种检测方法，所述阵列基板包括多个元器件，一个所述元器件与同一组所述导电垫组中的各所述导电垫电连接，所述方法包括：
采集所述阵列基板的背面的目标图像；所述背面为所述基底远离所述导电垫的表面；
根据所述目标图像中各所述导电垫的参数信息，确定所述元器件与所述导电垫之间是否连接不良。
在本申请的一些实施例中，所述参数信息包括所述导电垫的连接层在所述基底上的正投影的面积和所述元器件的各焊脚在所述基底上的正投影的面积；
所述根据所述目标图像中各所述导电垫的参数信息，确定所述元器件与所述导电垫之间是否连接不良包括：
当所述导电垫组中各所述导电垫的所述连接层在所述基底上的投影面积相较所述焊脚在所述基底上的正投影的面积均大于或等于第二预设值时，确定所述元器件与所述导电垫之间连接合格；
当所述导电垫组中有至少一个所述导电垫的所述连接层在所述基底上的投影面积相较所述焊脚在所述基底上的正投影的面积小于所述第二预设值时，确定所述元器件与所述导电垫之间连接不良。
在本申请的一些实施例中，所述参数信息包括所述元器件与所述导 电垫连接合格的模板图像；
所述根据所述目标图像中各所述导电垫的参数信息，确定所述元器件与所述导电垫之间是否连接不良包括：
当所述目标图像中的所述导电垫与所述模板图像中的所述导电垫的相似度大于或等于第三预设值时，确定所述元器件与所述导电垫之间连接合格；
当所述目标图像中存在至少一个所述导电垫与所述模板图像中的所述导电垫的相似度小于所述第三预设值时，确定所述元器件与所述导电垫之间连接不良。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本申请实施例提供的一种相关技术中的焊盘与元器件焊接合格和虚焊的SEM对比图。
图2a-图2d为本申请实施例提供的四种不同阵列基板的结构示意图；
图3a-图10b为本申请实施例提供的十六种说明焊接区与透光区位置关系的阵列基板的结构示意图；
图11a-图11c为本申请实施例提供的连接层的形成过程的原理示意图；
图11d-图11e为本申请实施例提供的连接层的两种特征形貌的示意图；
图12为本申请实施例提供的又一种阵列基板的结构示意图；
图13a为本申请实施例提供的焊盘焊接不良的形貌特征图；
图13b为本申请实施例提供的焊盘焊接合格的形貌特征图；
图14a-图16b为本申请的实施例提供的六种不同的阵列基板的具体结构示意图；
图17为本申请的实施例提供的一种显示装置的结构示意图；
图18为本申请的实施例提供的一种阵列基板的制备方法流程图；
图19为本申请的实施例提供的一种阵列基板的检测方法流程图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
在本申请的实施例中，除非另有说明，“多个”的含义是两个或两个以上；术语“上”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的结构或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在本申请的实施例中，采用“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分，仅为了清楚描述本申请实施例的技术方案，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
目前，Mini LED和Micro LED发光器件均是通过焊接的方式固定 在基板中，无论是发光基板中的发光器件还是背光基板的发光器件，若有一个发光器件发生虚焊或者焊接不良，且未及时发现问题并进行修补，在封装工艺完成后使用的过程中该发光器件无法发光，此基板就可能会报废，这将产生巨大的成本损失，因此，虚焊的快速准确检测，进而及时进行修补，保证每一个发光器件的焊接合格，是整个Mini/Micro LED工艺路线中的重要步骤。
图1所示为相关技术中发光器件在焊接位置的SEM(Scanning Electron Microscope，扫描电子显微镜)图像，可以看到，一个焊盘(Pad)与元器件的一个焊脚焊接合格(OK)，而另一个焊盘(Pad)与元器件的另一个焊脚之间虚焊(NG)。
基于此，本申请的实施例提供了一种阵列基板，参考图2a所示，包括：
基底1，基底1包括多个第一透光区T1；
位于基底1上的第一导电层2；
第一导电层2包括多个导电垫组W，导电垫组W包括至少一个导电垫(例如图2a中的H1、H2)；
其中，导电垫在基底1上的正投影区域与第一透光区T1存在交叠区；基底1位于第一透光区T1的部分的透过率大于或者等于第一预设值。
在本申请的一些实施例中，第一预设值大于或者等于50％。
实际应用中，第一预设值可以包括50％，55％，60％，70％，80％，85％，具体可以根据不同产品的设计和透过率需求确定，这里不做限制。
导电垫在基底1上的正投影区域与第一透光区T1存在交叠区的含义为：导电垫在基底1上的正投影区域与第一透光区T1至少部分交叠。可以理解，导电垫在基底1上的正投影区域与第一透光区T1存在交叠的情况下，这里对于交叠区的大小不做限定，具体可以根据不同产品的需求确定。
示例性的，参考图8a和图8b所示，第一导电层2包括导电垫组W，导电垫组W包括第三导电垫H3、第四导电垫H4、第五导电垫H5和第六导电垫H6，其中，同一个导电垫组W中的每个导电垫在基底1上的正投影区域分别与同一个第一透光区T1存在交叠区。
示例性的，导电垫可以是焊盘。
在本申请的一些实施例中，交叠区的面积占导电垫在基底1上的正投影区域的面积的至少一半。
示例性的，各导电垫在基底1上的正投影的50％的区域与第一透光区T1交叠；各导电垫在基底1上的正投影的70％的区域与第一透光区T1交叠；各导电垫在基底1上的正投影的90％的区域与第一透光区T1交叠；各导电垫在基底1上的正投影的100％的区域与第一透光区T1交叠；此时，可以通过第一透光区T1漏出每个导电垫的背面，从而便于通过背面检测技术观测导电垫的背面，以确定导电垫是否存在不良问题；在后续工艺中将导电垫与元器件3连接时，还便于通过背面检测技术判断元器件3与导电垫之间是否存在连接不良。
连接不良的情况包括焊接不良，例如：虚焊、导电垫破损或导电垫腐蚀等不良问题。
示例性的，在本申请的实施例提供的阵列基板中，还可以是部分导电垫在基底1上的正投影的一半区域与第一透光区T1交叠，部分导电垫在基底1上的正投影的一半以上的区域与第一透光区T1交叠。具体可以根据实际情况确定。
在实际应用中，若第一透光区T1漏出的每一个导电垫的背面的区域较小，则无法准确的通过背面检测技术观测导电垫的背面，在后续工艺中将导电垫与元器件3连接时，也无法准确的通过背面检测技术判断元器件3与导电垫之间是否存在连接不良。本申请的实施例提供的阵列基板，通过设置交叠区的面积占导电垫(例如图5b中的H1、H2)在基底1上的正投影区域的面积的至少一半，从而通过第一透光区T1漏出各导电垫的背面的至少一半区域，进而提高在背面检测技术中确定元器件3与导电垫是否存在连接不良的准确性。
当然，在实际应用中，还可以存在个别情况，当各导电垫在基底1上的正投影的30％或40％的区域与第一透光区T1交叠时，也可以通过第一透光区T1漏出的导电垫的背面的部分判断出元器件3与导电垫是否存在连接不良。但这种情况属于少数情况，并不普遍存在。
导电垫组W包括至少一个导电垫，在图2a中，以导电垫组W包括两个导电垫(H1、H2)为例进行绘示。
在实际应用中，每一个导电垫组W对应于一个元器件3，可以根据与导电垫组W电连接的元器件3包括的焊脚数量确定每个导电垫组W 中包括的导电垫的数量。
示例性的，参考图14a所示，元器件3包括元器件本体31、第一焊脚32和第二焊脚33；与之对应的，导电垫组W包括第一导电垫H1和第二导电垫H2；第一焊脚32和第一导电垫H1电连接，第二焊脚33和第二导电垫H2电连接。
本申请的实施例对第一透光区T1在第一导电层1上的正投影的形状不做限定。示例的，第一透光区T1在第一导电层1上的正投影的形状大致可以为条形、长方形、正方形、菱形、圆形、半圆形或三角形中任意的一种，当然，还可以是其它的形状，具体可以根据实际需求设计。
“大致可以为条形、长方形、正方形、菱形、圆形、半圆形或三角形”是指第一透光区T1在第一导电层1上的正投影的整体形状为条形、长方形、正方形、菱形、圆形、半圆形或三角形，但并不局限为标准的条形、长方形、正方形、菱形、圆形、半圆形或三角形。
在示例性的实施例中，基底1可以包括如图14a所示的衬底100、缓冲层101、第二导电层102、第一绝缘层103、第一平坦层104和第二绝缘层105；或者，基底1可以包括如图16a所示的衬底100和缓冲层101；基底1的具体结构可以根据实际情况确定，这里不做限定。
在示例性的实施例中，第一导电层2用于形成导电图案。
在示例性的实施例中，导电垫可以是焊盘。
在一些实施例中，第一导电层2的材料可以包括铜、铝、镍、钼和钛中的任意一种或者层叠设置的几种金属的组合。
示例性的，第一导电层2可以包括依次层叠设置的钼镍钛合金(MoNiTi)层(或钼铌合金层(MoNb))、铜金属层和铜镍合金(CuNi)(或镍金层(NiAu))，钼镍钛或钼铌合金层可提高电镀工艺中铜金属晶粒的成核密度，铜镍合金或镍金层起到防止铜金属氧化的作用。其中，镍金层包括镍子层和金子层两个膜层，在实际应用中，可以设置镍子层与铜金属层直接接触，或者，也可以设置金子层与铜金属层直接接触，具体根据实际情况确定，这里不做限制。
第一导电层2中的钼镍钛合金层的厚度范围可为
Figure PCTCN2021118687-appb-000001
例如，厚度可为
Figure PCTCN2021118687-appb-000002
或
Figure PCTCN2021118687-appb-000003
在一些实施例中，第一导电层2的厚度范围可为0.3μm～10μm，例如，厚度可为0.3μm、0.5μm、0.6μm、0.9μm、2.7μm、3.6μm、4μm、 4.5μm、5μm、6.5μm、7μm、8μm、9μm或10μm。
示例性地，在基底1上有足够的空间排布所有导电图案的情况下，阵列基板可以只包括如图16a和图16b所示的一层导电层，此时，第一导电层2的厚度可以为2.7μm、3.6μm、4μm、4.5μm、5μm、6.5μm、7μm、8μm、9μm或10μm。
在本申请的实施例中，通过在基底1中设置多个第一透光区T1，基底1位于第一透光区T1的部分的透过率大于或者等于第一预设值，从而，从基底1位于第一透光区T1的部分可以看到第一导电层2中各导电垫的背面，进而可以通过背面检测技术检测导电垫可能存在的不良问题，拦截存在不良问题的阵列基板并进行修复，提高产品的可靠性。
在本申请的一些实施例中，导电垫(例如图2a中的H1、H2)在基底1上的正投影区域的边缘位于第一透光区T1以内。可以理解，导电垫在基底1上的正投影区域的面积小于第一透光区T1的面积。这样，通过第一透光区T1可以观测到完整的导电垫的背面，从而提高观测的准确性。
在本申请的一些实施例中，基底1位于第一透光区T1的部分的材料包括透光材料，和/或，基底1位于第一透光区T1的部分包括镂空结构。
上述方案包括三种情况：
第一种：参考图2b所示，基底1位于第一透光区T1的部分的材料包括透光材料，在本申请中，当基底1位于第一透光区T1的部分的材料包括透光材料时，第一透光区T1可以标记为L1。
第二种：参考图2a所示，基底1位于第一透光区T1的部分为镂空结构，在本申请中，当基底1位于第一透光区T1的部分为镂空结构时，第一透光区T1可以标记为K1。
第三种，参考图2c所示，基底1位于第一透光区T1的部分的材料包括透光材料，且基底1位于第一透光区T1的部分还包括镂空结构。具体的，如图2c所示的基底1包括透光层11和遮光层12，透光层11位于第一透光区T1的部分的材料为透光材料，遮光层12位于第一透光区T1的部分为镂空结构，这里将遮光层12位于第一透光区T1的部分的镂空结构标记为K2。在实际应用中，透光层11整层的材料可以均为透光材料。
示例性的，透光材料可以是硅胶、紫外光固化胶、氮化硅或氧化硅。
在本申请的实施例中，通过在基底1中设置多个第一透光区T1，基底1位于第一透光区T1的部分的透过率大于或者等于第一预设值，从而，从基底1位于第一透光区T1的部分可以看到第一导电层2中各导电垫的背面，进而可以通过背面检测技术检测导电垫可能存在的不良问题，拦截存在不良问题的阵列基板并进行修复，提高产品的可靠性。
在本申请的一些实施例中，参考图12所示，至少两个第一透光区T1连通设置并构成第二透光区T2。
示例性的，参考图12所示，第一导电层2包括第一导电垫组W1、第二导电垫组W2和第七走线27，第一导电垫组W1和第二导电垫组W2分别与第七走线27电连接；其中，第一导电垫组W1在基底1上的正投影落入一个第一透光区T1，第二导电垫组W2在基底1上的正投影落入另一个第一透光区T1，这两个第一透光区T1连通设置构成第二透光区T2，使得第一导电垫组W1、第二导电垫组W2和第七走线27在基底1上的正投影均落入同一个第二透光区T2。
在一些实施例中，通过多个第一透光区T1连通设置，使得多个导电垫组W和与导电垫组W连接的元器件3在基底1上的正投影均落入连通在一起的多个第一透光区T1构成的第二透光区T2中。
在本申请的一些实施例中，参考图12所示，部分导电垫组W在基底1上的正投影区域与第二透光区T2存在交叠。
在本申请的一些实施例中，参考图12所示，基底1还包括多个第三透光区T3；第一导电层2还包括多条走线，走线和导电垫电连接；
其中，至少部分走线在基底1上的正投影区域与第三透光区T3存在交叠。
需要说明的是，本申请的实施例中提到的“存在交叠”、“存在交叠区”的含义均为至少部分交叠。
在本申请的一些实施例中，参考图12所示，部分第三透光区T3和部分第一透光区T1连通设置，和/或，部分第三透光区T3和部分第二透光区T2连通设置。
该方案包括三种情况：
第一种情况，部分第三透光区T3和部分第一透光区T1连通设置。
下面将提供具体的实施例说明：
1、结合图3a和图3b所示，第一导电层2包括第一走线21、第二走线22和导电垫组W，导电垫组W包括第一导电垫H1和第二导电垫H2；在阵列基板的部分区域中，部分第三透光区T3和部分第一透光区T1连通设置，形成如图3a和图3b中标记为T1+T3的投影形状为矩形的透光区。
其中，第一导电垫H1和第二导电垫H2在基底1上的正投影均落入第一透光区T1内；第一走线21在基底1上的正投影与第三透光区T3至少部分交叠，第二走线22在基底1上的正投影与第三透光区T3至少部分交叠。另外，在阵列基板包括元器件3的情况下，元器件3在基底1上的正投影落入第一透光区T1内。
2、结合图4a和图4b所示，第一导电层2包括第一走线21、第二走线22和导电垫组W，导电垫组W包括第一导电垫H1和第二导电垫H2；在阵列基板的部分区域中，部分第三透光区T3和部分第一透光区T1连通设置，形成如图4a和图4b中标记为T1+T3的投影形状为矩形的透光区。
其中，第一导电垫H1和第二导电垫H2在基底1上的正投影均落入第一透光区T1内；第一走线21在基底1上的正投影与第三透光区T3部分交叠，第二走线22在基底1上的正投影与第三透光区T3部分交叠；元器件3在基底1上的正投影落入第一透光区T1内。
3、结合图5a和图5b所示，第一导电层2包括第一走线21、第二走线22和导电垫组W，导电垫组W包括第一导电垫H1和第二导电垫H2；在阵列基板的部分区域中，部分第三透光区T3和部分第一透光区T1连通设置，形成如图5a和图5b中标记为T1+T3的投影形状为矩形的透光区。
其中，第一导电垫H1在基底1上的正投影与第一透光区T1部分交叠，第二导电垫H2在基底1上的正投影与第一透光区T1部分交叠；第一走线21在基底1上的正投影与第三透光区T3部分交叠，第二走线22在基底1上的正投影与第三透光区T3部分交叠；元器件3在基底1上的正投影与第一透光区T1部分交叠。
4、结合图6a和图6b所示，第一导电层2包括第一走线21、第二走线22和导电垫组W，导电垫组W包括第一导电垫H1和第二导电垫H2；在阵列基板的部分区域中，部分第三透光区T3和部分第一透光区 T1连通设置，形成如图6a和图6b中标记为T1+T3的投影形状为多边形的透光区。
其中，第一导电垫H1和第二导电垫H2在基底1上的正投影均落入第一透光区T1内；第一走线21在基底1上的正投影与第三透光区T3至少部分交叠，第二走线22在基底1上的正投影与第三透光区T3至少部分交叠；元器件3在基底1上的正投影落入第一透光区T1内。
5、结合图7a和图7b所示，第一导电层2包括第三走线23、第四走线24、第五走线25、第六走线26和导电垫组W，导电垫组W包括第三导电垫H3、第四导电垫H4、第五导电垫H5和第六导电垫H6；在阵列基板的局部区域，部分第三透光区T3和部分第一透光区T1连通设置，形成如图7a和图7b中标记为T1+T3的投影形状为矩形的透光区。
其中，第三导电垫H3、第四导电垫H4、第五导电垫H5和第六导电垫H6在基底1上的正投影均落入第一透光区T1中，第三走线23和第五走线25在基底1上的正投影与分别第三透光区T3至少部分交叠，第四走线24和第六走线26在基底1上的正投影与第三透光区T3分别与第三透光区T3部分交叠。元器件3在基底1上的正投影落入第一透光区T1内。
6、结合图9a和图9b所示，第一导电层2包括第三走线23、第四走线24、第五走线25、第六走线26和导电垫组W，导电垫组W包括第三导电垫H3、第四导电垫H4、第五导电垫H5和第六导电垫H6；在阵列基板的局部区域，部分第三透光区T3和部分第一透光区T1连通设置，形成如图9a和图9b中标记为T1+T3的投影形状为矩形的透光区。
其中，第三导电垫H3、第四导电垫H4、第五导电垫H5和第六导电垫H6在基底1上的正投影均落入第一透光区T1中，第三走线23、第四走线24、第五走线25和第六走线26在基底1上的正投影分别与第三透光区T3部分交叠。元器件3在基底1上的正投影落入第一透光区T1内。
7、结合图10a和图10b所示，第一导电层2包括第三走线23、第四走线24、第五走线25、第六走线26和导电垫组W，导电垫组W包括第三导电垫H3、第四导电垫H4、第五导电垫H5和第六导电垫H6； 在阵列基板的局部区域，部分第三透光区T3和部分第一透光区T1连通设置，形成如图10a和图10b中标记为T1+T3的投影形状为矩形的透光区。
其中，第三导电垫H3、第四导电垫H4、第五导电垫H5和第六导电垫H6在基底1上的正投影均落入第一透光区T1中，第三走线23、第四走线24和第五走线25在基底1上的正投影与第三透光区T3至少部分交叠；第六走线26在基底1上的正投影与第三透光区T3部分交叠。元器件3在基底1上的正投影落入第一透光区T1内。
在本申请的一些实施例中，参考图3a-图5b所示，第一走线21和第二走线22在基底1上的投影形状均为条形；或者，参考图6a和图6b所示，第一走线21和第二走线22在基底1上的投影形状均为L形。
需要说明的是，第二走线22包括沿竖直方向延伸的部分线段222和沿水平方向延伸的线段221，第一走线21和第二走线22的结构类似，且两者的投影形状均为L形。在实际应用中，第一走线21和第二走线22可以均包括相交的两个线段，其相交的角度可以根据实际情况确定，这里不进行限定。
第二种情况，部分第三透光区T3和部分第二透光区T2连通设置。
下面将提供具体的实施例说明：
1、参考图12所示，第二导电层2包括第八走线28、第一导电垫组W1和第二导电垫组W2；在阵列基板的部分区域中，第一导电垫组W1在基底1上的正投影落入一个第一透光区T1，第二导电垫组W2在基底1上的正投影落入另一个第一透光区T1，这两个第一透光区T1连通设置构成第二透光区T2；第八走线28在基底1上的正投影落入第三透光区T3，第三透光区T3和第二透光区T2连通设置。
第三种情况，部分第三透光区T3和部分第一透光区T1连通设置，且部分第三透光区T3和部分第二透光区T2连通设置。
下面将提供具体的实施例说明：
1、参考图12所示，在阵列基板的部分区域中，第一导电垫组W1在基底1上的正投影落入一个第一透光区T1，第二导电垫组W2在基底1上的正投影落入另一个第一透光区T1，这两个第一透光区T1连通设置构成第二透光区T2；第八走线28在基底1上的正投影与第三透光区T3部分交叠，该第三透光区T3和该第二透光区T2连通设置；
在阵列基板的部分区域中，第三导电垫组W3在基底1上的正投影落入一个第一透光区T1，第九走线29在基底1上的正投影与第三透光区T3部分交叠；该第一透光区T1与该第三透光区T3连通设置。
在本申请的实施例中，通过将部分第三透光区T3和部分第一透光区T1连通设置，和/或，部分第三透光区T3和部分第二透光区T2连通设置，可以制作较大尺寸的透光区，避免了透光区的尺寸过小造成的制备工艺难度高的问题。
需要说明的是，在本申请的实施例中，图3a、图4a、图5a、图6a、图7a、图8a、图9a、和图10a分别是从阵列基板的八种正视图；图3b是与图3a对应的背视图，图4b是与图4a对应的背视图，图5b是与图5a对应的背视图，图6b是与图6a对应的背视图，图7b是与图7a对应的背视图，图8b是与图8a对应的背视图，图9b是与图9a对应的背视图，图10b是与图10a对应的背视图。
在一些实施例中，通过透光区，可以漏出导电垫背面的至少部分区域之外，还可以漏出导电垫周边的其它结构。示例性的，这里的其它结构可以包括与导电垫连接的走线、驱动线或者元器件3。
在一些实施例中，参考图2d所示，所有的小尺寸的透光区连接在一起构成一个整面性的透光区T，可以理解，该基底1中所有的膜层均采用透光材料制作。
在一些实施例中，在基底1上没有足够的空间排布所有导电图案的情况下，阵列基板可以包括如图14a、图14b、图15a和图15b所示的两层导电层，第一导电层2和第二导电层102(或1021)共同构成导电图案。其中，第一导电层2相对于第二导电层102(或1021)更接近元器件3设置，此时，第一导电层2的厚度可以为0.3μm、0.5μm、0.6μm或0.9μm、2.7μm、3.6μm、5μm。
在本申请的一些实施例中，参考图12所示，基底1包括衬底100和位于衬底100上的第二导电层102，第二导电层102和第一导电层2绝缘设置；
第一导电层2和第二导电层102(或1021)共同构成导电图案，其中，第一导电层2中包括多条走线，用于将接收到的电信号传输给各元器件3；
第二导电层102包括沿第一方向排布且沿第二方向延伸的多条驱 动线；第三透光区T3在衬底100上的正投影落入相邻的两个驱动线在衬底100上的正投影之间的区域。
示例性的，参考图12所示，驱动线可以分为第一驱动线(VLED)、第二驱动线(GND)和第三驱动线(PWR)。
在本申请的一些实施例中，参考图12所示，至少部分第三透光区T3沿第一方向排布，且沿第二方向延伸。
第一方向可以是竖直方向或者列方向，第二方向可以是水平方向或者行方向；当然，第一方向还可以是水平方向或者行方向，第二方向还可以是竖直方向或者列方向。
在一些实施例中，第二导电层102(或1021)的材料可以包括铜、铝、镍、钼和钛中的任意一种或者层叠设置的几种金属的组合。
在一些实施例中，第二导电层102(或1021)可包括依次层叠设置的钼铌合金层、铜金属层和保护层，保护层可包括铜镍合金(CuNi)、镍金层或氧化铟锡(Indium Tin Oxide，简称ITO)中的任一者。其中，钼铌合金层起到提高铜金属与靠近衬底一侧膜层的粘附力的作用，保护层起到防止铜金属氧化的作用。
示例性地，第二导电层102(或1021)的厚度范围可为0.5-10μm，例如，厚度可为0.5μm、1μm、1.8μm、2.7μm或10μm。
在一些实施例中，第二导电层102(或1021)的材料可以包括透光材料，例如：氧化铟锡(ITO)。
需要说明的是，在本申请的实施例中，当第二导电层的材料不透光时，第二导电层标记为102，例如图14a和图15a中的标记；当第二导电层的材料透光时，第二导电层标记为1021，例如图14b和图15b中的标记。
在本申请的一些实施例中，透光区T在第一导电层2上的正投影的轮廓到导电垫之间的距离范围为0-200μm。
示例性的，透光区T可以包括第一透光区T1、第二透光区T2和第三透光区T3中的任意一种或多种。基底1位于透光区T的部分的材料包括透光材料，和/或，基底位于透光区T的部分包括镂空结构。
本申请中提到的透光区T均指的是：第一透光区T1、第二透光区T2和第三透光区T3中的任意一种；或者，第一透光区T1、第二透光区T2和第三透光区T3中的多种连通设置后构成的区域。
其中，第一透光区T1与导电垫在基底1上的正投影区域存在交叠；至少两个第一透光区T1连通设置构成一个第二透光区T2；第三透光区T3与部分走线在基底1上的正投影区域存在交叠。
示例性的，在透光区T在第一导电层2上的投影轮廓与导电垫的外轮廓重合的情况下，透光区T在第一导电层2上的正投影的轮廓到导电垫之间的距离为0μm。
示例性的，在透光区T在第一导电层2上的投影轮廓包围导电垫的外轮廓的情况下，透光区T在第一导电层2上的正投影的轮廓到导电垫之间的距离大于0μm，且小于或等于200μm。
在一些实施例中，参考图7b所示，透光区(T1+T3)在第一导电层2上的正投影的轮廓包围第三导电垫H3的外轮廓，透光区在第一导电层2上的正投影的轮廓到第三导电垫H3直接的距离d1大于0μm，且小于或等于200μm；例如，d1可以为10μm、30μm、50μm、100μm、150μm或200μm。
在一些实施例中，参考图6b所示，透光区(T1+T3)在第一导电层2上的投影轮廓包围第一导电垫H1的外轮廓，透光区在第一导电层2上的正投影的轮廓沿水平方向到第一导电垫H1之间的距离d2大于0μm，且小于或等于200μm；透光区在第一导电层2上的正投影的轮廓沿竖直方向到第一导电垫H1之间的距离d2大于0μm，且小于或等于200μm。
在本申请的一些实施例中，阵列基板还包括多个元器件3，一个元器件3与同一组导电垫组W电连接。
在示例性的实施例中，元器件3可以包括发光器件、传感器件、微型驱动芯片或其它种类的器件中的任意一种或多种，可以理解是，不同类型的器件的数量不同，或者，不同类型的器件的阵列排布的密度不同。
其中，发光器件可以为次毫米发光二极管(Mini Light Emitting Diode，英文缩写为Mini LED)或微型发光二极管(Micro Light Emitting Diode，英文缩写为Micro LED)，在此不作限定。
示例性地，多个元器件3可以均为发蓝光的次毫米发光二极管或微型发光二极管，或者，多个元器件3以同时包括发红光、发绿光和发蓝光的三种发光二极管或微型发光二极管。
示例性的，一个元器件3可以包括至少一个焊脚，一组导电垫组W 可以包括至少一个导电垫，元器件3的焊脚和导电垫组W的导电垫电连接。在实际应用中，包括有3个焊脚的元器件3可以与包括2个导电垫的导电垫组W电连接；可以理解，一个元器件3对应一组导电垫组W，但是，元器件3中的焊脚数量可以和导电垫组W中的导电垫数量相同，或者，元器件3中的焊脚数量可以和导电垫组W中的导电垫数量不同，具体可以根据实际情况确定。
本申请的所有实施例以元器件3中的焊脚数量和导电垫组W中的导电垫数量相同为例进行说明。
在本申请的一些实施例中，多个导电垫组W阵列排布，参考图11c所示，导电垫包括金属层202和位于金属层202上的连接层203；
其中，连接层203位于金属层202和元器件3之间，且金属层202通过连接层203与元器件3连接；连接层203包括金属间化合物(IMC，Intermetallic Compound)，金属间化合物的形态呈如图11e中所示的块状结构M1、贝壳状结构、树枝形结构或如图11d中所示的米粒状结构M2中的至少一种。
在一些实施例中，通过在第一导电层2上印刷如图11a所示的焊接层201，参考图11b所示，通过加热使得焊接层201发生熔化和扩散，熔化的焊接层201润湿第一导电层2的部分区域，并与第一导电层2的材料发生扩散，在回流焊的过程中，焊接层201和第二导电层2的界面形成如图11c所示的连接层203。
在本申请的一些实施例中，金属间化合物包括Cu 6Sn 5、Cu 3Sn、Ni 3Sn 4、(Cu、Ni) 6Sn 5、(Ni、Cu) 3Sn 4或Ag 3Sn中的任意一种或多种。
(Cu，Ni) 6Sn 5是一种以Cu 6Sn 5为主要成分的材料，其中，部分Cu 6Sn 5中的铜(Cu)原子被镍(Ni)原子置换；(Ni、Cu) 3Sn 4是一种以Ni 3Sn 4为主要成分的材料，其中，部分Ni 3Sn 4中的镍(Ni)原子被铜(Cu)原子置换。示例性的，金属层202的材料包括铜(Cu)，焊接层201的材料包括SnAg或者SnAgCu。
在一些实施例中，焊接层201可以预制在元器件3的各焊脚上，或者，也可以印刷在各导电垫上。
在一些实施例中，为了在从背面检测时透过透光区观察到连接层203的金属间化合物的形态，以确定导电垫与元器件之间是否连接不良， 导电垫(或者第一导电层2)沿垂直于基底1方向的厚度范围可以为0.3μm-5μm，此时，金属层202的厚度较薄，不会遮挡住连接层203中金属间化合物的形态，以便于使用者通过背面检测技术准确的判断元器件3与各导电垫之间的连接状况。
示例性的，导电垫(或者第一导电层2)沿垂直于基底1方向的厚度可以为0.3μm、0.5μm、0.6μm、0.7μm、0.8μm、0.9μm、1.0μm、1.5μm、1.8μm、2.0μm、2.5μm、2.7μm、3.6μm、4.5μm或5μm。
在本申请的一些实施例中，阵列基板还包括焊接层，焊接层位于元器件的焊脚和导电垫之间，焊接层包括焊接材料；
在焊接层和导电垫直接接触的情况下，金属间化合物(IMC)的形态呈如图11d中所示的米粒状结构M2。
在本申请的一些实施例中，阵列基板还包括焊接层，焊接层位于元器件的焊脚和导电垫之间，焊接层包括焊接材料；
在焊接层和导电垫之间设置有抑制层的情况下，金属间化合物(IMC)的形态呈如图11e中所示的块状结构M1、贝壳状结构或树枝形结构中的一种或多种。
示例性的，焊接材料可以为焊锡。
示例性的，抑制层的材料包括镍(Ni)和/或金(Au)。
需要说明的是，金属间化合物(IMC)呈现的米粒状结构M2与焊接材料和第二导电层的材料的晶体生长过程相关，金属间化合物(IMC)呈现的块状结构M1与焊接材料、第二导电层的材料和抑制层的材料的晶体生长过程相关；由于在上述两种情况下，连接层203中生成的晶体的晶型不同，和/或晶体的尺寸不同，导致形成的连接层203中的金属间化合物(IMC)呈现出的形貌结构不同。
还需要在说明的是，在实际应用中，块状结构可以是连接层203的部分区域与金属层202的部分区域之间形成的空隙，从而在X-射线图像中呈现出块状空洞结构；或者，还可以是连接层203中的金属间化合物形成的晶簇聚集体，从而也可在显微镜下呈现出如图11e中所示的块状结构M1。
在本申请的一些实施例中，参考图14a所示，该阵列基板包括二层导电层(第一导电层2和第二导电层102)，第一导电层2和第二导电层102共同形成导电图案。
具体的，基底1包括衬底100、以及位于衬底100上依次层叠设置的缓冲层101、第二导电层102、第一绝缘层103、第一平坦层104和第二绝缘层105；其中，缓冲层101、第一绝缘层103、第一平坦层104和第二绝缘层105的材料均为透光材料；第二导电层102位于透光区T的部分的材料为透光材料，或，第二导电层102位于透光区T的部分为镂空结构。
示例性的，参考图14a和图15a所示的阵列基板，基底1中除第二导电层102之外的其它膜层的材料均为透光材料，第二导电层102位于透光区T的部分为镂空结构。需要说明的是，图14a所示的阵列基板为图6a沿A1A2方向的截面图。图15a所示的阵列基板为图4a沿B1B2方向的截面图。
示例性的，参考图14b和图15b所示，基底1中所有膜层的材料均为透光材料。
在本申请的一些实施例中，参考图16a和图16b所示，基底1包括衬底100和缓冲层101，且该阵列基板只包括一层导电层(第一导电层2)，第一导电层2用于形成导电图案。
示例性的，参考图16a和图16b所示，基底1中所有膜层的材料均为透光材料。
在一些实施例中，参考图14a-图16b所示，阵列基板还包括位于第一导电层2上的第三绝缘层106和第二平坦层107，其中，第三绝缘层106和第二平坦层107在基底1上在正投影分别与导电垫组W在基底1上的正投影互不交叠。第三绝缘层106和第二平坦层107中设置有开口区，开口区暴露出导电垫组W的区域，元器件3位于开口区中且与导电垫组W电连接。
在一些实施例中，参考图14a-图16b所示，阵列基板还包括反射层108，反射层108位于第二平坦层107上除开口区之外的区域，反射层108在基底1上的正投影与元器件3在基底1上的正投影互不交叠，且反射层108在基底1上的正投影位于第二平坦层107在基底1上的正投影以内。
通过设置反射层108，能够增加阵列基板沿垂直于基底1所在平面的方向上的出光量，从而提高阵列基板的出光效率。需要说明的是，此时，元器件3至少包括发光器件。
示例性的，反射层108的材料可以包括白色油墨、硅系白胶或者反射片中的任意一种或多种的组合。
在一些实施例中，阵列基板还包括辅助反射部109，辅助反射部109位于反射层108靠近元器件3的侧壁处，辅助反射部109在基底1上的正投影与反射层108在基底1上的正投影部分交叠。这样，通过反射层108和辅助反射部109的共同作用，能够进一步增加阵列基板沿垂直于基底1所在平面的方向上的出光量，从而提高阵列基板的出光效率。
辅助反射部109的材料包括硅系白胶，硅系白胶的颜色为白色，使辅助反射部109的颜色与反射层108的颜色大致相同，以保证辅助反射部109对光线的反射率接近于反射层108对光线的反射率。
在一些实施例中，阵列基板还包括多个与元器件3对应的封装单元4，封装单元4在基底1上的正投影覆盖元器件3在基底1上的正投影，且封装单元4在基底1上的正投影与反射层108在基底1上的正投影部分交叠。
示例性地，参考图16a和图16b所示，每个封装单元4包裹住一个元器件3。封装单元4在对元器件3起到封装保护作用的同时，还可通过设计其远离基底1的表面形状，例如使其具有类凸透镜的表面，从而可以进一步地调整元器件3包括的发光器件的出光角度。
另一方面，本申请的实施例提供了一种发光装置，参考图17所示，包括如上的阵列基板400。
该发光装置可以用作背光装置，或者，也可以用作显示装置。具体的，若发光装置中的多个元器件3包括发单一颜色光的发光器件，则上述发光装置可以用作背光装置；若发光装置中的多个元器件3包括分别发不同颜色光的发光器件，例如红光、发绿光和发蓝光的三种发光器件，则上述发光装置可以用作显示装置。
在一些实施例中，阵列基板还包括发光膜片406。
在一些实施例中，阵列基板还包括多个支撑柱401，多个支撑柱401用于支撑多个光学膜片406，光学膜片406包括沿远离阵列基板400依次设置的扩散板402、量子点膜403、扩散片404和复合膜405，其中，扩散板402和扩散片404可改善阵列基板所产生的灯影，提高发光装置的显示画质。量子点膜403在阵列基板中的发光器件发出的蓝光的激发下，将蓝光转换为白光，可以提高阵列基板400的光能的利用率。复合 膜405用于提高从扩散片404射出的光线的亮度。
本申请的实施例以发光装置中的多个元器件3包括发单一颜色光的发光器件，上述发光装置可以用作背光装置为例进行说明。此时，在该发光装置的出光侧设置一显示面板407，可以构成如图17所示的显示装置。
在本申请提供的发光装置中，通过在基底1中设置多个第一透光区T1，各第一透光区T1包括透光材料和/或镂空结构，由于基底1位于第一透光区T1的部分的透过率大于或者等于第一预设值，从而使得从基底1位于第一透光区T1的部分可以看到各导电垫的背面的部分区域，进而可以通过背面检测技术直接确定各导电垫的不良情况，在完成元器件3的制作后，还可以通过背面检测技术直接确定各导电垫与元器件3的连接不良情况，拦截连接不良的阵列基板并进行修复，提高产品的可靠性。
本申请的实施例提供了一种阵列基板的制备方法，应用于制备如上所述的阵列基板，参考图18所示，该方法包括：
S901、提供基底1；基底1包括多个第一透光区T1。
在本申请的一些实施例中，基底1位于第一透光区T1的部分的材料包括透光材料，和/或，基底1位于第一透光区T1的部分包括镂空结构。
示例性的，透光材料可以是硅胶、紫外光固化胶、氮化硅或氧化硅。
S902、在基底1上形成第一导电层2；其中，第一导电层2包括多个导电垫组W，导电垫组W包括至少一个导电垫，导电垫在基底1上的正投影区域与第一透光区T1存在交叠区；基底1位于第一透光区T1的部分的透过率大于或者等于第一预设值。
在本申请的一些实施例中，第一预设值大于或者等于50％。
实际应用中，第一预设值可以包括50％，55％，60％，70％，80％，85％，具体可以根据不同产品的设计和透过率需求确定，这里不做限制。
导电垫在基底1上的正投影区域与第一透光区T1存在交叠区的含义为：导电垫在基底1上的正投影区域与第一透光区T1至少部分交叠。可以理解，导电垫在基底1上的正投影区域与第一透光区T1存在交叠的情况下，这里对于交叠区的大小不做限定，具体可以根据不同产品的需求确定。
示例性的，导电垫可以是焊盘。
在本申请的一些实施例中，交叠区的面积占导电垫在基底1上的正投影区域的面积的至少一半。
在实际应用中，若第一透光区T1漏出的每一个导电垫的区域较小，则无法准确的通过背面检测技术观测导电垫的背面，在后续工艺中将导电垫与元器件3连接时，也无法准确的通过背面检测技术判断元器件3与导电垫之间是否存在连接不良。本申请的实施例提供的阵列基板，通过设置交叠区的面积占导电垫(例如图5b中的H1、H2)在基底1上的正投影区域的面积的至少一半，从而通过第一透光区T1漏出各导电垫的背面的至少一半区域，进而提高在背面检测技术中确定元器件3与导电垫是否存在连接不良的准确性。
在一些实施例中，在步骤S902、在基底1上形成第一导电层2之后，该方法还包括：
S903、将元器件3与导电垫组W连接在一起。
示例性的，参考图14a所示，元器件3包括元器件本体31、第一焊脚32和第二焊脚33；与之对应的，导电垫组W包括第一导电垫H1和第二导电垫H2；第一焊脚32和第一导电垫H1电连接，第二焊脚33和第二导电垫H2电连接。
示例性的，阵列基板还包括焊接层201，焊接层201位于元器件3和第一导电层2之间；
在一些实施例中，通过在导电垫上印刷如图11a所示的焊接层201，参考图11b所示，通过加热使得焊接层201发生熔化和扩散，熔化的焊接层201润湿第一导电层2，并与第一导电层2的材料发生扩散，在回流焊的过程中，焊接层201和第二导电层2的界面形成如图11c所示的连接层203，从而完成焊接。
本申请提供的制备方法制备的阵列基板，通过在基底1中设置多个第一透光区T1，各第一透光区T1包括透光材料和/或镂空结构，由于基底1位于第一透光区T1的部分的透过率大于或者等于第一预设值，从而使得从基底1位于第一透光区T1的部分可以看到各导电垫的背面的部分区域，进而可以通过背面检测技术直接确定各导电垫的不良情况，在完成元器件3的制作后，还可以通过背面检测技术直接确定各导电垫与元器件3的连接不良情况，拦截连接不良的阵列基板并进行修复，提 高产品的可靠性。
再一方面，本申请的实施例提供了一种检测方法，阵列基板包括多个元器件3，一个元器件3与同一组导电垫组W中的各导电垫电连接，参考图19所示，该方法包括：
S801、采集阵列基板的背面的目标图像；背面为基底1远离导电垫的表面；
其中，目标图像是指从阵列基板的背面，透过第一透光区T1采集到的，包括至少一个导电垫的图像；可以理解，目标图像是第一导电层2中包含有导电垫的部分的图像，且该图像中呈现出各导电垫远离元器件3的表面的形貌。
图13a和图13b示出了两种不同的目标图像。
目标图像是通过AOI(Automated Optical Inspection，自动光学检测)设备检测拍摄得到的，当然，还可以是其它设备，本申请的实施例以AOI设备为例进行说明。
S802、根据目标图像中各导电垫的参数信息，确定元器件3与导电垫之间是否连接不良。
连接不良可以包括焊接不良，焊接不良的情况包括导电垫虚焊、导电垫破损、导电垫腐蚀等问题。
在一些实施例中，参数信息包括导电垫的连接层203在基底1上的正投影的面积和元器件3的各焊脚在基底1上的正投影的面积。
在一些实施例中，参数信息包括元器件3与导电垫连接合格的模板图像。
在实际应用中，在完成固晶工艺后，会先对阵列基板的正面进行AOI检查，以确定各元器件3固定位置的准确性；再进行回流焊工艺，将元器件3和各导电垫焊接在一起，然后再进行上述的AOI背面检测的过程。
在本申请提供的阵列基板的检测方法，通过从阵列基板的背面，透光第一透光区T1采集到目标图像，根据目标图像中各导电垫的连接层203中金属间化合物呈现出的形貌特征和连接层203相对于各元器件3的焊脚的外扩面积来确定元器件3与导电垫是否连接不良，解决了相关技术中通过AOI正面检测无法准确拦截阵列基板的连接不良的问题。
在一些实施例中，在进行AOI背面检测之后，还会进行点灯测试， 根据点灯测试结构再进一步对部分连接不良的阵列基板进行修复。具体的点灯和修复工艺可以参考相关技术，这里不再赘述。
需要说明的是，本申请的检测方法针对的阵列基板中，一个元器件3对应连接一个导电垫组W，其中，元器件3包括的焊脚的数量和导电垫组W包括的导电垫的数量相同。
在本申请的一些实施例中，参数信息包括导电垫的连接层203在基底1上的正投影的面积和元器件3的各焊脚在基底1上的正投影的面积；
其中，S802、根据目标图像中各导电垫的参数信息，确定元器件与导电垫之间是否连接不良具体包括：
S8021、当导电垫组W中各导电垫的连接层203在基底1上的投影面积相较焊脚在基底1上的正投影的面积均大于或等于第二预设值时，确定元器件3与导电垫之间连接合格；
S8022、当导电垫组中有至少一个导电垫的连接层在基底上的投影面积相较焊脚在基底上的正投影的面积小于第二预设值时，确定元器件与导电垫之间连接不良。
需要说明的是，由于在焊接过程中，焊接层201的焊接材料与第一导电层2之间发生相互作用，使得焊接层201的焊接材料在第一导电层2位于各导电垫(焊盘)的部分发生熔解和扩散，并进一步形成如图11c所示的连接层203，由于焊接材料会发生扩散，实际形成的连接层203的区域大小与焊接过程中焊接材料的扩散区域的大小一致，在实际应用中，焊接材料会以焊脚所在的区域为中心向四周扩散，故而形成的连接层203的实际面积会大于各焊脚与焊接材料的接触面的面积。
图13a和图13b示出了两种不同的目标图像。其中，图13a为虚焊的目标图像，图13b为焊接合格的目标图像。可以看到，在图13a中，第一导电垫H1的焊接影响区M中形成的连接层203的层间化合物呈现的块状结构并不显著，且焊接影响区M中连接层203外扩的范围很小，说明焊接材料在加热时熔解和扩散效果不好，可以确定该第一导电垫H1对应的焊盘与元器件3之间存在焊接不良的问题。在图13b中，可以明显看到焊接影响区M中连接层203的金属间化合物呈现块状结构，且焊接影响区M区域较大，焊接影响区M中的连接层203的外扩痕迹明显，可以确定该第一导电垫H1对应的焊盘与元器件3之间焊接 合格。
需要说明的是，在图13a和图13b中，连接层203位于焊接影响区M中，连接层203为图13a和图13b中呈现块状结构的部分。
示例性的，上述第二预设值可以包括是30％、35％、40％、45％或50％。当然，第二预设值还可以包括其它数值，具体可以根据焊接材料的种类、焊接温度和焊接时间确定，这里不做限制。
示例性的，在元器件3的每个焊脚对应的连接层203的面积相较于该焊脚接的设计尺寸面积大30％的情况下，确认该元器件3焊接合格。
具体的，连接层203的尺寸较焊脚的尺寸向外围扩大20μm、30μm、40μm、50μm、80μm或100μm的情况下，确定元器件的其中一个焊脚焊接合格。
示例性的，当元器件3包括LED芯片的情况下，若LED芯片的焊脚的直径为90um，各连接层203相较于各焊脚均向外扩40um，连接层203的直径可以为130um，确认该LED芯片焊接合格。
一个元器件3的所有焊脚均合格，才能确认该元器件3焊接合格，一个元器件3中有至少一个焊脚焊接出现问题，确认该元器件3焊接不良。
本申请的检测方法针对于元器件3的焊脚数量和导电垫组W的导电垫数量相同、且各焊脚与各导电垫一一对应电连接的产品。
可以理解，在元器件3的焊脚数量和导电垫组W的导电垫数量不同时，可以根据实际情况，确定每一个导电垫组W中需要与元器件3的焊脚连接的导电垫的数量，再通过与本申请的检测方法类似的方法，判断与元器件3的焊脚连接的每一个导电垫的焊接情况，进而判断元器件3与各导电垫之间是否存在连接不良的问题。
在本申请的一些实施例中，参数信息包括元器件与导电垫连接合格的模板图像；
模板图像和目标图像在相同的拍摄倍率下拍摄。
其中，S802、根据目标图像中各导电垫的参数信息，确定元器件3与导电垫之间是否连接不良包括：
S8023、当目标图像中的导电垫与模板图像中的导电垫的相似度大于或等于第三预设值时，确定元器件3与导电垫之间连接合格；
S8024、当目标图像中存在至少一个导电垫与模板图像中的导电垫 的相似度小于第三预设值时，确定元器件与导电垫之间连接不良。
需要说明的是，由于在焊接过程中，焊接层201的焊接材料与第一导电层2之间发生相互作用，使得焊接层201的焊接材料在导电垫上发生熔解和扩散，并进一步形成如图11c所示的连接层203，在焊接合格的情况下，连接层203中形成金属间化合物，金属间化合物呈现出块状结构M1、米粒状结构M2、贝壳状结构或树枝形结构中的一种或多种。可以理解，根据目标图像中连接层203的形貌特征，可以确定出元器件3是否连接合格。
具体的，以模板图像中的特征形貌为块状结构M1为例进行说明，当目标图像中的各导电垫的连接层203形成具有块状结构M1的特征形貌，且连接层203外扩的面积符合要求时，此时，目标图像与模板图像的相似度大于或者等于第三预设值，说明对应的该元器件3与导电垫焊接合格。当目标图像中的各导电垫的连接层203未形成具有块状结构的特征形貌，或者形成的具有块状结构的特征形貌的区域较小时(如图13a所示)，此时，目标图像与模板图像的相似度小于第三预设值时，说明对应的该元器件3与导电垫焊接不良。
示例性的，第三预设值可以为40％、45％或50％。
在本申请提供的阵列基板的检测方法，通过从阵列基板的背面，透光第一透光区T1采集到目标图像，根据目标图像中各导电垫的连接层203中金属间化合物呈现出的形貌特征和连接层203相对于各元器件3的焊脚的外扩面积来确定元器件3与导电垫是否连接不良，解决了相关技术中通过AOI正面检测无法准确拦截阵列基板的连接不良的问题。
在实际应用中，当AOI检测设备通过上述方法检测到连接不良的基板时，根据具体不良的类型，再进一步进行人工检测或者修复。
示例性的，当检测到发生虚焊问题时，直接通过修复设备对导电垫位置进行修复；当检测到导电垫发生破损时，需要再次进行人工检测，确定破损面积，在破损面积小于或者等于第四预设值时，可以认为该破损不影响阵列基板的正常使用，在破损面积大于第四预设值时，该阵列基板报废。
示例性的，第四预设值可以包括5％、10％、15％或20％。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内， 可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种阵列基板，其中，包括：
    基底，所述基底包括多个第一透光区；
    位于所述基底上的第一导电层；
    所述第一导电层包括多个导电垫组，所述导电垫组包括至少一个导电垫；
    其中，所述导电垫在所述基底上的正投影区域与所述第一透光区存在交叠区；所述基底位于所述第一透光区的部分的透过率大于或者等于第一预设值。
  2. 根据权利要求1所述的阵列基板，其中，所述第一预设值大于或者等于50％。
  3. 根据权利要求1所述的阵列基板，其中，所述交叠区的面积占所述导电垫在所述基底上的正投影区域的面积的至少一半。
  4. 根据权利要求3所述的阵列基板，其中，所述导电垫在所述基底上的正投影区域的边缘位于所述第一透光区以内。
  5. 根据权利要求2所述的阵列基板，其中，所述基底位于所述第一透光区的部分的材料包括透光材料，和/或，所述基底位于所述第一透光区的部分包括镂空结构。
  6. 根据权利要求1所述的阵列基板，其中，至少两个所述第一透光区连通设置并构成第二透光区。
  7. 根据权利要求6所述的阵列基板，其中，部分所述导电垫组在所述基底上的正投影区域与所述第二透光区存在交叠。
  8. 根据权利要求6所述的阵列基板，其中，所述基底还包括多个第三透光区；所述第一导电层还包括多条走线，所述走线和所述导电垫电连接；
    其中，至少部分所述走线在所述基底上的正投影区域与所述第三透光区存在交叠。
  9. 根据权利要求8所述的阵列基板，其中，部分所述第三透光区和部分所述第一透光区连通设置，和/或，部分所述第三透光区和部分所述第二透光区连通设置。
  10. 根据权利要求8所述的阵列基板，其中，所述基底包括衬底和 位于所述衬底上的第二导电层，所述第二导电层和所述第一导电层绝缘设置；
    其中，所述第二导电层包括沿第一方向排布且沿第二方向延伸的多条驱动线；所述第三透光区在所述衬底上的正投影落入相邻的两个所述驱动线在所述衬底上的正投影之间的区域。
  11. 根据权利要求10所述的阵列基板，其中，至少部分所述第三透光区沿所述第一方向排布，且沿所述第二方向延伸。
  12. 根据权利要求1-11任一项所述的阵列基板，其中，透光区在所述第一导电层上的正投影的轮廓到所述导电垫之间的距离范围为0-200μm。
  13. 根据权利要求12所述的阵列基板，其中，所述阵列基板还包括多个元器件，一个所述元器件与同一组所述导电垫组电连接；
    多个所述导电垫组阵列排布，所述导电垫包括金属层和位于所述金属层上的连接层；
    其中，所述连接层位于所述金属层和所述元器件之间，且所述金属层通过所述连接层与所述元器件连接；所述连接层包括金属间化合物，所述金属间化合物的形态呈块状结构、贝壳状结构、树枝形结构或米粒状结构中的至少一种。
  14. 根据权利要求13所述的阵列基板，其中，所述金属间化合物包括Cu 6Sn 5、Cu 3Sn、Ni 3Sn 4、(Cu、Ni) 6Sn 5、(Ni、Cu) 3Sn 4或Ag 3Sn中的任意一种或多种。
  15. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括焊接层，所述焊接层位于所述元器件的焊脚和所述导电垫之间，所述焊接层包括焊接材料；
    在所述焊接层和所述导电垫直接接触的情况下，所述金属间化合物的形态呈米粒状结构。
  16. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括焊接层，所述焊接层位于所述元器件的焊脚和所述导电垫之间，所述焊接层包括焊接材料；
    在所述焊接层和所述导电垫之间设置有抑制层的情况下，所述金属间化合物的形态呈块状结构、贝壳状结构或树枝形结构中的一种或多种。
  17. 根据权利要求1-8、11-12、14-16任一项所述的阵列基板，其 中，所述基底包括衬底、以及位于所述衬底上依次层叠设置的缓冲层、第二导电层、第一绝缘层、第一平坦层和第二绝缘层；
    其中，所述缓冲层、第一绝缘层、第一平坦层和第二绝缘层的材料均为透光材料；
    所述第二导电层位于所述透光区的部分的材料为透光材料，或，所述第二导电层位于所述透光区的部分为镂空结构。
  18. 一种发光装置，其中，包括如权利要求1-17中任一项所述的阵列基板。
  19. 一种检测方法，其中，应用于检测如权利要求1-17中任一项所述的阵列基板，所述阵列基板包括多个元器件，一个所述元器件与同一组所述导电垫组中的各所述导电垫电连接，所述方法包括：
    采集所述阵列基板的背面的目标图像；所述背面为所述基底远离所述导电垫的表面；
    根据所述目标图像中各所述导电垫的参数信息，确定所述元器件与所述导电垫之间是否连接不良。
  20. 根据权利要求19所述的检测方法，其中，所述参数信息包括所述导电垫的连接层在所述基底上的正投影的面积和所述元器件的各焊脚在所述基底上的正投影的面积；
    所述根据所述目标图像中各所述导电垫的参数信息，确定所述元器件与所述导电垫之间是否连接不良包括：
    当所述导电垫组中各所述导电垫的所述连接层在所述基底上的投影面积相较所述焊脚在所述基底上的正投影的面积均大于或等于第二预设值时，确定所述元器件与所述导电垫之间连接合格；
    当所述导电垫组中有至少一个所述导电垫的所述连接层在所述基底上的投影面积相较所述焊脚在所述基底上的正投影的面积小于所述第二预设值时，确定所述元器件与所述导电垫之间连接不良。
  21. 根据权利要求19所述的检测方法，其中，所述参数信息包括所述元器件与所述导电垫连接合格的模板图像；
    所述根据所述目标图像中各所述导电垫的参数信息，确定所述元器件与所述导电垫之间是否连接不良包括：
    当所述目标图像中的所述导电垫与所述模板图像中的所述导电垫的相似度大于或等于第三预设值时，确定所述元器件与所述导电垫之间 连接合格；
    当所述目标图像中存在至少一个所述导电垫与所述模板图像中的所述导电垫的相似度小于所述第三预设值时，确定所述元器件与所述导电垫之间连接不良。
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CN102931107A (zh) * 2011-08-09 2013-02-13 财团法人交大思源基金会 用于减缓金属间化合物成长的方法
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CN105979719A (zh) * 2016-06-20 2016-09-28 努比亚技术有限公司 印刷电路板的焊接方法

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CN101272679A (zh) * 2007-03-19 2008-09-24 株式会社东芝 电子设备的制造方法
US20090091024A1 (en) * 2007-06-11 2009-04-09 Texas Instruments Incorporated Stable Gold Bump Solder Connections
CN102931107A (zh) * 2011-08-09 2013-02-13 财团法人交大思源基金会 用于减缓金属间化合物成长的方法
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