TW201301466A - 無凸塊增層式封裝體翹曲降低技術 - Google Patents

無凸塊增層式封裝體翹曲降低技術 Download PDF

Info

Publication number
TW201301466A
TW201301466A TW101120105A TW101120105A TW201301466A TW 201301466 A TW201301466 A TW 201301466A TW 101120105 A TW101120105 A TW 101120105A TW 101120105 A TW101120105 A TW 101120105A TW 201301466 A TW201301466 A TW 201301466A
Authority
TW
Taiwan
Prior art keywords
layer
microelectronic device
microelectronic
package
thermal expansion
Prior art date
Application number
TW101120105A
Other languages
English (en)
Other versions
TWI578469B (zh
Inventor
Pramod Malatkar
Drew W Delaney
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW201301466A publication Critical patent/TW201301466A/zh
Application granted granted Critical
Publication of TWI578469B publication Critical patent/TWI578469B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

本發明係有關於製造微電子封裝體及其製造之領域，其中一微電子裝置可形成在一無凸塊增層式無核心(BBUL-C)微電子封裝體內且其中一翹曲控制結構可設置在該微電子裝置之一背面上。該翹曲控制結構可以是一層結構，且該層結構包含包括但不限於一填充環氧樹脂材料之至少一高熱膨脹係數材料層，及例如一金屬層之高彈性模數材料層。

Description

無凸塊增層式封裝體翹曲降低技術
本發明係有關於一種無凸塊增層式封裝體翹曲降低技術。
本發明之實施例係大致有關於微電子裝置封裝體設計且，更特別地，係有關於具有一無凸塊增層式(BBUL)設計之一微電子裝置封裝體。
依據本發明之一實施例，係特地提出一種微電子封裝體，包含：一微電子裝置，其具有一主動表面，一相對背面，及至少一側；及一翹曲控制結構，其與該微電子裝置背面相鄰，其中該翹曲控制結構包括一高熱膨脹係數材料層及一高彈性模數材料層。
依據本發明之一實施例，係特地提出一種製造一微電子封裝體之方法，包含：形成一微電子裝置，且該微電子裝置具有一主動表面，一相對背面，及至少一側；及形成一與該微電子裝置背面相鄰之翹曲控制結構，其包含形成與一高彈性模數材料層相鄰之一高熱膨脹係數材料層。
依據本發明之一實施例，係特地提出一種製造一微電子封裝體之方法，包含：提供一載體；在該載體上形成一微電子裝置附接墊，其中該微電子裝置附接墊包括一高彈性模數材料層；附接具有一主動表面，一相對背面，及至少一側之一微電子裝置在該微電子裝置附接墊上，其中附 接該微電子裝置之步驟包括將一高熱膨脹係數材料層設置在該微電子裝置背面與該微電子裝置附接墊之間；將一封裝材料設置成與該微電子裝置主動表面之至少一部份及至少一微電子裝置側之至少一部份相鄰；及移除該載體。
圖式簡單說明
本發明之標的物係在說明書之結論部份中特別指出且清楚地請求。本發明之前述及其他將可配合附圖，由以下說明及附加申請專利範圍更完整地了解。應了解的是該等附圖只顯示依據本發明之數個實施例且因此不應被視為限制其範圍。本揭露將透過利用附圖以另外之特性及細節說明，使得本發明之優點可以更輕易地確定，其中：第1圖顯示依據本發明一實施例之一無凸塊增層式無核心微電子封裝體的側橫截面圖。
第2圖顯示依據本發明另一實施例之一無凸塊增層式無核心微電子封裝體的側橫截面圖。
第3-13圖顯示依據本發明一實施例之形成一凹孔型無凸塊增層式無核心微電子封裝體之一製程的橫截面圖。
第14-20圖顯示依據本發明一實施例之形成一埋入型無凸塊增層式無核心微電子封裝體之一製程的橫截面圖。
詳細說明
在以下詳細說明中，參照藉由舉例說明顯示可實施之請求標的物的特定實施例。這些實施例係充分詳細地說明以使所屬技術領域中具有通常知識者可實施該標的物。應 了解的是各種實施例雖然不同，但不一定是互相排他的。例如，在此關於一實施例所述之特定特徵、結構或特性可在不偏離所請求之標的物之精神及範疇之情形下，在其他實施例內實施。在這說明書內提及之“一個實施例”或“一實施例”表示關於該實施例所述之一特定特徵、結構或特性包含在本發明之至少一個實施例中。因此，使用該片語“在一個實施例中”或“在一實施例中”的出現不一定指的是相同實施例。此外，應了解的是在各揭露實施例內之個別元件之位置及配置可在不偏離該請求之標的物之情形下修改。因此，以下詳細說明不應一限制方式解釋，且該標的物之範疇係只由附加之申請專利範圍以及附加之申請專利範圍所賦予之等效物之全部範圍界定，及適當地判讀。在圖式中，類似符號表示在全部數個圖中相同或類似元件或功能性，且其中所示之元件不一定互相成比例，而是個別元件可放大或縮小以便更容易地了解在此說明之上下文中的元件。
本發明之實施例係有關於製造微電子封裝體及其製造之領域，其中一微電子裝置可在一無凸塊增層式無核心(BBUL-C)微電子封裝體內形成且其中一翹曲控制結構可設置在該微電子裝置之一背面上。該翹曲控制結構可以是一層結構，且該層結構包含包括但不限於一填二氧化矽環氧樹脂材料之至少一高熱膨脹係數材料層，及例如一金屬層之至少一高彈性模數材料層。這翹曲控制結構可以在室溫(大約攝氏25度)及在迴焊溫度(例如，大約攝氏260度)均 有效地減少該無凸塊增層式無核心微電子封裝體之翹曲。迴焊溫度係互連焊料結構被加熱到將該微電子封裝體附接在例如一母板之外部裝置上的溫度。
如所屬技術領域中具有通常知識者可了解地，減少翹曲可減少微電子裝置損壞之可能性及在將該微電子封裝體附接在外部裝置上時之連接問題。此外，由於因翹曲減少而減少在該等微電子裝置內之電晶體上的平面內壓力，因此可改善在該等微電子封裝體內之微電子裝置的效能。
第1圖顯示一凹孔型無凸塊增層式無核心(BBUL-C)微電子封裝體之一實施例的橫截面圖。如第1圖所示，一微電子封裝體100可包括實質被包封在一封裝材料112中之一微電子裝置102，其中該封裝材料112可抵靠該微電子裝置102之一主動表面104之至少一部份及該微電子裝置102之至少一側110。該微電子主動表面104可具有形成於其中及/或其上之至少一接觸焊墊106。該微電子裝置102可以是任何所需裝置，包括但不限於一微處理器(單核心或多核心)，一記憶體裝置，一晶片組，一繪圖裝置，一特殊應用積體電路等。該封裝材料112可以是一填二氧化矽環氧樹脂，例如由日本210-0801川崎市川崎區鈴木鎮1-2之Ajinomoto Fine-Techno公司(Ajinomoto ABF-GX13，Ajinomoto GX92等)取得之增層薄膜。
一增層122可形成在靠近該微電子裝置主動表面104之該封裝材料112之一第一表面114上。該增層122可包含多數介電層，且多數導電線路與各介電層相鄰地形成，並且多 數導電通孔延伸穿過各介電層以連接在不同層上之導電線路。請參閱第1圖，該增層122可包含至少一第一層導電線路132，且一第一增建介電層134與該第一層導電線路132及該封裝材料112相鄰地形成。至少一線路至裝置導電通孔136可延伸穿過該第一增建介電層134以連接至少一第一層導電線路132與至少一微電子裝置接觸焊墊106。至少一第二層導電線路142可與該第一增建介電層134相鄰地形成且一第二增建介電層144可與該第二層導電線路142及該第一增建介電層134相鄰地形成。至少一線路至線路導電通孔146可延伸穿過該第一增建介電層134以連接至少一第一層導電線路132與至少一第二層導電線路142。至少一第三層導電線路152可形成在該第二增建介電層144上且至少一線路至線路導電通孔146可延伸穿過該第二增建介電層144以連接至少一第二層導電線路142與第三層導電線路152。一阻焊材料154可在該第二增建介電層144及第三層導電線路152上圖案化，且具有至少一暴露該第三層導電線路152之一部份之開口156。應了解的是例如焊料球之多數互連結構(未顯示)可形成在該(等)第三層導電線路152穿過該(等)阻焊材料開口156。
至少一疊合式封裝(PoP)墊162可形成在該封裝材料112之一第二表面116(實質相對該封裝材料第一表面114)上及/或中。該疊合式封裝墊162可與至少一第一層導電線路132電連接。如所屬技術領域中具有通常知識者可了解地，該等疊合式封裝墊可用來在不需要貫穿矽通孔之情形下， 以一z方向在微電子裝置封裝體之間形成多數連接部以便堆疊(例如，所謂3D堆疊)。
如第1圖所示，例如由日本910-0381 Fukui Sakai Maruoka Funayose 110-1-1之Nitto Denko取得之Nitto NX2 DBF材料，可設置在該微電子裝置102之背面108上。一翹曲控制結構180可包含一設置在該晶粒背側薄膜172上之高熱膨脹係數(CTE)材料層182及一設置在該高CTE材料層182上之高彈性模數材料層184。該高CTE材料層182可包括，但不限於填充環氧樹脂，例如一填二氧化矽環氧樹脂，包括但不限於由日本210-0801川崎市川崎區鈴木鎮1-2之Ajinomoto Fine-Techno公司的Ajinomoto ABF-GX13，Ajinomoto GX92等。該高彈性模數材料層184可包括，但不限於一金屬層，例如銅、鎳、鋁及其合金等。在一實施例中，該高CTE材料層182及該高彈性模數材料層184可以與供該微電子封裝體100之其他區域使用之材料相同或類似，且實質上使該微電子封裝體100更對稱(例如，比較不會翹曲)。在一實施例中，該翹曲控制結構180包含一含有厚度在大約5μm與50μm之間，且厚度特別為30μm之填二氧化矽環氧樹脂的該高CTE材料層182及含有厚度大約在大約5μm與50μm之間的該高彈性模數材料層184。
設置在一微電子裝置上之具有一高CTE材料層及一高彈性模數材料層兩者的一層結構應產生一較低封裝體翹曲。在一實施例中，該高CTE材料層182可大於大約25微米每米每攝氏度(“ppm/℃”)且該高彈性模數材料層184可大於 大約5京帕斯卡(GPa”)。在此應了解的是該必要之最小CTE及彈性模數值可隨著該微電子裝置之厚度、得到之微電子封裝體之厚度及/或該等材料層之厚度改變。該等最小CTE值係與所考慮之溫度有關，因為大部份環氧樹脂材料在它們的玻璃轉移溫度之前之CTE值(以CTE1表示)及在它們的玻璃轉移溫度之後之CTE值(以CTE2表示)會非常不同。如果必須控制之封裝體翹曲之溫度(例如，室溫或迴焊溫度)低於欲設置之材料之玻璃轉移溫度，則該最小CTE值將稱為CTE1之值，且如果高於該玻璃轉移溫度將稱為之CTE2之值。該最小彈性模數一直稱為在所考慮之溫度下之模數。
在本發明之一實施例中，該翹曲控制結構180可薄到足以嵌入在一堆疊封裝體構形(未顯示)中之一頂封裝體(未顯示)與一底封裝體(例如微電子封裝體100)之間的間隙內且因此，如所屬技術領域中具有通常知識者可了解地，不會增加該堆疊封裝體構形(未顯示)之整體z-高度。在另一實施例中，該高CTE材料層182及該高彈性模數材料層184可選擇成使得翹曲可在室溫(大約攝氏25度)及在迴焊溫度(例如，大約攝氏260度)都減少。
如第2圖所示，該晶粒背側薄膜(在第1圖中所示之元件172)可本身作為該高CTE材料層。在一實施例中，一翹曲控制結構190可直接設置在該微電子裝置背面108上，其中該翹曲控制結構180可包含設置在該微電子裝置背面108上之高CTE材料層182及一設置在該高CTE材料層182上之高彈性模數材料層184。該高CTE材料層182可包括，但不限於 晶粒背側薄膜或黏著材料，例如由日本910-0381 Fukui Sakai Maruoka Funayose 110-1-1之Nitto Denko取得之Nitto NX2 DBF材料，或由日本東京101-0021 Chiyoda區Sotokanda 4街14-1之日本鋼鐵化學公司取得之NEX系列材料(例如NEX-130CTX，NEX140DBF)。該高彈性模數材料層184可包括，但不限於一金屬層，例如銅、鎳、鋁及其合金。
第3-13圖顯示形成一凹孔型無凸塊增層式無核心(BBUL-C)微電子封裝體之一製程之一實施例的橫截面圖。如第3圖所示，可提供一載體200。所示之載體200可以是一銅積層基體，且該銅積層基體包含在兩相對銅釋放層(即一第一銅釋放層204與一第二銅釋放層204')之間的一心材206，並且兩相對銅層(即一第一銅層202及一第二銅層202')抵靠它們的各個銅釋放層(即一第一銅釋放層204與一第二銅釋放層204')且抵靠該心材206之一部份，其中該第一銅層202之外表面界定該載體200之一第一表面208且該第二銅層202'之外表面界定該載體200之一第二表面208'。該心材206可以是任何適當材料，包括但不限於一預浸滲複合纖維材料。應了解的是雖然與該心材206積層之該等層係特別指明為銅層(即該等銅層及該等銅釋放層)，本發明不限於此，因為該等層可以由任何適當材料構成。
如第4圖所示，一第一微電子裝置附接墊212可形成在該載體第一表面208上且一第二微電子裝置附接墊212'可形成該載體第二表面208'上。如第4圖進一步所示，該第一微 電子裝置附接墊212可以是例如一第一鎳層之一第一保護層214，及例如一第一銅層之一第一高彈性模數材料層216之層結構，且該第一保護層214抵靠該載體第一表面208並且該第一高彈性模數材料層216抵靠該第一保護層214。又，該第二微電子裝置附接墊212'亦可是例如一第二鎳層之一第二保護層214'，及例如一第二銅層之一第二高彈性模數材料層216'之層結構，且該第二保護層214'抵靠該載體第二表面208'並且該第二高彈性模數材料層216'抵靠該第二保護層214'。該第一保護層214及該第二保護層214'可被用來防止氧化物分別形成在該第一高彈性模數材料層216及該第二高彈性模數材料層216'上，且防止在將說明之後續製造程序時蝕刻該第一高彈性模數材料層216及該第二高彈性模數材料層216'。
如第5圖所示，例如一光阻材料之一第一犧牲材料層222可形成在該載體第一表面208上且在該第一微電子裝置附接墊212上；且例如例如一光阻材料之一第二犧牲材料層222'可形成在該載體第二表面208'上且在該第二微電子裝置附接墊212'上。該第一犧牲材料層222及該第二犧牲材料層222'可藉由在所屬技術領域中習知之任何技術形成，包括但不限於旋塗法、乾光膜積層法、及化學蒸氣沈積法。
如第6圖所示，一開口224可穿過該第一犧牲材料層222而形成以暴露該第一微電子裝置附接墊212及該載體第一表面208之一部份。一開口224'可同時穿過該第二犧牲材料層222'而形成以暴露該第二微電子裝置附接墊212'及該載 體第二表面208'之一部份。該第一犧牲材料層開口224及該第二犧牲材料層開口224'可藉由在所屬技術領域中習知之任何技術形成，包括但不限於光刻法及濕式或乾式蝕刻法。
如第7圖所示，多數疊合式封裝(PoP)墊可形成在第一犧牲材料層222及該第二犧牲材料層222'上。第7圖顯示一第一疊合式封裝墊228a及一形成在該第一犧牲材料層222上之第二疊合式封裝墊228b，以及一第三疊合式封裝墊228a'及一形成在該第二犧牲材料層222'上之第四疊合式封裝墊228b'。該等疊合式封裝墊(例如，元件228a、228b、228a'、228b')可以是層狀金屬結構，例如一金、鎳及銅層，且該層狀金屬結構可藉由包括但不限於鍍敷之在所屬技術領域中習知之任何技術圖案化。如所屬技術領域中具有通常知識者可了解地，該等疊合式封裝墊可用來在不需要貫穿矽通孔之情形下，以一z方向(請參見第1圖)在微電子裝置封裝體之間形成多數連接部以便堆疊(例如，所謂3D堆疊)。
如第8圖所示，一第一微電子裝置242可藉由其一背面250與一高CTE材料層244一起附接在該第一犧牲材料層開口224內之載體第一表面208上。該第一微電子裝置242可在其一主動表面248上具有至少一接觸焊墊(顯示為元件246a與246b)。一第二微電子裝置242'可藉由其一背面250'與一高CTE材料層244'一起附接在該第二犧牲材料層開口224'內之載體第二表面208'上。該第二微電子裝置242'可可在其一主動表面248'上具有至少一接觸焊墊(顯示為元件246a'與246b')。該第一微電子裝置242及該第二微電子裝置242'可 以是任何所需裝置，包括但不限於一微處理器(單核心或多核心)，一記憶體裝置，一晶片組，一繪圖裝置，一特殊應用積體電路等。該等高CTE材料層244與244'可為任何適當材料，包括但不限於晶粒背側薄膜材料。
如第9圖所示，一第一封裝層252可形成在該第一微電子裝置242，該第一犧牲材料層開口224，該第一疊合式封裝墊228a，及該第二疊合式封裝墊228b上。一第二封裝層252'可同時形成在該第二微電子裝置242'，該第二犧牲材料層開口224'，該第三疊合式封裝墊228a'，及該第四疊合式封裝墊228b'上。在一實施例中，該第一封裝層252及該第二封裝層252'可包含填二氧化矽環氧樹脂。
如第10圖所示，一第一增層262可形成在該第一封裝層252上。該第一增層262可包含多數介電層，且多數導電線路與各介電層相鄰地形成並且多數導電通孔延伸穿過各介電層以連接在不同層上之導電線路。請參閱第10圖，該第一增層262可包含至少一第一層導電線路272，且一第一增建介電層274與該第一層導電線路272及該第一封裝層252相鄰地形成。至少一線路至裝置導電通孔276可延伸穿過該第一增建介電層274以連接至少一第一層導電線路272與至少一微電子裝置接觸焊墊(例如元件246a與246b)。至少一線路至墊導電通孔278可延伸穿過該第一增建介電層274以連接至少一第一層導電線路272與至少一疊合式封裝墊(例如，元件228a與228b)。至少一第二層導電線路282可與該第一增建介電層274相鄰地形成且一第二增建介電層284可 與該第二層導電線路282及該第一增建介電層274相鄰地形成。至少一線路至線路導電通孔286可延伸穿過該第一增建介電層274以連接至少一第一層導電線路272與至少一第二層導電線路282。至少一第三層導電線路292可形成在該第二增建介電層284上且至少一線路至線路導電通孔286可延伸穿過該第二增建介電層284以連接至少一第二層導電線路282與至少一第三層導電線路292。一阻焊材料294可在該第二增建介電層284及該第三層導電線路292上圖案化且具有至少一暴露該第三層導電線路292之至少一部份的開口296。應了解的是例如焊料球之多數互連結構(未顯示)可形成在該(等)第三層導電線路292上穿過該(等)阻焊材料開口296。
如第10圖進一步所示，一第二增層262'可形成在該第二封裝層252'上。該第二增層262'可包含多數介電層，且多數導電線路與各介電層相鄰地形成並且多數導電通孔延伸穿過各介電層以連接在不同層上之導電線路。請參閱第10圖，該第二增層262'可包含至少一第一層導電線路272'，且一第一增建介電層274'與該第一層導電線路272'及該第二封裝層252'相鄰地形成。至少一線路至裝置導電通孔276'可延伸穿過該第一增建介電層274'以連接至少一第一層導電線路272'與至少一微電子裝置接觸焊墊(例如元件246a'與246b')。至少一線路至墊導電通孔278'可延伸穿過該第一增建介電層274'以連接至少一第一層導電線路272'與至少一疊合式封裝墊(例如，元件228a'與228b')。至少一第二層導 電線路282'可與該第一增建介電層274'相鄰地形成且一第二增建介電層284'可與該第二層導電線路282'及該第一增建介電層274'相鄰地形成。至少一線路至線路導電通孔286'可延伸穿過該第一增建介電層274'以連接至少一第一層導電線路272'與至少一第二層導電線路282'。至少一第三層導電線路292'可形成在該第二增建介電層284'上且至少一線路至線路導電通孔286'可延伸穿過該第二增建介電層284'以連接至少一第二層導電線路282'與至少一第三層導電線路292'。一阻焊材料294'可在該第二增建介電層284'及該第三層導電線路292'上圖案化且具有至少一暴露該第三層導電線路292'之至少一部份的開口296'。應了解的是例如焊料球之多數互連結構(未顯示)可形成在該(等)第三層導電線路292'上穿過該(等)阻焊材料開口296'。
該等線路(例如元件272、272'、282、282'、292及292')可以是包括但不限於銅、鋁、銀、金及其合金之任何適當導電材料，且可由包括但不限於光刻法及鍍敷法之在所屬技術領域中習知之任何技術製成。該等導電通孔(例如元件276、276'、278、278'、286及286')可以是包括但不限於銅、鋁、銀、金及其合金之任何適當導電材料，且可由包括但不限於雷射鑽孔法、離子鑽孔、光刻法、鍍敷法及沈積法之在所屬技術領域中習知之任何技術製成。
應了解的是可增建另外之介電層、導電通孔及導電線路以形成所需數目之增層。
如此形成在該載體第一表面208上及在該載體第二表 面208'上之結構可以如在所屬技術領域中習知地利用一分板程序互相分開。第11圖顯示在分板後形成在該載體第一表面208上之結構。如第12圖所示，可例如，藉由蝕刻程序由該載體200移除在分板後留下之銅層202。如第13圖所示，如所屬技術領域中具有通常知識者可了解地，可例如，藉由電漿拋光、噴砂或溶劑脫離移除該第一犧牲材料層222以形成一微電子裝置封裝體290。因此，第3-13圖之製程形成一包含至少該高CTE材料層244及該第一高彈性模數材料層216之翹曲控制結構295。
如所屬技術領域中具有通常知識者可了解地，可進行另外之加工步驟，包括但不限於分割、堆疊及封裝。
第14-25圖顯示形成一埋入型無凸塊增層式無核心(BBUL-C)微電子封裝體之一製程之另一實施例的橫截面圖。如第14圖所示，可提供一載體，例如第3圖之載體200，且可在該載體上形成至少一支座。如圖所示，一第一微電子裝置附接墊312可形成在該載體第一表面208上且一第二微電子裝置附接墊312'可形成該載體第二表面208'上。如第14圖進一步所示，該第一微電子裝置附接墊312可以是例如一鎳層之一第一保護層314，及例如一銅層之一第一高彈性模數材料層316之層結構，且該第一保護層314抵靠該載體第一表面208並且該第一高彈性模數材料層316抵靠該第一保護層314。又，該第二微電子裝置附接墊312'亦可是例如一鎳層之一第二保護層314'，及例如一銅層之一第二高彈性模數材料層316'之層結構，且該第二保護層314'抵靠該載體 第二表面208'並且該第二高彈性模數材料層316'抵靠該第二保護層314'。
如第15圖所示，多數疊合式封裝(PoP)墊可形成在該載體第一表面208上及在該載體第二表面208'上。第15圖顯示一第一疊合式封裝墊328a及一形成在該載體第一表面208上之第二疊合式封裝墊328b，以及一第三疊合式封裝墊328a'及一形成在該載體第二表面208'上之第四疊合式封裝墊328b'。該等疊合式封裝墊(例如，元件328a、328b、328a'、328b')可以是層狀金屬結構，例如一金、鎳及銅層，且該層狀金屬結構可藉由包括但不限於鍍敷之在所屬技術領域中習知之任何技術圖案化。
如第16圖所示，一第一微電子裝置342可藉由其一背面350與一高CTE材料344一起附接在該第一微電子裝置附接墊312上。該第一微電子裝置342可在其一主動表面348上具有至少一接觸焊墊(顯示為元件346a與346b)。一第二微電子裝置342'可藉由其一背面350'與一高CTE材料344'一起附接在該第二微電子裝置附接墊312'上。該第二微電子裝置342'可在其一主動表面348'上具有至少一接觸焊墊(顯示為元件346a'與346b')。該第一微電子裝置342及該第二微電子裝置342'可以是任何所需裝置，包括但不限於一微處理器(單核心或多核心)，一記憶體裝置，一晶片組，一繪圖裝置，一特殊應用積體電路等。該等高CTE材料344與244'可為任何適當材料，包括但不限於晶粒背側薄膜材料。
如第17圖所示，一第一封裝層352可形成在該第一微電 子裝置342，該載體第一表面208，該第一疊合式封裝墊328a，及該第二疊合式封裝墊328b上。一第二封裝層352'可同時形成在該第二微電子裝置342'，該第三疊合式封裝墊328a'，及該第四疊合式封裝墊328b'上。在一實施例中，該第一封裝層352及該第二封裝層352'可包含填二氧化矽環氧樹脂。
如第18圖所示，一第一增層362可形成在該第一封裝層352上。該第一增層362可包含多數介電層，且多數導電線路與各介電層相鄰地形成並且多數導電通孔延伸穿過各介電層以連接在不同層上之導電線路。請參閱第18圖，該第一增層362可包含至少一第一層導電線路372，且一第一增建介電層374與該第一層導電線路372及該第一封裝層352相鄰地形成。至少一線路至裝置導電通孔376可延伸穿過該第一增建介電層374以連接至少一第一層導電線路372與至少一微電子裝置接觸焊墊(例如元件346a與346b)。至少一線路至墊導電通孔378可延伸穿過該第一增建介電層374以連接至少一第一層導電線路372與至少一疊合式封裝墊(例如，元件328a與328b)。至少一第二層導電線路382可與該第一增建介電層374相鄰地形成且一第二增建介電層384可與該第二層導電線路382及該第一增建介電層374相鄰地形成。至少一線路至線路導電通孔386可延伸穿過該第一增建介電層374以連接至少一第一層導電線路372與至少一第二層導電線路382。至少一第三層導電線路392可形成在該第二增建介電層384上且至少一線路至線路導電通孔386可延 伸穿過該第二增建介電層384以連接至少一第二層導電線路382與至少一第三層導電線路392。一阻焊材料394可在該第二增建介電層384及該第三層導電線路392上圖案化且具有至少一暴露該第三層導電線路392之至少一部份的開口396。應了解的是例如焊料球之多數互連結構(未顯示)可形成在該(等)第三層導電線路392上穿過該(等)阻焊材料開口396。
如第18圖進一步所示，一第二增層362'可形成在該第二封裝層352'上。該第二增層362'可包含多數介電層，且多數導電線路與各介電層相鄰地形成並且多數導電通孔延伸穿過各介電層以連接在不同層上之導電線路。請參閱第18圖，該第二增層362'可包含至少一第一層導電線路372'，且一第一增建介電層374'與該第一層導電線路372'及該第二封裝層352'相鄰地形成。至少一線路至裝置導電通孔376'可延伸穿過該第一增建介電層374'以連接至少一第一層導電線路372'與至少一微電子裝置接觸焊墊(例如元件346a'與346b')。至少一線路至墊導電通孔378'可延伸穿過該第一增建介電層374'以連接至少一第一層導電線路372'與至少一疊合式封裝墊(例如，元件328a'與328b')。至少一第二層導電線路382'可與該第一增建介電層374'相鄰地形成且一第二增建介電層384'可與該第二層導電線路382'及該第一增建介電層374'相鄰地形成。至少一線路至線路導電通孔386'可延伸穿過該第一增建介電層374'以連接至少一第一層導電線路372'與至少一第二層導電線路382'。至少一第三層導 電線路392'可形成在該第二增建介電層384'上且至少一線路至線路導電通孔386'可延伸穿過該第二增建介電層384'以連接至少一第二層導電線路382'與至少一第三層導電線路392'。一阻焊材料394'可在該第二增建介電層384'及該第三層導電線路392'上圖案化且具有至少一暴露該第三層導電線路392'之至少一部份的開口396'。應了解的是例如焊料球之多數互連結構(未顯示)可形成在該(等)第三層導電線路392'上穿過該(等)阻焊材料開口396'。
該等線路(例如元件372、372'、382、382'、392及3°92')可以是包括但不限於銅、鋁、銀、金及其合金之任何適當導電材料，且可由包括但不限於光刻法及鍍敷法之在所屬技術領域中習知之任何技術製成。該等導電通孔(例如元件376、376'、378、378'、386及386')可以是包括但不限於銅、鋁、銀、金及其合金之任何適當導電材料，且可由包括但不限於雷射鑽孔法、離子鑽孔、光刻法、鍍敷法及沈積法之在所屬技術領域中習知之任何技術製成。
應了解的是可增建另外之介電層、導電通孔及導電線路以形成所需數目之增層。
如此形成在該載體第一表面208上及在該載體第二表面208'上之結構可以如在所屬技術領域中習知地利用一分板程序互相分開。第19圖顯示在分板後形成在該載體第一表面208上之結構。如第20圖所示，可例如，藉由蝕刻程序由該載體200移除在分板後留下之銅層202，以形成一微電子裝置封裝體390。因此，第14-20圖之製程形成一包含至 少該高CTE材料層344及該高彈性模數材料層316之翹曲控制結構395。
如所屬技術領域中具有通常知識者可了解地，可進行另外之加工步驟，包括但不限於分割、堆疊及封裝。
在此應了解的是本發明之標的物不一定限定於第1-20圖所示之特定應用。該標的物可應用於包括會與翹曲有關之其他無核心及薄核心封裝體的其他微電子裝置封裝應用。此外，包括但不限於玻璃布積層、模製等在所屬技術領域中習知之其他翹曲減少技術可與本發明之標的物組合。另外，如所屬技術領域中具有通常知識者可了解地，本發明之標的物可以是一更大之無凸塊增層式封裝體之一部份，它可包括多數堆疊微電子晶粒，它可以一晶圓級，或任何次數之適當變化形成。又，該標的物亦可被使用在該微電子裝置製造領域以外之任何適當應用中。
已如此詳細說明了本發明之實施例，應了解的是由於在不偏離本發明之精神或範疇之情形下可有許多其顯而易見之變化，因此由附加申請專利範圍界定之發明不受限於在在以上說明中提出之特定細節。
100‧‧‧微電子封裝體
102‧‧‧微電子裝置
104‧‧‧主動表面
106‧‧‧接觸焊墊
108‧‧‧背面
110‧‧‧側
112‧‧‧封裝材料
114‧‧‧第一表面
116‧‧‧第二表面
122‧‧‧增層
132‧‧‧第一層導電線路
134‧‧‧第一增建介電層
136‧‧‧線路至裝置導電通孔
142‧‧‧第二層導電線路
144‧‧‧第二增建介電層
146‧‧‧線路至線路導電通孔
152‧‧‧第三層導電線路
154‧‧‧阻焊材料
156‧‧‧開口
162‧‧‧疊合式封裝(PoP)墊
172‧‧‧晶粒背側薄膜
180‧‧‧翹曲控制結構
182‧‧‧高熱膨脹係數(CTE)材料層
184‧‧‧高彈性模數材料層
190‧‧‧翹曲控制結構
200‧‧‧載體
202‧‧‧第一銅層
202'‧‧‧第二銅層
204‧‧‧第一銅釋放層
204'‧‧‧第二銅釋放層
206‧‧‧心材
208‧‧‧第一表面
208'‧‧‧第二表面
212‧‧‧第一微電子裝置附接墊
212'‧‧‧第二微電子裝置附接墊
214‧‧‧第一保護層
214'‧‧‧第二保護層
216‧‧‧第一高彈性模數材料層
216'‧‧‧第二高彈性模數材料層
222‧‧‧第一犧牲材料層
222'‧‧‧第二犧牲材料層
224,224'‧‧‧開口
228a‧‧‧第一疊合式封裝墊
228b‧‧‧第二疊合式封裝墊
228a'‧‧‧第三疊合式封裝墊
228b'‧‧‧第四疊合式封裝墊
242‧‧‧第一微電子裝置
242'‧‧‧第二微電子裝置
244,244'‧‧‧高CTE材料層
246a,246b‧‧‧接觸焊墊
246a',246b'‧‧‧接觸焊墊
248,248'‧‧‧主動表面
250,250'‧‧‧背面
252‧‧‧第一封裝層
252'‧‧‧第二封裝層
262‧‧‧第一增層
262'‧‧‧第二增層
272,272'‧‧‧第一層導電線路
274,274'‧‧‧第一增建介電層
276,276'‧‧‧線路至裝置導電通孔
278,278'‧‧‧線路至墊導電通孔
282,282'‧‧‧第二層導電線路
284,284'‧‧‧第二增建介電層
286,286'‧‧‧線路至線路導電通孔
290‧‧‧微電子裝置封裝體
292,292'‧‧‧第三層導電線路
294,294'‧‧‧阻焊材料
295‧‧‧翹曲控制結構
296,296'‧‧‧開口
312‧‧‧第一微電子裝置附接墊
312'‧‧‧第二微電子裝置附接墊
314‧‧‧第一保護層
314'‧‧‧第二保護層
316‧‧‧第一高彈性模數材料層
316'‧‧‧第二高彈性模數材料層
328a‧‧‧第一疊合式封裝墊
328b‧‧‧第二疊合式封裝墊
328a'‧‧‧第三疊合式封裝墊
328b'‧‧‧第四疊合式封裝墊
342‧‧‧第一微電子裝置
342'‧‧‧第二微電子裝置
344,344'‧‧‧高CTE材料
346a,346b‧‧‧接觸焊墊
346a',346b'‧‧‧接觸焊墊
348,348'‧‧‧主動表面
350,350'‧‧‧背面
352‧‧‧第一封裝層
352'‧‧‧第二封裝層
362‧‧‧第一增層
362'‧‧‧第二增層
372,372'‧‧‧第一層導電線路
374,374'‧‧‧第一增建介電層
376,376'‧‧‧線路至裝置導電通孔
378,378'‧‧‧線路至墊導電通孔
382,382'‧‧‧第二層導電線路
384,384'‧‧‧第二增建介電層
386,386'‧‧‧線路至線路導電通孔
390‧‧‧微電子裝置封裝體
392,392'‧‧‧第三層導電線路
394,394'‧‧‧阻焊材料
395‧‧‧翹曲控制結構
396,396'‧‧‧開口
第1圖顯示依據本發明一實施例之一無凸塊增層式無核心微電子封裝體的側橫截面圖。
第2圖顯示依據本發明另一實施例之一無凸塊增層式無核心微電子封裝體的側橫截面圖。
第3-13圖顯示依據本發明一實施例之形成一凹孔型無 凸塊增層式無核心微電子封裝體之一製程的橫截面圖。
第14-20圖顯示依據本發明一實施例之形成一埋入型無凸塊增層式無核心微電子封裝體之一製程的橫截面圖。
100‧‧‧微電子封裝體
102‧‧‧微電子裝置
104‧‧‧主動表面
106‧‧‧接觸焊墊
108‧‧‧背面
110‧‧‧側
112‧‧‧封裝材料
114‧‧‧第一表面
116‧‧‧第二表面
122‧‧‧增層
132‧‧‧第一層導電線路
134‧‧‧第一增建介電層
136‧‧‧線路至裝置導電通孔
142‧‧‧第二層導電線路
144‧‧‧第二增建介電層
142‧‧‧第二層導電線路
144‧‧‧第二增建介電層
146‧‧‧線路至線路導電通孔
152‧‧‧第三層導電線路
154‧‧‧阻焊材料
156‧‧‧開口
162‧‧‧疊合式封裝(PoP)墊
172‧‧‧晶粒背側薄膜
180‧‧‧翹曲控制結構
182‧‧‧高熱膨脹係數(CTE)材料層
184‧‧‧高彈性模數材料層

Claims (20)

  1. 一種微電子封裝體，包含：一微電子裝置，其具有一主動表面、一相對的背面、及至少一側；及一翹曲控制結構，其與該微電子裝置背面相鄰，其中該翹曲控制結構包括一高熱膨脹係數材料層及一高彈性模數材料層。
  2. 如申請專利範圍第1項之微電子封裝體，其中該高熱膨脹係數材料層包含一材料，且該材料具有一大於約25ppm/℃之熱膨脹係數。
  3. 如申請專利範圍第1項之微電子封裝體，其中該高熱膨脹係數材料層包含一填充環氧樹脂材料層。
  4. 如申請專利範圍第1項之微電子封裝體，其中該高彈性模數材料層包含一材料層，且該材料層具有一大於約50GPa之模數。
  5. 如申請專利範圍第1項之微電子封裝體，其中高彈性模數材料層包含一金屬層。
  6. 如申請專利範圍第1項之微電子封裝體，更包括一封裝材料，且該封裝材料係相鄰該微電子裝置主動表面之至少一部份及至少一微電子裝置側之至少一部份而設置。
  7. 如申請專利範圍第6項之微電子封裝體，更包括一增層，且該增層係形成在靠近該微電子裝置主動表面之該封裝材料之一第一表面上。
  8. 一種製造一微電子封裝體之方法，其包含下列步驟： 形成一微電子裝置，且該微電子裝置具有一主動表面、一相對的背面、及至少一側；及形成一與該微電子裝置背面相鄰之翹曲控制結構，其包含形成與一高彈性模數材料層相鄰之一高熱膨脹係數材料層。
  9. 如申請專利範圍第8項之方法，其中形成該高熱膨脹係數材料層之步驟包含在該微電子裝置背面上形成該高熱膨脹係數材料層。
  10. 如申請專利範圍第8項之方法，其中形成該高熱膨脹係數材料層之步驟包含形成具有一大於約25ppm/℃之熱膨脹係數之一材料層。
  11. 如申請專利範圍第8項之方法，其中形成該高熱膨脹係數材料層之步驟包含形成一填充環氧樹脂材料層。
  12. 如申請專利範圍第8項之方法，其中形成該高彈性模數材料層之步驟包含形成具有一大於約50GPa之模數之一材料層。
  13. 如申請專利範圍第8項之方法，更包括相鄰該微電子裝置主動表面之至少一部份及至少一微電子裝置側之至少一部份設置一封裝材料。
  14. 如申請專利範圍第8項之方法，更包括在靠近該微電子裝置主動表面之該封裝材料之一第一表面上形成一增層。
  15. 一種製造一微電子封裝體之方法，其包含下列步驟：提供一載體； 在該載體上形成一微電子裝置附接墊，其中該微電子裝置附接墊包括一高彈性模數材料層；附接具有一主動表面、一相對的背面、及至少一側之一微電子裝置在該微電子裝置附接墊上，其中附接該微電子裝置之步驟包括將一高熱膨脹係數材料層設置在該微電子裝置背面與該微電子裝置附接墊之間；相鄰該微電子裝置主動表面之至少一部份及至少一微電子裝置側之至少一部份相鄰設置一封裝材料；及移除該載體。
  16. 如申請專利範圍第15項之方法，其中將一高熱膨脹係數材料層設置在該微電子裝置背面與該微電子裝置附接墊之間的步驟包含將具有一大於約25ppm/℃之熱膨脹係數之一材料層設置在該微電子裝置背面與該微電子裝置附接墊之間。
  17. 如申請專利範圍第15項之方法，其中將一高熱膨脹係數材料層設置在該微電子裝置背面與該微電子裝置附接墊之間的步驟包含將一填充環氧樹脂材料層設置在該微電子裝置背面與該微電子裝置附接墊之間。
  18. 如申請專利範圍第15項之方法，其中在該載體上形成一微電子裝置附接墊之步驟包含在該載體上形成一微電子裝置附接墊，其中該微電子裝置附接墊包括具有一大於約50GPa之模數之一高彈性模數材料層。
  19. 如申請專利範圍第15項之方法，其中設置該封裝材料之步驟包含相鄰該微電子裝置主動表面之至少一部份及 至少一微電子裝置側之至少一部份設置一填充環氧樹脂材料。
  20. 如申請專利範圍第15項之方法，更包括在靠近該微電子裝置主動表面之該封裝材料之一第一表面上形成一增層。
TW101120105A 2011-06-30 2012-06-05 無凸塊增層式封裝體翹曲降低技術 TWI578469B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/173,327 US8848380B2 (en) 2011-06-30 2011-06-30 Bumpless build-up layer package warpage reduction

Publications (2)

Publication Number Publication Date
TW201301466A true TW201301466A (zh) 2013-01-01
TWI578469B TWI578469B (zh) 2017-04-11

Family

ID=47390489

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101120105A TWI578469B (zh) 2011-06-30 2012-06-05 無凸塊增層式封裝體翹曲降低技術

Country Status (5)

Country Link
US (2) US8848380B2 (zh)
KR (1) KR101579823B1 (zh)
CN (1) CN103635996B (zh)
TW (1) TWI578469B (zh)
WO (1) WO2013003695A2 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI624021B (zh) * 2013-04-23 2018-05-11 萬國半導體（開曼）股份有限公司 薄型功率器件及其製備方法
TWI704660B (zh) * 2015-09-23 2020-09-11 美商英特爾公司 用以致能多晶片覆晶封裝之基體、總成及技術
TWI764230B (zh) * 2019-08-23 2022-05-11 美商美光科技公司 微電子封裝中之翹曲控制、及其相關組件及方法

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US8780576B2 (en) * 2011-09-14 2014-07-15 Invensas Corporation Low CTE interposer
US9679863B2 (en) 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
WO2013089754A1 (en) * 2011-12-15 2013-06-20 Intel Corporation Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (bbul) packages
CN104137257B (zh) * 2011-12-21 2017-11-21 英特尔公司 封装的半导体管芯和cte工程管芯对
WO2013172814A1 (en) 2012-05-14 2013-11-21 Intel Corporation Microelectronic package utilizing multiple bumpless build-up structures and through-silicon vias
WO2013184145A1 (en) 2012-06-08 2013-12-12 Intel Corporation Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer
US20140158414A1 (en) * 2012-12-11 2014-06-12 Chris Baldwin Recessed discrete component mounting on organic substrate
US9320149B2 (en) * 2012-12-21 2016-04-19 Intel Corporation Bumpless build-up layer package including a release layer
US9685414B2 (en) 2013-06-26 2017-06-20 Intel Corporation Package assembly for embedded die and associated techniques and configurations
US8980691B2 (en) * 2013-06-28 2015-03-17 Stats Chippac, Ltd. Semiconductor device and method of forming low profile 3D fan-out package
US9006901B2 (en) 2013-07-19 2015-04-14 Alpha & Omega Semiconductor, Inc. Thin power device and preparation method thereof
DE102013107947A1 (de) * 2013-07-25 2015-02-19 Acquandas GmbH Verfahren zur Herstellung einer medizinischen Vorrichtung, Verfahren zum Modifizieren der Oberfläche einer medizinischen Vorrichtung, medizinische Vorrichtung und Schichtverbund mit einem Substrat
US20150084171A1 (en) * 2013-09-23 2015-03-26 Stmicroelectronics Pte. Ltd. No-lead semiconductor package and method of manufacturing the same
US9379041B2 (en) * 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
KR102250997B1 (ko) 2014-05-02 2021-05-12 삼성전자주식회사 반도체 패키지
US9754849B2 (en) * 2014-12-23 2017-09-05 Intel Corporation Organic-inorganic hybrid structure for integrated circuit packages
KR101605172B1 (ko) 2015-04-07 2016-03-22 삼성전자주식회사 패키지 기판 및 그 제조방법
US9929100B2 (en) 2015-04-17 2018-03-27 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
US9837484B2 (en) 2015-05-27 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming substrate including embedded component with symmetrical structure
US20180005916A1 (en) * 2016-06-30 2018-01-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN108172551B (zh) * 2016-11-29 2022-04-29 Pep创新私人有限公司 芯片封装方法及封装结构
CN110268510B (zh) 2016-12-22 2021-11-23 厦门四合微电子有限公司 一种分立器件的封装方法及分立器件
CN106783631B (zh) * 2016-12-22 2020-01-14 深圳中科四合科技有限公司 一种二极管的封装方法及二极管
CN106783632B (zh) * 2016-12-22 2019-08-30 深圳中科四合科技有限公司 一种三极管的封装方法及三极管
US10541211B2 (en) 2017-04-13 2020-01-21 International Business Machines Corporation Control warpage in a semiconductor chip package
WO2019005152A1 (en) * 2017-06-30 2019-01-03 Intel Corporation CHIP REAR FRONT STRUCTURES FOR AN ARROW CONTROL
US10297544B2 (en) * 2017-09-26 2019-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
KR102008343B1 (ko) * 2017-09-27 2019-08-07 삼성전자주식회사 팬-아웃 반도체 패키지
US11232957B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and package structure
US11233028B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and chip structure
US11610855B2 (en) 2017-11-29 2023-03-21 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US11114315B2 (en) 2017-11-29 2021-09-07 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US10636746B2 (en) 2018-02-26 2020-04-28 International Business Machines Corporation Method of forming an electronic package
US20220278053A1 (en) * 2019-03-29 2022-09-01 Nepes Co., Ltd. Semiconductor package and method for manufacturing same
US20210296194A1 (en) * 2020-03-18 2021-09-23 Advanced Micro Devices, Inc Molded semiconductor chip package with stair-step molding layer

Family Cites Families (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4921160A (en) 1988-02-29 1990-05-01 American Telephone And Telegraph Company Personal data card and method of constructing the same
US5510649A (en) * 1992-05-18 1996-04-23 Motorola, Inc. Ceramic semiconductor package having varying conductive bonds
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5527741A (en) 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
TW340967B (en) * 1996-02-19 1998-09-21 Toray Industries An adhesive sheet for a semiconductor to connect with a substrate, and adhesive sticking tape for tab, an adhesive sticking tape for wire bonding connection, a substrate for connecting with a semiconductor and a semiconductor device
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US5866953A (en) 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
US5899705A (en) 1997-11-20 1999-05-04 Akram; Salman Stacked leads-over chip multi-chip module
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6239482B1 (en) 1999-06-21 2001-05-29 General Electric Company Integrated circuit package including window frame
US6312972B1 (en) 1999-08-09 2001-11-06 International Business Machines Corporation Pre-bond encapsulation of area array terminated chip and wafer scale packages
US6242282B1 (en) 1999-10-04 2001-06-05 General Electric Company Circuit chip package and fabrication method
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6555908B1 (en) 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US6426545B1 (en) 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6586836B1 (en) 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
US6734534B1 (en) 2000-08-16 2004-05-11 Intel Corporation Microelectronic substrate with integrated devices
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6586822B1 (en) 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
US6713859B1 (en) 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
US6489185B1 (en) 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
US6399892B1 (en) 2000-09-19 2002-06-04 International Business Machines Corporation CTE compensated chip interposer
US6617682B1 (en) 2000-09-28 2003-09-09 Intel Corporation Structure for reducing die corner and edge stresses in microelectronic packages
US6709898B1 (en) 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6703400B2 (en) 2001-02-23 2004-03-09 Schering Corporation Methods for treating multidrug resistance
US6706553B2 (en) 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
JP3878430B2 (ja) 2001-04-06 2007-02-07 株式会社ルネサステクノロジ 半導体装置
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US6586276B2 (en) 2001-07-11 2003-07-01 Intel Corporation Method for fabricating a microelectronic device using wafer-level adhesion layer deposition
US6472762B1 (en) * 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US6580611B1 (en) 2001-12-21 2003-06-17 Intel Corporation Dual-sided heat removal system
US6841413B2 (en) 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
JP3938759B2 (ja) 2002-05-31 2007-06-27 富士通株式会社 半導体装置及び半導体装置の製造方法
JP2004200201A (ja) 2002-12-16 2004-07-15 Taiyo Yuden Co Ltd 電子部品内蔵型多層基板
US7294533B2 (en) 2003-06-30 2007-11-13 Intel Corporation Mold compound cap in a flip chip multi-matrix array package and process of making same
US6784535B1 (en) * 2003-07-31 2004-08-31 Texas Instruments Incorporated Composite lid for land grid array (LGA) flip-chip package assembly
US6909176B1 (en) * 2003-11-20 2005-06-21 Altera Corporation Structure and material for assembling a low-K Si die to achieve a low warpage and industrial grade reliability flip chip package with organic substrate
KR100632472B1 (ko) 2004-04-14 2006-10-09 삼성전자주식회사 측벽이 비도전성인 미세 피치 범프 구조를 가지는미세전자소자칩, 이의 패키지, 이를 포함하는액정디스플레이장치 및 이의 제조방법
US20060009744A1 (en) 2004-07-09 2006-01-12 Erdman Edward P Decorative component for an absorbent article
US7442581B2 (en) 2004-12-10 2008-10-28 Freescale Semiconductor, Inc. Flexible carrier and release method for high volume electronic package fabrication
KR100593703B1 (ko) 2004-12-10 2006-06-30 삼성전자주식회사 돌출부 와이어 본딩 구조 보강용 더미 칩을 포함하는반도체 칩 적층 패키지
TWI245388B (en) 2005-01-06 2005-12-11 Phoenix Prec Technology Corp Three dimensional package structure of semiconductor chip embedded in substrate and method for fabricating the same
US7109055B2 (en) 2005-01-20 2006-09-19 Freescale Semiconductor, Inc. Methods and apparatus having wafer level chip scale package for sensing elements
TWI269423B (en) * 2005-02-02 2006-12-21 Phoenix Prec Technology Corp Substrate assembly with direct electrical connection as a semiconductor package
US7160755B2 (en) 2005-04-18 2007-01-09 Freescale Semiconductor, Inc. Method of forming a substrateless semiconductor package
WO2007001018A1 (ja) 2005-06-29 2007-01-04 Rohm Co., Ltd. 半導体装置および半導体装置集合体
US7459782B1 (en) * 2005-10-05 2008-12-02 Altera Corporation Stiffener for flip chip BGA package
US7425464B2 (en) 2006-03-10 2008-09-16 Freescale Semiconductor, Inc. Semiconductor device packaging
US20070279885A1 (en) 2006-05-31 2007-12-06 Basavanhally Nagesh R Backages with buried electrical feedthroughs
TWI301663B (en) 2006-08-02 2008-10-01 Phoenix Prec Technology Corp Circuit board structure with embedded semiconductor chip and fabrication method thereof
US7723164B2 (en) 2006-09-01 2010-05-25 Intel Corporation Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same
US7659143B2 (en) 2006-09-29 2010-02-09 Intel Corporation Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same
US7476563B2 (en) 2006-11-17 2009-01-13 Freescale Semiconductor, Inc. Method of packaging a device using a dielectric layer
US7588951B2 (en) 2006-11-17 2009-09-15 Freescale Semiconductor, Inc. Method of packaging a semiconductor device and a prefabricated connector
JP4897451B2 (ja) 2006-12-04 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置
US7632715B2 (en) 2007-01-05 2009-12-15 Freescale Semiconductor, Inc. Method of packaging semiconductor devices
US8237259B2 (en) * 2007-06-13 2012-08-07 Infineon Technologies Ag Embedded chip package
TW200903756A (en) * 2007-06-18 2009-01-16 Samsung Electronics Co Ltd Semiconductor chip package, semiconductor package including semiconductor chip package, and method of fabricating semiconductor package
US7648858B2 (en) 2007-06-19 2010-01-19 Freescale Semiconductor, Inc. Methods and apparatus for EMI shielding in multi-chip modules
TW200901409A (en) 2007-06-22 2009-01-01 Nan Ya Printed Circuit Board Corp Packaging substrate with embedded chip and buried heatsink
US8384199B2 (en) 2007-06-25 2013-02-26 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
JP4752825B2 (ja) 2007-08-24 2011-08-17 カシオ計算機株式会社 半導体装置の製造方法
US7595226B2 (en) 2007-08-29 2009-09-29 Freescale Semiconductor, Inc. Method of packaging an integrated circuit die
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
US20090072382A1 (en) 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
US9941245B2 (en) 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US20090079064A1 (en) 2007-09-25 2009-03-26 Jiamiao Tang Methods of forming a thin tim coreless high density bump-less package and structures formed thereby
US7851905B2 (en) 2007-09-26 2010-12-14 Intel Corporation Microelectronic package and method of cooling an interconnect feature in same
JP2009105366A (ja) * 2007-10-03 2009-05-14 Panasonic Corp 半導体装置及び半導体装置の製造方法ならびに半導体装置の実装体
US20090152743A1 (en) 2007-12-15 2009-06-18 Houssam Jomaa Routing layer for a microelectronic device, microelectronic package containing same, and method of forming a multi-thickness conductor in same for a microelectronic device
US8035216B2 (en) 2008-02-22 2011-10-11 Intel Corporation Integrated circuit package and method of manufacturing same
JP4828559B2 (ja) 2008-03-24 2011-11-30 新光電気工業株式会社 配線基板の製造方法及び電子装置の製造方法
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
US7847415B2 (en) 2008-07-18 2010-12-07 Qimonda Ag Method for manufacturing a multichip module assembly
US20100073894A1 (en) 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
US7633143B1 (en) * 2008-09-22 2009-12-15 Powertech Technology Inc. Semiconductor package having plural chips side by side arranged on a leadframe
US7935571B2 (en) 2008-11-25 2011-05-03 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
US7901981B2 (en) * 2009-02-20 2011-03-08 National Semiconductor Corporation Integrated circuit micro-module
US20100237481A1 (en) 2009-03-20 2010-09-23 Chi Heejo Integrated circuit packaging system with dual sided connection and method of manufacture thereof
US20110156261A1 (en) 2009-03-24 2011-06-30 Christopher James Kapusta Integrated circuit package and method of making same
US8222716B2 (en) 2009-10-16 2012-07-17 National Semiconductor Corporation Multiple leadframe package
US20110108999A1 (en) 2009-11-06 2011-05-12 Nalla Ravi K Microelectronic package and method of manufacturing same
US8034661B2 (en) 2009-11-25 2011-10-11 Stats Chippac, Ltd. Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP
US8742561B2 (en) 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8247900B2 (en) * 2009-12-29 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Flip chip package having enhanced thermal and mechanical performance
US8497587B2 (en) * 2009-12-30 2013-07-30 Stmicroelectronics Pte Ltd. Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
JP5460388B2 (ja) 2010-03-10 2014-04-02 新光電気工業株式会社 半導体装置及びその製造方法
US8891246B2 (en) 2010-03-17 2014-11-18 Intel Corporation System-in-package using embedded-die coreless substrates, and processes of forming same
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8431438B2 (en) 2010-04-06 2013-04-30 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US8264849B2 (en) 2010-06-23 2012-09-11 Intel Corporation Mold compounds in improved embedded-die coreless substrates, and processes of forming same
US20110316140A1 (en) 2010-06-29 2011-12-29 Nalla Ravi K Microelectronic package and method of manufacturing same
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8786066B2 (en) 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
JP5598212B2 (ja) 2010-09-29 2014-10-01 パナソニック株式会社 ハイブリッドコア基板とその製造方法、半導体集積回路パッケージ、及びビルドアップ基板とその製造方法
US20120112336A1 (en) 2010-11-05 2012-05-10 Guzek John S Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
US20120139095A1 (en) 2010-12-03 2012-06-07 Manusharow Mathew J Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same
US8508037B2 (en) 2010-12-07 2013-08-13 Intel Corporation Bumpless build-up layer and laminated core hybrid structures and methods of assembling same
TW201250947A (en) * 2011-05-12 2012-12-16 Siliconware Precision Industries Co Ltd Package structure having a micromechanical electronic component and method of making same
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US9159649B2 (en) 2011-12-20 2015-10-13 Intel Corporation Microelectronic package and stacked microelectronic assembly and computing system containing same
US8975157B2 (en) 2012-02-08 2015-03-10 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
WO2013172814A1 (en) 2012-05-14 2013-11-21 Intel Corporation Microelectronic package utilizing multiple bumpless build-up structures and through-silicon vias
WO2013184145A1 (en) 2012-06-08 2013-12-12 Intel Corporation Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI624021B (zh) * 2013-04-23 2018-05-11 萬國半導體（開曼）股份有限公司 薄型功率器件及其製備方法
TWI704660B (zh) * 2015-09-23 2020-09-11 美商英特爾公司 用以致能多晶片覆晶封裝之基體、總成及技術
TWI764230B (zh) * 2019-08-23 2022-05-11 美商美光科技公司 微電子封裝中之翹曲控制、及其相關組件及方法
US11855002B2 (en) 2019-08-23 2023-12-26 Micron Technology, Inc. Warpage control in microelectronic packages, and related assemblies and methods

Also Published As

Publication number Publication date
US20140363929A1 (en) 2014-12-11
WO2013003695A3 (en) 2013-05-02
KR101579823B1 (ko) 2015-12-24
CN103635996A (zh) 2014-03-12
US9627227B2 (en) 2017-04-18
WO2013003695A2 (en) 2013-01-03
TWI578469B (zh) 2017-04-11
US8848380B2 (en) 2014-09-30
US20130003319A1 (en) 2013-01-03
KR20140026570A (ko) 2014-03-05
CN103635996B (zh) 2016-08-17

Similar Documents

Publication Publication Date Title
TWI578469B (zh) 無凸塊增層式封裝體翹曲降低技術
US7189596B1 (en) Process for forming a direct build-up layer on an encapsulated die packages utilizing intermediate structures
US9196597B2 (en) Semiconductor package with single sided substrate design and manufacturing methods thereof
TWI525774B (zh) 晶片封裝體
TWI649845B (zh) 半導體封裝結構及其製造方法
JP2010034403A (ja) 配線基板及び電子部品装置
US11127664B2 (en) Circuit board and manufacturing method thereof
TWI754839B (zh) 封裝結構及其形成方法
TW201220450A (en) Wafer level semiconductor package and manufacturing methods thereof
JP2009252859A (ja) 半導体装置及びその製造方法
TWI594382B (zh) 電子封裝件及其製法
JP2017017300A (ja) チップパッケージ
JP2010147096A (ja) 半導体装置及び半導体装置の製造方法
US9425066B2 (en) Circuit substrate
US20220375919A1 (en) Manufacturing method of package structure
TW201438159A (zh) 超薄封裝上封裝ＰｏＰ之封裝
TWI463622B (zh) 具有單側基板設計的半導體封裝及其製造方法
TW201944551A (zh) 封裝結構及其製造方法
US20200068721A1 (en) Package structure and manufacturing method thereof
TWI520238B (zh) 半導體封裝件及其製法
TWI830726B (zh) 創新的扇出型板層級封裝(foplp)翹曲控制技術
CN114023662A (zh) 扇出型封装结构
CN112435930A (zh) 封装结构及其制造方法
TW201947709A (zh) 創新的扇出型板層級封裝(foplp)翹曲控制技術
JP2005005730A (ja) 回路装置の製造方法