CN103635996B - 无焊内建层封装的翘曲减小 - Google Patents

无焊内建层封装的翘曲减小 Download PDF

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CN103635996B
CN103635996B CN201280032555.3A CN201280032555A CN103635996B CN 103635996 B CN103635996 B CN 103635996B CN 201280032555 A CN201280032555 A CN 201280032555A CN 103635996 B CN103635996 B CN 103635996B
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microelectronic component
layer
material layer
encapsulating material
back surfaces
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CN103635996A (zh
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P·马拉特卡尔
D·W·德莱尼
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Intel Corp
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Intel Corp
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Abstract

本公开内容涉及制造微电子封装及其制造方法的领域，其中，可以在无焊内建层无芯（BBUL-C）微电子封装内形成微电子器件，并且其中，可以在微电子器件的背部表面上设置翘曲控制结构。翘曲控制结构可以是层状结构，该层状结构包括：至少一个高热膨胀系数材料（包含但不限于填充环氧树脂材料）的层和至少一个高弹性模量材料的层（例如，金属层）。

Description

无焊内建层封装的翘曲减小
技术领域
概括地，本说明书的实施例涉及微电子器件封装设计的领域，并且更具体地，涉及具有无焊内建层（BBUL）设计的微电子器件封装。
附图说明
本公开内容的主题将在说明书的总结部分被特别指出并清楚地要求。从下面的描述和所附的权利要求、并且结合附图，本公开内容的前述及其他特征将得以更加完整体现。应当理解这些附图描述了根据本公开内容的仅仅几个实施例，因此并不能认为是对其范围的限制。将通过使用附图而以附加的特性和细节对本公开内容进行描述，使得可以更容易确定本公开内容的优点，其中：
图1示出了根据本说明书的实施例的无焊内建层无芯微电子封装的侧截面图。
图2示出了根据本说明书的另一个实施例的无焊内建层无芯微电子封装的侧截面图。
图3-13示出了根据本说明书的实施例的形成腔式无焊内建层无芯微电子封装的过程的截面图。
图14-20示出了根据本说明书的实施例的形成嵌入式无焊内建层无芯微电子封装的过程的截面图。
具体实施方式
在下面的具体实施方式中，将参考以示例形式示出具体实施例的附图，所要求保护的主题可以在这些实施例中实施。这些实施例被描述得足够详细以让本领域技术人员能够实施本主题。应当理解，各种实施例虽然互不相同，也不一定互相排斥。例如，这里结合某一实施例所描述的特定特征、结构或特性可以运用在其他实施例内而不脱离所要求保护的主题的精神和范围。本说明书内所引用的“一个实施例”或“一实施例”意指就该实施例描述的特定的特征、结构或特性包含在本发明所涵盖的至少一个实施方式中。所以，短语“一个实施例”或“在一实施例中”的使用并不必然指向同一个实施例。此外，应当理解在每个所公开的实施例中的个体元件的位置和布置可以在不脱离所要求保护的主题的精神和范围的情况下做出修改。因此，下面的具体实施方式不应理解为具有限制意义，而本主题的范围仅由适当解释的所附权利要求、连同所附权利要求享有权利的等同形式的整个范围所限定。在附图中，相同的附图标记指代所有几个附图中相同的或相似的元件或功能，且其中所描绘的元件并不必须彼此成比例，而为了更易于理解本说明书上下文中的元件，可以放大或缩小个体元件。
本说明书的实施例涉及制造微电子封装及其制造方法的领域，其中，可以在无焊内建层无芯（BBUL-C）微电子封装内形成微电子器件，并且其中，可以在微电子器件的背部表面上设置翘曲控制结构。翘曲控制结构可以是层状结构，该层状结构包括：至少一个高热膨胀系数材料（包含但不限于硅石填充环氧树脂材料）的层和至少一个高弹性模量材料的层（例如，金属层）。这样的翘曲控制结构可以在室温下（大约25摄氏度）和在回流焊温度（例如，大约260摄氏度）下都有效地减小无焊内建层无芯微电子封装的翘曲。回流焊温度是互连焊料结构被加热到以便将微电子封装附接到外部器件（例如，母板）的温度。
本领域技术人员应当理解，翘曲方面的减小可以减少微电子器件损伤的可能性和/或在将微电子器件附接到外部器件期间的连接问题。此外，可以改善微电子封装内的微电子器件的性能，因为由于在翘曲方面的减小而产生的对微电子器件内的晶体管的面内压应力减小。
图1示出了腔式无焊内建层无芯（BBUL-C）微电子封装的实施例的截面图。如图1所示，微电子封装100可以包括基本上装入封装材料112中的微电子器件102，其中封装材料112可以邻接微电子器件102的有源表面104的至少一部分和微电子器件102的至少一侧110。微电子有源表面104可以具有形成在其中和/或其上的至少一个接触连接盘106。微电子器件102可以是任意期望的器件，包括但不限于：微处理器（单核或多核）、存储器器件、芯片组、图形器件、专用集成电路等。封装材料112可以是硅石填充环氧树脂，例如能够从Ajinomoto Fine-Techno Co.，Inc.，1-2Suzuki-cho，Kawasaki-ku，Kawasaki-shi，210-0801，Japan获得的内建膜（例如，Ajinomoto ABF-GX13，Ajinomoto GX92等）。
可以在靠近微电子器件有源表面104的封装材料112的第一表面114上形成内建层122。内建层122可以包括具有导电迹线的多个电介质层，所述导电迹线邻近各个电介质层而形成，其中，导电过孔穿过各个电介质层而延伸以连接不同的层上的导电迹线。参考图1，内建层122可以包括至少一个第一层导电迹线132，其中，第一内建电介质层134邻近第一层导电迹线132和封装材料112而形成。至少一个迹线-到-器件导电过孔136可以穿过第一内建电介质层134而延伸以将至少一个第一层导电迹线132连接到至少一个微电子器件接触连接盘106。至少一个第二层导电迹线142可以邻近第一内建电介质层134而形成，并且第二内建电介质层144可以邻近第二层导电迹线142和第一内建电介质层134而形成。至少一个迹线-到-迹线导电过孔146可以穿过第一内建电介质层134而延伸以将至少一个第一层导电迹线132连接到至少一个第二层导电迹线142。在第二内建电介质层144上可以形成至少一个第三层导电迹线152，并且至少一个迹线-到-迹线导电过孔146可以穿过第二内建电介质层144而延伸以将至少一个第二层导电迹线142连接到至少一个第三层导电迹线152。可以在第二内建电介质层144上对阻焊材料154进行构图，并且第三层导电迹线152具有至少一个开口部156，所述开口部暴露至少第三层导电迹线152的一部分。应当理解，互连结构（未示出），例如焊球，可以穿过阻焊材料开口部156而形成在第三层导电迹线152上。
可以在封装材料112的第二表面（基本上与封装材料第一表面114相对）上和/或中形成至少一个层叠封装（PoP）焊盘162。层叠封装焊盘162可以电气连接到至少一个第一层导电迹线132。如本领域技术人员应当理解的那样，层叠封装焊盘可以用来在用于进行堆叠（例如，被称为3D堆叠）的z方向上的微电子器件封装之间形成连接，而不需要穿过硅过孔。
如图1所示，可以在第一微电子器件102的背部表面108上设置管芯背面膜172，例如可以从Nitto Denko，110-1-1，Funayose，Maruoka，Sakai，Fukui，910-0381，Japan获得的Nitto NX2DBF材料。可以在管芯背面膜172上设置翘曲控制结构180，其中，翘曲控制结构180可以包括：设置在管芯背面膜172上的高热膨胀系数（CTE）材料层182和设置在高CTE材料层182上的高弹性模量材料层184。高CTE材料层182可以包括但不限于填充环氧树脂，例如硅石填充环氧树脂，该硅石填充环氧树脂包括但不限于可以从Ajinomoto Fine-Techno Co.，Inc.，1-2Suzuki-cho，Kawasaki-ku，Kawasaki-shi，210-0801，Japan获得的Ajinomoto ABF-GX13，AjinomotoGX92等。高弹性模量材料层184可以包括但不限于金属层，例如铜、镍、铝以及它们的合金。在一个实施例中，高CTE材料层182和高弹性模量材料层184可以与在用于微电子封装100的其他领域中所使用的材料相同或相似，从而本质上使得微电子封装100更加对称（例如，更少翘曲的可能性）。在一个实施例中，翘曲控制结构180包括高CTE材料层182和高弹性模量材料层184，其中，高CTE材料层182包括厚度大约在5μm和50μm之间的硅石填充环氧树脂，具体地约30μm的硅石填充环氧树脂，高弹性模量材料层184包括厚度在5μm和50μm之间的铜。
设置在微电子器件上的具有高CTE材料层和高弹性模量层两者的层状结构将产生较低的封装翘曲。在一个实施例中,高CTE材料层182可以大于大约25微米每米每摄氏度（“ppm/℃”），并且高弹性模量材料层184可以大于大约5千兆帕斯卡（“Gpa”）。应当理解，需要的最小CTE和弹性模量值可以随着微电子器件的厚度、产生的微电子封装的厚度和/或材料层的厚度而改变。最小CTE值与关注的温度有关，因为大部分环氧树脂材料的CTE值在它们的玻璃态转化温度之前（由CTE1表示）和在它们的玻璃态转化温度之后（由CTE2表示）可以完全不同。如果需要控制封装翘曲的温度（例如，室温或回流温度）低于将设置的材料的玻璃态转化温度，则最小CTE值将指CTE1的最小CTE值，如果需要控制封装翘曲的温度大于玻璃态转化温度，则最小CTE值指CTE2的最小CTE值。最小模量值总是指处于关注的温度的模量。
在本说明书的一个实施例中，如本领域技术人员应当理解的那样，翘曲控制结构180可以足够薄以适配在堆叠的封装结构（未示出）中的顶部封装（未示出）和底部封装（例如，微电子封装100）之间的间隙内，由此不增加堆叠的封装结构（未示出）的整体z高度。在另一个实施例中，可以选择高CTE材料层182和高弹性模量材料层184以使得翘曲可以在室温下（大约25摄氏度）和在回流焊温度（例如，大约260摄氏度）下都减小。
如图2所示，管芯背面膜（示为图1中的元件172）其自身可以充当高CTE材料层。在一个实施例中，可以直接在微电子器件背部表面108上设置翘曲控制结构190，其中，翘曲控制结构180可以包括设置在微电子器件背部表面108上的高CTE材料层182和设置在高CTE材料层182上的高弹性模量材料层184。高CTE材料层182可以包括但不限于管芯背面膜或粘附材料，例如可以从Nitto Denko，110-1-1，Funayose，Maruoka，Sakai，Fukui，910-0381，Japan获得的Nitto NX2DBF材料或可以从Nippon SteelChemical Co.Ltd.14-1Sotokanda4-Chome，Chiyoda-ku，Tokyo101-0021，Japan获得的NEX系列材料（例如，NEX-130CTX，NEX140DBF）。高弹性模量材料层184可以包括但不限于金属层，例如铜、镍、铝以及它们的合金。
图3-13示出了形成腔式无焊内建层无芯（BBUL-C）微电子封装的过程的实施例的截面图。如图3所示，可以提供载体200。所示的载体200可以是铜层叠衬底，其包括设置在两个相对的铜剥离层（即，第一铜剥离层204和第二铜剥离层204’）之间的芯部材料206，其中，两个相对的铜层（即，第一铜层202和第二铜层202’）邻接它们各自的铜剥离层（即，第一铜剥离层204和第二铜剥离层204’）且邻接芯部材料206的一部分，其中，第一铜层202的外部表面限定了载体200的第一表面208，并且第二铜层202’的外部表面限定了载体200的第二表面208’。芯部材料206可以是任何适当的材料，包括但不限于预浸渍的复合纤维材料。应当理解，虽然层叠有芯部材料206的层被具体指定为铜层（即，铜层和铜剥离层），但是本说明书并不作这样的限制，因为所述层可以由任何适当的材料制成。
如图4所示，可以在载体第一表面208上形成第一微电子器件附接焊盘212，并且可以在载体第二表面208’上形成第二微电子器件附接焊盘212’。进一步如图4所示，第一微电子器件附接焊盘212可以是邻接载体第一表面208的第一保护层214（例如第一镍层）和邻接第一保护层214的第一高弹性模量材料层216（例如第一铜层）的层叠结构，并且第二微电子器件附接焊盘212’也可以是邻接载体第二表面208’的第二保护层214’（例如第二镍层）和第二高弹性模量材料层216’的层叠结构，该第二高弹性模量材料层216'邻接第二保护层214’。如将讨论的那样，第一保护层214和第二保护层214’可以用来分别防止第一高弹性模量材料层216和第二高弹性模量材料层216’上的氧化物的形成，以及防止在后续的制造过程期间第一高弹性模量材料层216和第二高弹性模量材料层216’的蚀刻。
如图5所示，可以在载体第一表面208上和在第一微电子器件附接焊盘212上形成第一牺牲材料层222，例如光刻胶材料；并且可以在载体第二表面208’上和在第二微电子器件附接焊盘212’上形成第二牺牲材料层222’，例如光刻胶材料。可以通过任何本领域公知技术来形成第一牺牲材料层222和第二牺牲材料层222’，所述本领域公知技术包括但不限于：旋涂、干法光学膜层叠(dry photofilm lamination)和化学气相沉积。
如图6所示，可以穿过第一牺牲材料层222来形成开口部224以暴露第一微电子器件附接焊盘212和载体第一表面208的一部分。可以同时穿过第二牺牲材料层222’来形成开口部224’以暴露第二微电子器件附接焊盘212’和部分载体第二表面208’。可以通过任何本领域公知技术来形成第一牺牲材料层开口部224和第二牺牲材料层开口部224’，所述本领域公知技术包括但不限于：光刻工艺和湿法或干法蚀刻。
如图7所示，可以在第一牺牲材料层222和第二牺牲材料层222’上形成层叠封装（PoP）焊盘。图7示出了形成在第一牺牲材料层222上的第一层叠封装焊盘228a和第二层叠封装焊盘228b，以及形成在第二牺牲材料层222’上的第三层叠封装焊盘228a’和第四层叠封装焊盘228b’。层叠封装焊盘（例如，元件228a、228b、228a’和228b’）可以是层状金属结构，例如，金、镍和铜的层，其可以通过本领域公知的任何技术（包括但不限于镀覆）来构图。如本领域技术人员应当理解的，层叠封装焊盘可以用来形成在用于进行堆叠（例如，被称为3D堆叠）的z方向上的微电子器件封装之间的连接，而不需要穿硅过孔。
如图8所示，第一微电子器件242可以通过具有高CTE材料层244的其背部表面250附接到第一牺牲材料层开口部224内的载体第一表面208。第一微电子器件242在其有源表面248上具有至少一个接触连接盘（示为元件246a和246b）。第二微电子器件242’可以通过具有高CTE材料层244’的背部表面250’附接到第二牺牲材料层开口部224’内的载体第二表面208’。第二微电子器件242’可以在其有源表面248’上具有至少一个接触连接盘（示为元件246a’和246b’）。第一微电子器件242和第二微电子器件242’可以是任意期望的器件，包括但不限于：微处理器（单核或多核）、存储器器件、芯片组、图形器件、专用集成电路等。高CTE材料层244和244’可以是任何适当的材料，包括但不限于管芯背面膜材料。
如图9所示，可以在第一微电子器件242、第一牺牲材料层开口部224、第一层叠封装焊盘228a和第二层叠封装焊盘228b上形成第一封装层252。可以在第二微电子器件242’、第二牺牲材料层开口部224’、第三层叠封装焊盘228a’和第四层叠封装焊盘228b’上同时形成第二封装层252’。在一个实施例中，第一封装层252和第二封装层252’可以包括硅石填充环氧树脂。
如图10所示，可以在第一封装层252上形成第一内建层262。第一内建层262可以包括具有导电迹线的多个电介质层，所述导电迹线邻近各个电介质层而形成，其中，导电过孔穿过各个电介质层而延伸以连接不同的层上的导电迹线。参考图10，第一内建层262可以包括至少一个第一层导电迹线272，其中第一内建电介质层274邻近第一层导电迹线272和第一封装层252而形成。至少一个迹线-到-器件导电过孔276可以穿过第一内建电介质层274而延伸以将至少一个第一层导电迹线272连接到至少一个微电子器件接触连接盘（例如，元件246a和246b）。至少一个迹线-到-焊盘导电过孔278可以穿过第一内建电介质层274而延伸以将至少一个第一层导电迹线272连接到至少一个层叠封装焊盘（例如，元件228a和228b）。至少一个第二层导电迹线282可以邻近第一内建电介质层274而形成，并且第二内建电介质层284可以邻近第二层导电迹线282和第一内建电介质层274而形成。至少一个迹线-到-迹线导电过孔286可以穿过第一内建电介质层274而延伸以将至少一个第一层导电迹线272连接到至少一个第二层导电迹线282。可以在第二内建电介质层284上形成至少一个第三层导电迹线292，并且至少一个迹线-到-迹线导电过孔286可以穿过第二内建电介质层284而延伸以将至少一个第二层导电迹线282连接到至少一个第三层导电迹线292。可以在第二内建电介质层284上对阻焊材料294进行构图，并且第三层导电迹线292具有至少一个开口部296，该开口部296暴露第三层导电迹线292的至少一部分。应当理解，可以穿过阻焊材料开口部296在第三层导电迹线292上形成互连结构（未示出），例如焊球。
进一步如图10所示，可以在第二封装层252’上形成第二内建层262’。第二内建层262’可以包括具有导电迹线的多个电介质层，所述导电迹线形成在各个电介质层上，其中，导电过孔穿过各个电介质层而延伸以连接不同的层上的导电迹线。参考图10，第二内建层262'可以包括至少一个第一层导电迹线272’，其中第一内建电介质层274’邻近第一层导电迹线272’和第一封装层252’而形成。至少一个迹线-到-器件导电过孔276’可以穿过第一内建电介质层274’而延伸以将至少一个第一层导电迹线272’连接到至少一个微电子器件接触连接盘（例如，元件246a’和246b’）。至少一个迹线-到-焊盘导电过孔278’可以穿过第一内建电介质层274’而延伸以将至少一个第一层导电迹线272’连接到至少一个层叠封装焊盘（例如，元件228a'和228b'）。至少一个第二层导电迹线282’可以邻近第一内建电介质层274’而形成，并且第二内建电介质层284’可以邻近第二层导电迹线282’和第一内建电介质层274’而形成。至少一个迹线-到-迹线导电过孔286’可以穿过第一内建电介质层274’而延伸以将至少一个第一层导电迹线272’连接到至少一个第二层导电迹线282’。可以在第二内建电介质层284’上形成至少一个第三层导电迹线292’，并且至少一个迹线-到-迹线导电过孔286’可以穿过第二内建电介质层284’而延伸以将至少一个第二层导电迹线282’连接到至少一个第三层导电迹线292’。可以在第二内建电介质层284’上对阻焊材料294’进行构图，并且第三层导电迹线292’具有至少一个开口部296’，该开口部296’暴露第三层导电迹线292’的至少一部分。应当理解，可以穿过阻焊材料开口部296’在第三层导电迹线292’上形成互连结构（未示出），例如焊球。
导电迹线（例如，元件272、272’、282、282’、292和292’）可以是任何适当的导电材料，该导电材料包括但不限于：铜、铝、银、金以及它们的合金，并且导电迹线可以由本领域中的任何公知技术来制造，这些公知技术包括但不限于光刻和镀覆。导电过孔（例如，元件276、276’、278、278’、286和286’）可以是任何适当的导电材料，该导电材料包括但不限于：铜、铝、银、金以及它们的合金，并且可以通过本领域中的任何公知技术来制造导电过孔，这些公知技术包括但不限于：激光钻孔、离子钻孔、光刻、镀覆和沉积。
应当理解，附加的电介质层、导电过孔和导电迹线可以是内建的以形成期望数目的内建层。
如本领域所公知的那样，可以用分板工艺（depaneling process）将由此在载体第一表面208上和在载体第二表面208’上所形成的结构彼此分离开。图11示出了在进行分板之后在载体第一表面208上所形成的结构。如图12所示，可以去除在进行分板之后从载体200剩余的铜层202，例如通过蚀刻工艺来去除。如图13所示，如本领域技术人员应当理解的那样，可以去除第一牺牲材料层222（例如通过等离子体灰化、喷砂或溶剂剥离），从而形成微电子器件封装290。因此，图3-13的过程形成了翘曲控制结构295，该翘曲控制结构至少包括高CTE材料层244和第一高弹性模量材料层216。
如本领域技术人员应当理解的那样，可以执行附加的处理步骤，包括但不限于：切割（singulation）、堆叠和封装。
图14-25示出了形成嵌入式无焊内建层无芯（BBUL-C）微电子封装的过程的另一实施例的截面图。如图14所示，可以提供载体，例如图3的载体200，并且在该载体上可以形成至少一个支撑体（stand-off）。如图所示，可以在载体第一表面208上形成第一微电子器件附接焊盘312，并且可以在载体第二表面208’上形成第二微电子器件附接焊盘312’。进一步如图14所示，第一微电子器件附接焊盘312可以是邻接载体第一表面208的第一保护层314（例如镍层）和邻接第一保护层314的第一高弹性模量材料层316（例如铜层）的层叠结构，并且第二微电子器件附接焊盘312’也可以是邻接载体第二表面208’的第二保护层314’（例如镍层）和邻接第二保护层314’的第二高弹性模量材料层316’（例如铜层）的层叠结构。
如图15所示，可以在载体第一表面208上和在载体第二表面208’上形成层叠封装（PoP）焊盘。图15示出了形成在载体第一表面208上的第一层叠封装焊盘328a和第二层叠封装焊盘328b，以及形成在载体第二表面208’上的第三层叠封装焊盘328a’和第四层叠封装焊盘328b’。层叠封装焊盘（例如，元件328a、328b、328a’和328b’）可以是层状金属结构，例如，金、镍和铜的层，层状金属结构可以通过本领域中公知的任何技术（包括但不限于镀覆）来构图。
如图16所示，第一微电子器件342可以通过采用高CTE材料344的其背部表面350而附接到第一微电子器件附接焊盘312。第一微电子器件342可以在其有源表面348上具有至少一个接触连接盘（示为元件346a和346b）。第二微电子器件342’可以通过采用高CTE材料344’的背部表面350’而附接到第二微电子器件附接焊盘312’。第二微电子器件342’可以在其有源表面348’上具有至少一个接触连接盘（示为元件346a’和346b’）。第一微电子器件342和第二微电子器件342’可以是任意期望的器件，包括但不限于：微处理器（单核或多核）、存储器器件、芯片组、图形器件、专用集成电路等。高CTE材料344和344’可以是任何适当的材料，包括但不限于管芯背面材料。
如图17所示，可以在第一微电子器件342、载体第一表面208、第一层叠封装焊盘328a和第二层叠封装焊盘328b上形成第一封装层352。可以同时在第二微电子器件342’、载体第二表面208’、第三层叠封装焊盘328a’和第四层叠封装焊盘328b’上形成第二封装层352’。在一个实施例中，第一封装层352和第二封装层352’可以包括硅石填充环氧树脂。
如图18所示，可以在第一封装层352上形成第一内建层362。第一内建层362可以包括具有导电迹线的多个电介质层，所述导电迹线邻近各个电介质层而形成，其中，导电过孔穿过各个电介质层而延伸以连接不同的层上的导电迹线。参考图18，第一内建层362可以包括至少一个第一层导电迹线372，其中，第一内建电介质层374邻近第一层导电迹线372和第一封装层352而形成。至少一个迹线-到-器件导电过孔376可以穿过第一内建电介质层374而延伸以将至少一个第一层导电迹线372连接到至少一个微电子器件接触连接盘（例如，元件346a和346b）。至少一个迹线-到-焊盘导电过孔378可以穿过第一内建电介质层374而延伸以将至少一个第一层导电迹线372连接到至少一个层叠封装焊盘（例如，元件328a和328b）。至少一个第二层导电迹线382可以邻近第一内建电介质层374而形成，并且第二内建电介质层384可以邻近第二层导电迹线382和第一内建电介质层374而形成。至少一个迹线-到-迹线导电过孔386可以穿过第一内建电介质层374而延伸以将至少一个第一层导电迹线372连接到第二层导电迹线382。可以在第二内建电介质层384上形成至少一个第三层导电迹线392，并且至少一个迹线-到-迹线导电过孔386可以穿过第二内建电介质层384而延伸以将至少一个第二层导电迹线382连接到至少一个第三层导电迹线392。可以在第二内建电介质层384上对阻焊材料394进行构图，并且第三层导电迹线392具有至少一个开口部396，该开口部暴露第三层导电迹线392的至少一部分。应当理解，可以穿过阻焊材料开口部396在第三层导电迹线392上形成互连结构（未示出），例如焊球。
进一步如图18所示，可以在第二封装层352’上形成第二内建层362’。第二内建层362’可以包括具有导电迹线的多个电介质层，该导电迹线邻近各个电介质层而形成，其中，导电过孔穿过各个电介质层而延伸以连接不同的层上的导电迹线。参考图18，第二内建层362’可以包括至少一个第一层导电迹线372’，其中第一内建电介质层374’邻近第一层导电迹线372’和第二封装层352’而形成。至少一个迹线-到-器件导电过孔376’可以穿过第一内建电介质层374’而延伸以将至少一个第一层导电迹线372’连接到至少一个微电子器件接触连接盘（例如，元件346a’和346b’）。至少一个迹线-到-焊盘导电过孔378’可以穿过第一内建电介质层374’而延伸以将至少一个第一层导电迹线372’连接到至少一个层叠封装焊盘（例如，元件328a'和328b'）。至少一个第二层导电迹线382’可以邻近第一内建电介质层374’而形成，并且第二内建电介质层384’可以邻近第二层导电迹线382’和第一内建电介质层374’而形成。至少一个迹线-到-迹线导电过孔386’可以穿过第一内建电介质层374’而延伸以将至少一个第一层导电迹线372’连接到第二层导电迹线382’。可以在第二内建电介质层384’上形成至少一个第三层导电迹线392’，并且至少一个迹线-到-迹线导电过孔386’可以穿过第二内建电介质层384’而延伸以将至少一个第二层导电迹线382’连接到至少一个第三层导电迹线392’。可以在第二内建电介质层384’上对阻焊材料394’进行构图，并且第三层导电迹线392’具有至少一个开口部396’，所述开口部暴露第三层导电迹线392’的至少一部分。应当理解，可以穿过阻焊材料开口部396’在第三层导电迹线392’上形成互连结构（未示出），例如焊球。
导电迹线（例如，元件372、372’、382、382’、392和392’）可以是任何适当的导电材料，包括但不限于：铜、铝、银、金以及它们的合金，并且导电迹线可以由本领域中的任何公知技术来制造，这些公知技术包括但不限于光刻和镀覆。导电过孔（例如，元件376、376’、378、378’、386和386’）可以是任何适当的导电材料，包括但不限于：铜、铝、银、金以及它们的合金，并且可以通过本领域中的任何公知技术来制造导电过孔，这些公知技术包括但不限于：激光钻孔、离子钻孔、光刻、镀覆和沉积。
应当理解，附加的电介质层、导电过孔和导电迹线可以是内建的以形成期望数目的内建层。
如本领域所公知的那样，可以用分板工艺将由此在载体第一表面208上和在载体第二表面208’上所形成的结构彼此分离开。图19示出了在进行分板之后在载体第一表面208上所形成的结构。如图20所示，可以去除在进行分板之后从载体200剩余的铜层202，例如通过蚀刻工艺来去除，以形成微电子器件封装390。因此，图14-20的过程形成了翘曲控制结构395，该翘曲控制结构至少包括高CTE材料层344和高弹性模量材料层316。
如本领域技术人员应当理解的那样，可以执行附加的处理步骤，包括但不限于切割、堆叠和封装。
应当理解，本说明书的主题不必限于图1-20中所示的具体应用。本主题可以应用到可能考虑翘曲的、包括其它无芯和薄芯封装的其它微电子器件封装应用。而且，可以将本领域中公知的其它翘曲减小技术（包括但不限于玻璃布层叠、模制等）与本说明书的主题相结合。此外，如本领域技术人员应当理解的那样，本说明书的主题可以是较大的无焊内建封装的一部分，其可以包括多个堆叠的微电子管芯，其可以以晶片级或任意数目的适当的变型来形成。更进一步，本主题也可以用于微电子器件制造领域之外的任何适当的应用。
已经具体描述了本发明的实施例，应当理解由所附权利要求限定的本发明并不受上述说明中所列举的特定细节的限制，因为在不脱离本发明精神和范围的情况下，可以对本发明作出许多明显的变化。

Claims (13)

1.一种微电子封装，包括：
微电子器件，其具有有源表面、相对的背部表面和至少一个侧面；
邻近所述微电子器件背部表面的翘曲控制结构，其中，所述翘曲控制结构包括高热膨胀系数材料层和高弹性模量材料层；
邻近所述微电子器件的有源表面的至少一部分和至少一个微电子器件侧面的至少一部分而设置的封装材料，其中所述封装材料包括靠近所述微电子器件的有源表面的第一表面以及与所述封装材料的第一表面相对的第二表面；以及
所述封装材料的第二表面中或上的层叠封装焊盘。
2.如权利要求1所述的微电子封装，其中，所述高热膨胀系数材料层包括热膨胀系数大于25ppm/℃的材料。
3.如权利要求1所述微电子封装，其中，所述高热膨胀系数材料层包括填充环氧树脂材料层。
4.如权利要求1所述的微电子封装，其中，所述高弹性模量材料层包括模量大于50GPa的材料层。
5.如权利要求1所述的微电子封装，其中，所述高弹性模量材料包括金属层。
6.如权利要求1所述的微电子封装，进一步包括：在所述封装材料的第一表面上所形成的内建层。
7.一种微电子封装，包括：
微电子器件，其具有有源表面、相对的背部表面和至少一个侧面；
邻近所述微电子器件背部表面的翘曲控制结构，其中，所述翘曲控制结构包括高热膨胀系数材料层和高弹性模量材料层，其中所述高热膨胀系数材料层的热膨胀系数大于25ppm/℃，并且所述高弹性模量材料层的弹性模量大于50GPa；
邻近所述微电子器件的有源表面的至少一部分和至少一个微电子器件侧面的至少一部分而设置的封装材料，其中所述封装材料包括靠近所述微电子器件的有源表面的第一表面以及与所述封装材料的第一表面相对的第二表面；以及
所述封装材料的第二表面中或上的层叠封装焊盘。
8.一种制造微电子封装的方法，包括：
提供载体；
在所述载体上形成微电子器件附接焊盘，其中，所述微电子器件附接焊盘包括高弹性模量材料层；
附接微电子器件到所述微电子器件附接焊盘，所述微电子器件具有有源表面、相对的背部表面和至少一个侧面，其中，附接所述微电子器件包括：在所述微电子器件的背部表面和所述微电子器件的附接焊盘之间设置高热膨胀系数材料层；
邻近所述微电子器件的有源表面的至少一部分和至少一个微电子器件侧面的至少一个部分来设置封装材料，其中所述封装材料包括靠近所述微电子器件的有源表面的第一表面以及与所述封装材料的第一表面相对的第二表面，并且在所述封装材料的第二表面中或上形成层叠封装焊盘；以及
去除所述载体。
9.如权利要求8所述的方法，其中，在所述微电子器件的背部表面和所述微电子器件的附接焊盘之间设置高热膨胀系数材料层包括：在所述微电子器件的背部表面和所述微电子器件的附接焊盘之间设置热膨胀系数大于25ppm/℃的材料层。
10.如权利要求8所述的方法，其中，在所述微电子器件的背部表面和所述微电子器件的附接焊盘之间设置高热膨胀系数材料层包括：在所述微电子器件的背部表面和所述微电子器件的附接焊盘之间设置填充环氧树脂材料层。
11.如权利要求8所述的方法，其中，在所述载体上形成微电子器件附接焊盘包括：在所述载体上形成微电子器件附接焊盘，其中，所述微电子器件附接焊盘包括模量大于50GPa的高弹性模量材料层。
12.如权利要求8所述的方法，其中，设置所述封装材料包括：邻近所述微电子器件的有源表面的至少一部分和至少一个微电子器件侧面的至少一个部分设置填充环氧树脂材料。
13.如权利要求8所述的方法，进一步包括：在封装材料的第一表面上形成内建层。
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