TW201222827A - Memory cell block, manufacturing method therefor, memory device, and method for driving a memory device - Google Patents

Memory cell block, manufacturing method therefor, memory device, and method for driving a memory device Download PDF

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Publication number
TW201222827A
TW201222827A TW100132261A TW100132261A TW201222827A TW 201222827 A TW201222827 A TW 201222827A TW 100132261 A TW100132261 A TW 100132261A TW 100132261 A TW100132261 A TW 100132261A TW 201222827 A TW201222827 A TW 201222827A
Authority
TW
Taiwan
Prior art keywords
layer
insulating layer
gate
memory
gate insulating
Prior art date
Application number
TW100132261A
Other languages
English (en)
Chinese (zh)
Inventor
Tatsuya Shimoda
Eisuke Tokumitsu
Takaaki Miyasako
Nguyen Quoc Trinh Bui
Original Assignee
Japan Science & Tech Agency
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Science & Tech Agency filed Critical Japan Science & Tech Agency
Publication of TW201222827A publication Critical patent/TW201222827A/zh

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/223Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B51/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/10Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B51/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
TW100132261A 2010-09-10 2011-09-07 Memory cell block, manufacturing method therefor, memory device, and method for driving a memory device TW201222827A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010203783 2010-09-10

Publications (1)

Publication Number Publication Date
TW201222827A true TW201222827A (en) 2012-06-01

Family

ID=45810704

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100132261A TW201222827A (en) 2010-09-10 2011-09-07 Memory cell block, manufacturing method therefor, memory device, and method for driving a memory device

Country Status (3)

Country Link
JP (1) JPWO2012033106A1 (ja)
TW (1) TW201222827A (ja)
WO (1) WO2012033106A1 (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9876067B2 (en) 2013-03-22 2018-01-23 Japan Science And Technology Agency Dielectric layer and manufacturing method of dielectric layer, and solid-state electronic device and manufacturing method of solid-state electronic device
US11200950B2 (en) 2017-04-28 2021-12-14 Micron Technology, Inc. Programming enhancement in self-selecting memory
TWI754793B (zh) * 2018-02-09 2022-02-11 美商美光科技公司 用於記憶體裝置之摻雜劑調變蝕刻
US11404637B2 (en) 2018-02-09 2022-08-02 Micron Technology, Inc. Tapered cell profile and fabrication
US11545625B2 (en) 2018-02-09 2023-01-03 Micron Technology, Inc. Tapered memory cell profiles
US12048164B2 (en) * 2022-09-13 2024-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Memory array and operation method thereof
US12082513B2 (en) 2018-02-09 2024-09-03 Micron Technology, Inc. Memory cells with asymmetrical electrode interfaces

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2724150B2 (ja) * 1988-03-15 1998-03-09 株式会社東芝 不揮発性半導体メモリ装置
JP3704947B2 (ja) * 1998-04-15 2005-10-12 セイコーエプソン株式会社 電界効果トランジスタの製造方法
JP2000340759A (ja) * 1999-05-31 2000-12-08 Sony Corp 不揮発性半導体メモリおよびその駆動方法
JP2007157982A (ja) * 2005-12-05 2007-06-21 Seiko Epson Corp トランジスタ型強誘電体メモリおよびその製造方法
WO2010097862A1 (ja) * 2009-02-24 2010-09-02 パナソニック株式会社 半導体メモリセル及びその製造方法並びに半導体記憶装置
JP2010267704A (ja) * 2009-05-13 2010-11-25 Panasonic Corp 半導体メモリセルおよびその製造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9876067B2 (en) 2013-03-22 2018-01-23 Japan Science And Technology Agency Dielectric layer and manufacturing method of dielectric layer, and solid-state electronic device and manufacturing method of solid-state electronic device
TWI621142B (zh) * 2013-03-22 2018-04-11 Japan Science & Tech Agency Method for manufacturing dielectric layer and dielectric layer, and method for manufacturing solid state electronic device and solid state electronic device
US11200950B2 (en) 2017-04-28 2021-12-14 Micron Technology, Inc. Programming enhancement in self-selecting memory
US11735261B2 (en) 2017-04-28 2023-08-22 Micron Technology, Inc. Programming enhancement in self-selecting memory
TWI754793B (zh) * 2018-02-09 2022-02-11 美商美光科技公司 用於記憶體裝置之摻雜劑調變蝕刻
US11404637B2 (en) 2018-02-09 2022-08-02 Micron Technology, Inc. Tapered cell profile and fabrication
US11545625B2 (en) 2018-02-09 2023-01-03 Micron Technology, Inc. Tapered memory cell profiles
US11800816B2 (en) 2018-02-09 2023-10-24 Micron Technology, Inc. Dopant-modulated etching for memory devices
US12082513B2 (en) 2018-02-09 2024-09-03 Micron Technology, Inc. Memory cells with asymmetrical electrode interfaces
US12048164B2 (en) * 2022-09-13 2024-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Memory array and operation method thereof

Also Published As

Publication number Publication date
WO2012033106A1 (ja) 2012-03-15
JPWO2012033106A1 (ja) 2014-01-20

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