TW201222827A - Memory cell block, manufacturing method therefor, memory device, and method for driving a memory device - Google Patents

Abstract

This memory cell block is provided with a plurality of memory cells connected in series, each memory cell comprising a solid-state electronic element in which the following are connected in parallel: an information-storage transistor (TR1) that has a first gate-insulating layer comprising a ferroelectric layer; and an information-reading/writing transistor (TR2) that has a second gate-insulating layer. First channel regions and second channel regions comprise conductor layers or semiconductor layers formed in the same step. Each two adjacent memory cells are connected by a connection layer contiguous with the first channel regions and the second channel regions. When this memory cell block is used as a NAND memory device, the "write disturb problem" and "read disturb problem" are eliminated. Also, it is possible to form the first channel regions, the second channel regions, and the connection layers in one step. Furthermore, it is possible to reduce the contact resistance between the first and second channel regions and the connection layers.

Description

201222827 VI. Description of the Invention: [Technical Field] The present invention relates to a memory cell block and a method of manufacturing the same, a memory device (m e m 〇 r y d e v i c e ), and a method of driving a memory device. [Prior Art] A solid state electronic device using a ferroelectric material (for example, Patent Document 1) has been known as a gate insulating layer. Fig. 41 is a view for explaining a conventional solid-state electronic component 9 〇 。. Fig. 4 2 is a view for explaining a switching operation in the conventional solid-state electronic component 9 〇 。. Fig. 42(a) is a diagram showing an ON state. Fig. 42(b) is a diagram showing an OFF state. The conventional solid state electronic component 900 includes a source electrode 950 and a drain electrode 960 as shown in FIG. 41; a channel layer between the source electrode 950 and the ytterbium electrode 960 (channei) A gate electrode 920 that controls the conduction state of the channel layer 940; a gate insulating layer 930 formed of a ferroelectric material formed between the gate electrode 92 0 and the channel layer 940. Further, reference numeral 9 1 0 in Fig. 41 denotes an insulating substrate. In the conventional solid-state electronic component 900, when the positive potential of the gate electrode 920 is given, as shown in FIG. 42(a), a channel 100132261 1003447808-0 201222827 ^ (channel ) 94 0 a is formed in the channel layer 940. The current flows from the drain electrode 96 to the source electrode 95. On the other hand, when the Zener 35920 is given a zero or negative potential, as shown in Fig. 42 (b), the channel layer 94 is depleted and depleted lavpr q4f]h, %. > _ is ,, Λ ^ becomes a state in which current does not flow between > and the electrode 9 6 〇 and the source electrode 950. Further, in the conventional solid-state electronic component 9, the material constituting the insulating layer 930 is made of a ferroelectric material (for example, BLT ((Bi4x, U)() Ti3〇i2) or PZT (Pb (Zrx, Tn-dO3). The material constituting the channel layer 94 is made of an oxide conductive material (for example, indium tin oxide (IT): Indium Tin Oxide). Therefore, according to the conventional solid electronic component 9 〇〇, the gate insulating layer is formed. Since the material of 930 is made of a ferroelectric material, it can be switched at a high speed with a low driving voltage, and as a result, a large current can be controlled at a high speed with a low driving voltage. The solid-state electronic component 9 〇〇, because the material constituting the gate insulating layer 930 is made of a ferroelectric material, the gate insulating layer 9 3 〇 has a hysteresis property. Therefore, the gate insulating layer 9 3 0 can be utilized. The hysteresis characteristic 'writes information into the gate insulating layer 930 or reads information from the gate insulating layer 930, and can be used as a memory element using the conventional solid state electronic component 90 。. 3 is to illustrate the hysteresis characteristics of the gate insulating layer 930 Figure 4 4 shows the picture of the state when the information is not written to the gate of the gate. Figure 4 4 (a) shows that the information of [1] is written into the gate insulating layer 9 3 The appearance of 0, Fig. 4 4 (b) is a view showing that information of [0] is written to the gate insulating layer 930. Fig. 45 is a view showing how the information is read by the gate insulating layer 930. Fig. 4 5 (a) 100132261 1003447808-0 201222827 疋颂不II Bar edge layer 930 keeps the information of [丨], Figure 45(b) is not free, the bar edge layer 9 3 0 keeps [〇] In addition, in FIG. 4, the symbol k is a coercive voltage (c〇ercive vo1tage) indicating the free insulating layer 93〇. In the white metal component, the gate insulating layer 93 Since 〇 has hysteresis characteristics as shown in FIG. 43, as shown in FIG. 44, the gate electrode 92 can be applied by lowering the source electrode 95 〇 & and the 汲 electrode to the ground potential. The write voltage ±vw is written into the gate insulating layer 930 by the negative of [丨] or [〇] 。. That is, as shown in Fig. 44 (a), the gate electrode 920 can be insulated by a gate. + positive coercive voltage 曰(10)) Writing electric pot w), the information written ⑴ gate insulating layer 93. . Further, as shown in FIG. 44(b), the gate insulating layer voltage can be written to the gate insulating layer by a write information having a low negative coercive voltage (a Vc) in the gate electrode 930. (―Vw), [〇] and 'in the conventional solid state electronic component 9〇〇a ^ , because the gate insulating layer 930 has hysteresis characteristics as shown in Fig. 43, so as shown in Fig. 45 _ ◎ The positive oscillating voltage (+Vc) is low and is more than negative, and the voltage can be reduced by the voltage (VC) and the electrode 9 5 only in the state of being applied to the gate electrode 902. A predetermined voltage is applied between the 、 and the Fenlei poles 960, and the resources are read by the gate/and/off edge layer 930. That is, 'the information of the [1] is maintained in the gate insulating layer 930. * The pinch guards are shown in the figure, and the current is maintained in the state of the gate insulating layer 930 by the state in which the current flows from the xenon electrode 906 to the source electrode 9 When the information of [0] is as shown in Fig. 45(b), "fl," is a state in which the current does not flow from the electrode 906 to the source electrode 950, so < The mark is read by the gate insulating layer 9 3 0 ^ ^ 100132261 1003447808-0 201222827 [Patent Document 1] 曰 National Special Open 2 QQ 6~1 2 1 〇 2 9 [Invention] But The known solid-state electron element knows that even if 9 〇 is applied to the gate electrode 92, the true voltage (+V c ) can be obtained from Fig. 45 and is higher than the negative bridge voltage (~VC). The voltage, 诎 only technique - Γ ^, the information of the horse-made insulation layer 930 is also maintained, so the conventional solid-state electricity - picking m + ^ ^ 9 90 〇 can be used as a memory component. Therefore, it is conceivable to use the conventional ^ L _ u core son element 900 for a memory cell of a NAND type memory 奘 w & It is used in the NAND type but the following problems occur when the conventional solid-state electronic component 9 is used as the suffix unit. FIG. 46 and FIG. 47 show the conventional solid-state electronic component 9〇. The problem of the case of the case of the NAND-type memory device used in the NAND-type memory device is shown in Fig. 46 for the purpose of explaining the problem of writing new information into the solid-state electronic component 900. 47 is a view for explaining a problem in a case where information to be written into the solid-state electronic component 900 is read. In addition, in FIGS. 46 and 47, the symbol SW is a block selection transistor. In the case where the conventional solid-state electronic component 900 is used for the memory unit of the NAND-type memory device, for example, when it is desired to write new information to the selection unit M6, as shown in FIG. 46 The potential of the bit line (bit Hne) BL and the plate line (p 1 ate 1 ine) PL is lowered to the ground potential, and the potentials of the source (s 〇urce ) end and the drain (drai η) end of the unit Μ 6 are selected. Reduced to 100132261 1003447808-0 6 201222827 After potential, the [+ Vwl or "should -Vwl of x +, the Η㊉ Jiang Mei twenty - owe ^] given the option of writing potential between the electrodes and Μ6 the unit - Tony hearing people choose to write unit (iv). However, this is a non-selection unit. There are only i cutoffs (〇ff) in Μ5 and Μ7: The early choice...the green shape' cannot reduce the source terminal and potential of the selection unit M6 to the ground potential, so there is no Will destroy the non-selection list... The information maintained by J M7 cannot write new information to the selection list & μ question. This problem is referred to in this specification as [^ite disturb problem]. Further, in the case where the conventional solid-state electronic component 900 is used in a memory unit of a NAND-type memory device, for example, when it is desired to read information of a memory unit (hereinafter referred to as a selection unit) M6 held and selected, In the case where the unselected memory cells (hereinafter referred to as non-selected cells) M0 to M5 and M7 are both turned on (0N), the specification is applied between the bit line BL and the plate line. The electric dust 'is judged whether the information that is nested in the selection unit M6 is [1] or [0] by whether the current flows at the time. However, in this case, since the non-selected cells M0 to M5 and M7 are all turned ON, there is a process in the process [π information is written to all of the non-selected cells Μ0~Μ5, Μ7, destroying the non-selected cells. Μ 0 ~ Μ 5, Μ 7 The information kept by the problem. This problem is referred to as a "read disturb problem" in this specification. As described above, in the case where the conventional solid-state electronic component 900 is used in the memory unit of the nand type memory device, 'when the new information is to be written into the selection unit and the case where the information held by the selection unit is to be read, Any one of them has major problems like the above ([Write Interference Problem] and [Read Interference Problem]). 100132261 1003447808-0 201222827 In addition, this problem does not occur, ^ nnn 疋 will only occur in the memory of the use of the 皞 兀 兀 θ θ 〇〇 记忆 记忆 记忆 电子 电子 电子 电子 电子 电子 电子 电子Use the Ρ & layer to use the ferroelectric material [Ϊ! At use closed,, and aba margin questions. The memory of the U anger 'electronic component is all the same. Therefore, the present invention is for the purpose of providing the creation of the problem of the use/the above, and the time does not make the memory of the written memory device The body of a single gas - Du Duo ^ disturbance problem] and [read interference problem] is composed of solid and evil electronic components, the purpose of the memory is to provide a kind of ancient and 'no memory cell block The body of the body and the driving method of the memory device U body device [1], the memory of the present invention _ mouth early element block, its characteristics include. The information memory of the lower right member is used for 3., like m❹ Said Zhuo-Crystal: a first channel F with a first source and a first drain, and a first gate electrode that controls the first channel region, a guide m of the ki L· domain s F ^ , a first-instance insulating layer formed between the first gate electrode and the aforementioned one-way region; and the "me layer" constitutes a transistor: having a second source = The second control area for information read/write is to control the second channel area: the second channel area of the second?: end 'With the aforementioned second gate electrode and the former Chengdi...,, -柽 and the formation, the second gate isolating layer between the passage area, including ···························· And the second transistor is connected to the second source terminal at the first source terminal and the second source terminal, wherein the first 汲 terminal and the second 汲 terminal are connected to the first gate electrode and the second gate electrode a plurality of memory cells composed of solid-state electronic components connected in parallel in a state of being connected to another gate me, the plurality of memory cells being connected in series by the plurality of memory blocks 100132261 1003447808-0 8 201222827 The two-channel region is formed by the first channel region and the foregoing, and the two memory cells in the plurality of memory layers or the semiconductor layer structure Φ ^ ^ ^ - 5 Xuan two memory single 沭筮-, animal, sound F Α in the first channel area and the aforementioned brother-channel area, and with the m μ ^ ^ ψ> > m rn Λ>, region Connection formed by a conductor layer or a + conductor layer formed by the same process Therefore, the π-i° heart-shaped early-breaking block according to the present invention can be used for the memory of the Nand r% ^ χ ^ - r ^ 5 u body by using the L-body as early as 70 £ blocks. Unit, structure ('Do not make a [write interference problem] "state" L ° shell out interference problem] memory device. That is, 'in the case of the invention, the single U basket is 70 £ block In the UI of the memory cell area of the NAND type memory device, for example, when the new information is to be written in the selection unit Μ6, as shown in FIG. 5, FIG. 7, and FIG. 14, which will be described later, As shown in FIG. 16, FIG. 18 and FIG. 20, at least the second word line (w〇rd Hne) ffL2〇 to WL27 connected to the non-selected cells Μ〇 to Μ5 and Μ7 is applied with a turn-on state voltage (0N_state v〇itage). Von' and the number connected to the selection unit M6

The word line WL!6 applies a first write voltage (VW: Vw > Vcl) higher than the coercive voltage vcl of the first gate insulating layer and a coercive voltage of the first gate insulating layer.

Vcl is added with a negative voltage (a vcl) lower than the second write voltage ([-Vw] : 〇Vw] < -Vcl). Accordingly, since at least the second transistors TR2 in the non-selected cells M0 to M5 and M7 are turned on (ON), the selection unit M6 can be made to pass through the second transistor TR2 even if the first transistor TR1 is not used. Each of the second and second source terminals has the same ground potential as the potential of the bit line BL and the plate line PL. Therefore, the information held by the first transistor TR1 in the non-selection order 100132261 1003447808-0 201222827 element MO~M5, M7 can be destroyed, and new information can be written to the selection unit M6. As a result, the memory cell block of the present invention becomes a memory cell block which does not cause the [write disturb problem] to occur. Further, in this case, when new information is written in the selection unit Μ 6, any of the on-state voltage Von or the off-state voltage Voff is applied to the second word line WL26 connected to the selection unit Μ6. Also. On the other hand, in the case of the memory cell block of the memory device of the present invention, for example, it is intended to read the information held by the selection unit M6, as shown in FIG. 6, FIG. 8, FIG. As shown in FIG. 19, FIG. 19 and FIG. 21, the on-state voltage v〇n is applied to the second word lines WL20, 25 and 仏7 connected to the non-selection cells M (M15, M7), and the pair is connected to the selection unit M6. The second word line WL26 applies an off-state voltage Voff. 摅m μ ^ 隹乂 曰 + f + unit Μ〇 Μ Μ 5, 第二 7 of the second electric body TR 2 are both turned on (〇ν,,, When - all are cut off (QFn n ± 70 Μ 6 of the second transistor m, because any - strip Λ can read the information held in the selection unit ^. Thus, the sub-line is not connected to the complex _ φ Β Τ Ρ 1 XL· Non-selection unit Mniic: Biting on the younger day of the body TR1, so the crystal - also = breaking 7 and selecting any of the first electronic memory unit ^AA k in the unit M6 The message block of the present invention, the memory cell of the present invention, which does not cause the [readout interference problem] to occur, is in accordance with the memory cell block of the present invention. Due to the domain and the second channel layer structure, the conductor layer or semi-conductor formed by the plurality of two-dimensional processes is the first of the two memory cells Λ X memory cells which are continued from the 兮, body unit The channel region and the second 10 100132261 1003447308-0 201222827 track region 'and are connected with the connection layer formed by the same conductor region as the channel region, so that the first channel region and the second region can be formed by one process In the channel region, the contact resistance of the first channel region and the second channel region can be reduced. [2] In the memory cell block of the present invention, the domain and the second channel region and the foregoing connection layer are Preferably, the configuration is such that the carrier concentration can be increased, so that a large current can be driven at a low level. [3] In the memory cell block of the present invention, the electrode And the gate electrode layer of the second gate electrode, and the gate insulating layer of the framing layer and the second gate insulating layer, and the conductor layer are preferably formed of a liquid material. With this configuration, embossing can be used. ) Mo 1 di ng) Processing technology to manufacture memory cell blocks, to produce raw memory cells with less raw materials (raw mater ia 1) and energy production). M0D (Metal Organic Decomposition material, sol-minus) Sol-gel solution, liquid material, etc. [4] In the memory cell block of the present invention, a process of forming a conductor layer or a half of the gate insulating layer with the conductor layer or the semiconductor, that is, Short into and connected to the layer. And the carrier concentration dynamic voltage in the first channel region oxide conductive material region between the connection layer and the connection layer is controlled at a high speed to form the first gate into the first gate to eliminate the conductor layer or the semi-defective shape (embossing can be used) Far more than (manufacturing: block liquid material can be: metal organic decomposition), nanoparticle dispersion of the above gate electrode layer, the layer is not used vacuum 100132261 1003447808-0 201222827 vacuum process shape, 1 formed better. By using this composition, because of

u It is possible to manufacture a memory cell block without using a vacuum process, so that it is possible to manufacture a memory cell block superior to the above with a manufacturing energy of less than 4 U. [5], in the memory of the present invention, the gate electrode layer constituting the first electrode and the second gate electrode of the second gate electrode, and the first edge layer And the gate insulating layer of the second gate insulating layer and the conductor conductive layer are preferably made of an oxide material. The wire electrode layer and the gate insulating layer are formed by using a liquid material. And the conductor layer or semi-conducting ^Φ ^ Slip. Moreover, it can be regarded as a solid electronic component with high reliability (rel iabi 1 ty). [6] In the memory cell block of the present invention, the foregoing gate Preferably, the electrode layer and the gate, the insulating layer and the conductor layer or the _f body layer have a (four) perovski te structure. By forming the gate electrode layer and the gate insulating layer and the conductor layer or the semiconductor layer The same crystal structure (cryStalIine structure) can produce high-quality solid-state electronic components with few lattice defects. [7] In the memory cell block of the present invention, the second gate insulating layer is a ferroelectric layer in the same layer as the first gate insulating layer The first transistor and the second transistor may have a gate electrode layer constituting the first gate electrode and the second gate electrode on one surface of the solid substrate, and insulating the first gate The gate insulating layer of the layer and the second gate insulating layer and the conductor layer or the semiconductor layer constituting the aforementioned first channel region and the second channel region and the aforementioned connecting layer of 100132261 1003447808-0 12 201222827 are formed in this order. According to this configuration, a planar separation type s-resonance unit block (lower gate type: b〇11 om ga tety pe) can be formed on a solid substrate (refer to Embodiment 5 to be described later). [8] In the memory cell block of the present invention, the second gate insulating layer is composed of a ferroelectric layer in the same layer as the first gate insulating layer, and the first transistor and the second transistor may have: a surface of one of the substrates constituting the first channel region and the second channel region and the conductor layer or the semiconductor layer of the connection layer, and the first gate insulating layer and the aforementioned a gate insulating layer of the second gate insulating layer and a gate electrode layer constituting the first gate electrode and the second gate electrode are formed in this order. By using such a structure, a planar separation type can be formed on the solid substrate. The hex-body unit block (upper gate type: t 〇p ^ ^ etype ) (refer to the sixth embodiment described later). [9] In the memory cell block of the present invention, the first transistor It is preferable that the second transistors are arranged side by side in the channel width direction. The first transistor and the second transistor can be disposed in a space-efficient manner by such a configuration. [1] In the memory cell block of the present invention, the first transistor and the second transistor may have a first surface on a surface of the solid substrate that constitutes a first gate electrode a gate electrode layer, and the first gate insulating layer 'and a conductor layer or a semiconductor layer constituting the first channel region and the second channel region and the connecting layer and the second gate insulating layer 100132261 1003447808-0 201222827' The structure constituting the aforementioned second gate electrode. The idle-pole layer is formed in this order: it can be constituted by: the upper electrode of the solid substrate, the first-inter-insulating layer and the first-channel region constitute a second channel region, the first gate π transistor, And - and the second gate electrode - (see Embodiments 1, 3, and 4 to be described later). In the memory cell block of the present invention, in the memory cell block of the present invention, the body and the second transistor can be in the right-hand side, and the electro-crystal is formed on the solid substrate. a second gate electrode insulating layer constituting the surface of the second gate electrode, the second gate electrode of the π Ί: pole, and a conductor constituting the first gate and the gate and the connecting layer. The second channel region is formed by layering: the second or + conductor layer 'is insulated from the aforementioned first gate. The pole-interelectrode layer of the pole is formed in this order. , ^ Composition: on the solid substrate, from the first -n ray pole, the first gate insulation layer and the _ „ 闸 罘 及 及 及 弟 通 通 通 通 通 通 通 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由The first electric eclipse composed of the electric 曰曰 body's and the two 曰**, 巴* β », 巴, ^ and the first gate electrode is solidified by the layered Manba and the layer knife in this order. The energy can be divided into the following: (2) [11] in the memory unit block), &&., quote the first gate insulating layer from the paraelectric layer

Cparaelectric layer) constitutes a piece. According to the first, second, and fourth embodiments of the above-described composition, it is also possible to accurately correct 100132261 1003447808-0 14 201222827 in the above-mentioned abundance separation type u core and electronic component. Write and read information. [13] In the memory cell block of the present invention (described in the memory cell block 彳 φ of [11] or the above [10] is preferably configured.), the second gate insulating layer is described by With such a configuration, the ferroelectric layer can also be written and read by the stacked-separated memory of the above-described third embodiment. In the block...the block can be correctly carried out, in the memory unit block of the present invention (documentation, the record of any one of [10 [10] to [13]; the above-mentioned "body early zone" In the block), among the conductor layer or the abundance conductor 9, the first channel region is located one by one, the vicinity of the interface of the second gate, and the second channel region is located near the interface with the second electrode. In the memory cell block of the present invention (described in the memory cell block of any one of [10] to [13]), in the portion of the 'u ^ ^ channel region and the second channel region The thickness of the conductor layer or the semiconductor layer is determined to be as follows. When it is desired to read the cutoff information (off i nf0rmati0n) held in the predetermined two=two binary, the predetermined memory unit is used. In the other memory cells, at least the second channel region serves as a guide. On the other hand, in a predetermined memory cell, the entire conductor layer or the semiconductor layer constituting the first channel and the second channel are rendered non-conductive. In the memory cell block of the present invention, the second insulating layer is The first gate insulating layer is formed of a ferroelectric layer of the same layer, and the first channel region and the second channel region are located in a predetermined source region and a predetermined surface formed on a surface of a semiconductor substrate. Between the drain regions, 100132261 100344780S-0 201222827, the first gate insulating layer is formed to cover the first channel region, and the second gate insulating layer is formed to cover the second channel region, the first gate electrode The first gate insulating layer is formed to face the first channel region, and the second gate electrode is preferably opposed to the second channel region via the second gate insulating layer. In the configuration, a planar separation type solid-state electronic component (MFS (Metal-Ferroelectric-Semiconductor) type) can be formed on the surface of the semiconductor substrate (see Embodiment 7 described later). As a result, one millimeter can be used. The semiconductor process of the present invention manufactures a memory cell block at a low cost of manufacture. [1 5 ] In the memory cell block of the present invention (recorded In the memory cell block of the above [丨4], a parasitic buffer layer is formed between the first channel region and the second channel region, and between the first gate insulating layer and the second gate insulating layer ( Paraelectric buffer layer) is preferable. By adopting such a configuration, a planar separation type memory cell region can be formed on the surface of the semiconductor substrate.

(MFIS (Metal-Ferroelectric-Insulator-Semiconductor type)) (refer to Embodiment 8 described later). According to this, it is possible to suppress the "undesirable interdifius phenomenon" which is often generated between the semiconductor substrate (for example, S i ) and the ferroelectric layer (for example, p ZT) constituting the first gate insulating layer and the second gate insulating layer. ° [1 6 ], in the memory cell block of the present invention (described in the above [1 4 "! or [1 5 ] memory cell block), in the aforementioned paraelectric buffer layer, and the foregoing 1 6 100132261 1003447808-0 201222827 A float electrode is formed between the first gate insulating layer and the second gate insulating layer. By using such a configuration, a memory cell block (MFMIS (Metal-Ferroelectric-Metal-Insulator-Semicon due tor) can be formed on the surface of a semiconductor substrate. Type) (refer to Embodiment 9 described later). Accordingly, by arbitrarily adjusting the area of the capacitor composed of the gate insulating layer and the capacitor composed of the parallax buffer layer, the gate insulating layer and the residual electrode having a large amount of residual polarization can be alleviated. Charge mismatch between semiconductor substrates with a small amount (to be mismatched). [17] The memory device w feature of the present invention comprises: a bit line; a board, a line; a first word line; a second word line; and a plurality of series connection between the bit line and the board line a memory cell block of the memory unit; a memory cell array (memory ce 1丨array) of the plurality of memory cell blocks, wherein the memory cell is connected to the first word at the first gate electrode ◎ The memory line unit is connected in parallel in a state in which the second idle electrode is connected to the second word line, wherein the memory unit block includes the memory unit block of the present invention. Therefore, the memory device of the present invention becomes a war horse to use the solid-state electronic component of the present invention for the large capacity of the straight meta-memory unit of the NAND-type memory device without causing [write interference problem] and [readout interference In addition, in the memory device of the present invention, the transistor is a depleted 100132261 1003447808 17 201222827 type (depletion type) transistor (see the implementation of the following description) (2, 5 to IX) 'and an electric heating type of an enhancement type may be referred to (see Embodiment 4 to be described later). Any type of transistor is a sensible device that can read or write information correctly to the selection unit. Further, the first transistor may be a depleted transistor, and may be an enhanced transistor. Any type of transistor is a memory device that can read or write information correctly to the selection unit. [8 8] In the memory device of the present invention, the block is connected through at least one block to select a transistor. It is better for the board line.

The memory cell region of the bit line or the above-described memory cell block can be selected by the block selection signal selectiQn signai) which is given to the cell selection transistor. In the memory device of the present invention, the block includes the memory cell block of the present invention (described in the memory cell region of any of the above [7] to [9]: In the above-mentioned connection layer, it is preferable that a conductor layer for resistance reduction is formed in an upper layer or a lower layer of the connection layer at a position where the first word line or the second word line is overlapped. .

With such a configuration, it is possible to prevent a poor switching phenomenon (Undesirable switching phen〇raen〇n) from occurring in the portion of the connection layer located at a position intersecting the first meta-line or the L-shaped element line. [20] In the memory device of the present invention, the memory block includes the memory cell block of the present invention (described in the memory cell block of the two items "2 to 9"). Conductor layer or semiconducting layer of the foregoing connecting layer

1 S 100132261 1003447808-0 201222827 Conductor wire or phenomenon. Chemical. The conductor of the conductor monomolecular region [13] of the Zhan or half-domain conduction semiconductor, the structure or the second F sign is: the L element containing the term (the memory cell is a non-selective layer ratio constitutes the aforementioned The one-channel arduous area or the aforementioned second-channel area layer or the semiconductor layer is also thicker. By using this configuration, it is also possible to prevent the connection layer located at a position crossing the first character two-character line. Poorly produced. Switching and making the connection; the conductor layer or the semiconductor layer with low resistance in the case of the smear-free + human-free layer can be reported by using the embossing point. Make up the connection layer

The layer or the semiconductor layer is thicker than the layer constituting the -Fth Dankele channel & or the second channel region or semiconductor layer. [C] [21] In the memory device of the present invention, the memory block includes the memory cell block of the present invention (described in the above [10] to § the memory cell block of any of the above), and constitutes the aforementioned The conductor conductor layer of the connection layer is preferably thicker than the first channel region and the second channel region body layer or semiconductor layer. With such a configuration, the conductor layer or layer constituting the connection layer can be made low in resistance. In this case, the conductor layer or the semiconductor layer of the connection layer by using an embossing forming technique or the like may be thicker than the conductor layer or the semiconductor layer constituting the first channel region 〇 channel region. [2 2] The method of driving the memory device of the present invention, wherein the memory device of the present invention is used and the memory cell block of the memory cell block invention is described (described in the above [丨〇] ~ [ The memory device of any memory cell block of 丨3] is referred to as a selection unit for a predetermined memory, and is not selected among the memory cells of the cell block belonging to the same cell as the selection unit. The memory single selection unit) performs information writing 'where the second transistor in the non-selection unit is caused by applying at least a second state line connected to the 100132261 1003447808-0 19 201222827 unit to the on-state voltage Von Turning on (0N), and applying a second word line ground potential connected to the selection unit, applying a higher coercive voltage V c 1 than the first gate insulating layer to the first word line connected to the selection unit A write voltage (Vw: Vw > Vcl) and a second write voltage ([-Vw]: [-Vw] <- which is lower than a voltage (-Vcl) to which the aforementioned coercive voltage Vcl is added with a negative sign. Any one of Vcl) to write information about the selected unit Work. Therefore, according to the driving method of the memory device of the present invention, it is also known from the test examples described later that the information can be written to the selection unit at a high speed. [2 3] The method of manufacturing a memory cell block of the present invention, characterized in that a method of manufacturing a memory cell block for manufacturing a memory cell block including: a member for information memory having the following components a first transistor: a first channel region having a first source terminal and a first drain terminal, and a first gate electrode for controlling an on state of the first channel region, and a first gate electrode formed in the first gate electrode and the first a first gate insulating layer formed by a ferroelectric layer between the channel regions; a second transistor for information read/write having: a second source region having a second source terminal and a second drain terminal, and a second gate electrode for controlling an on state of the second channel region, and a second gate insulating layer formed between the second gate electrode and the second channel region, comprising: the first transistor and the foregoing The second transistor is connected to the second source terminal at the first source terminal, the first 汲 terminal is connected to the second 汲 terminal, and the first gate electrode and the second gate electrode are respectively In the state connected to another gate line, a plurality of memory units composed of solid electronic components connected in parallel, the plurality of memory sheets 100132261 1003447808-0 20 201222827 domain and the middle connection, so that the channel and the average electrode are insulated , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The connecting layer of the U-body early in the memory unit. [24] In the manufacturing method of the present invention, the emulsion conductive material is used in the method of manufacturing the L-form and the early-stage block, and the connecting layer is the channel a region and the second method for manufacturing a second body material; the 闸 ΛΑ η ^ α ^ 冓 is the first gate electrode and the gate electrode layer of the second gate ί I, disk; i#士乂, 丄... /, to form the gate insulating layer of the sluice insulation layer and the second sluice layer, and the conductor layer or the semiconductor layer is better. [26] Method for manufacturing memory cell block of the present invention

It is preferable to use a vacuum aluminum alloy to form a gate electrode layer, and the above-mentioned gate insulating layer is preferably a conductor layer or a semiconductor layer.

C

[2] In the method of manufacturing a memory cell block of the present invention, an oxide material is used to form a dummy electrode layer ′ constituting the first gate electrode and the second electrode, and the first gate insulating layer and the first portion are formed. The insulating layer of the double-edge layer is preferably the same as the conductor layer or the semiconductor layer. According to the method of manufacturing a memory cell block of the present invention, the memory cell block of the present invention superior in the above-described manner can be produced. [Embodiment] Hereinafter, a memory cell block of the present invention, a method of manufacturing the same, and a method of driving a memory device will be described based on the illustrated embodiments. 100132261 1003447808-0 201222827 Fig. 1 is a diagram for explaining the structure of the solid-state electronic components 100 to 100h used in the memory devices 2000 to 2000h according to the first to ninth embodiments. The solid state electronic component used in the present invention is a first transistor TR1 for information memory and a second transistor TR2 for information read/write, and is connected at the first source terminal and the second source terminal, the first The solid state in which the extreme and second turns are connected, and the first gate electrode and the second gate electrode are respectively connected to another gate line (the first word line or the second word line) element. In the solid-state electronic component used in the present invention, as shown in FIG. 1, the gate insulating layer (first gate insulating layer) of the first transistor TR1 is composed of a ferroelectric layer (embodiments 1 to 9), and the second The gate insulating layer (second gate insulating layer) of the crystal TR2 is composed of a paraelectric layer (embodiments 1, 2, and 4) or a ferroelectric layer (embodiment 3, 5 to 9), and the channel region is formed on the solid substrate. The conductor layer or the semiconductor layer (Embodiments 1 to 6) or a semiconductor substrate (embodiment 7 to 9) located between a predetermined source region on the surface of the semiconductor substrate and a predetermined drain region. Further, the isolation structure of the first transistor TR1 and the second transistor TR2 is constituted by a laminated separation type (embodiments 1 to 4) or a plane separation type (embodiments 5 to 9). The gate type in the stacked separation type is a gate type in which the first gate is extremely lower and the second gate is extremely upper (embodiment 1, 3, 4) or the first gate is upper and the second gate It is composed of a gate type (Embodiment 2) of the lower layer. Further, the gate type in the planar separation type is constituted by a lower gate type (implementation form 5) or an upper gate type (embodiment 6 to 9). The second transistor TR2 100132261 1003447808-0 22 201222827 is composed of a depleted type (embodiment 1 to 3, 5 to 9) or an enhanced type (implemented with a bear. " In addition, in the present invention, when the depletion type is not pressed, the deadline is The state (OFF state), the 闸v day ^ is applied to the gate electrode, and the ON state can be turned into a complete [depletion type], and it also includes a load state when a negative voltage is applied to the #T closed electrode, but the gate is applied. Electrode application 〇V pull π丄 does not become

In the full conduction state, when a positive voltage is applied to the gate electrode, the first + top is turned into a transistor of the [incomplete depletion type] which is in a completely conductive state. [Embodiment 1] Fig. 2 is a circuit diagram of a memory device 2 η η ^ 与 according to the first embodiment. Fig. 3 is a view for explaining the display of the 恃 G G 11 body device 20 〇 related to the singularity. Fig. 3(a) is a partial view of the memory device 200, and Fig. 3(b) is a cross-sectional view taken along line A1-A1 of Fig. 3(a). Fig. 3(c) is A2-A2 of Fig. 3(c) FIG. 3(d) is a cross-sectional view taken along line A3-A3 of FIG. 3(a). Fig. 4 is a view for explaining the display and execution of the deforming device 200. 4(a) is an enlarged cross-sectional view showing a portion of the symbol rw Is] of FIG. 3(b) (a solid-state electronic component 1A for use in the first embodiment), and FIG. 4(b) is a view showing A graph of the relationship between the coercive voltage Vci of a gate insulating layer 132 and the write voltage (+Vw, -Vw) of the body TR1, FIG. 4, the conduction state voltage of the transistor 2 of the transistor 2 〇n and truncation ^ are graphs showing the voltage of the m state. 2 shows: the second word line and the plate line PL

The memory device 2 related to the first embodiment is shown as a bit line BL; a plate line PL; a first word line WLi〇~wLj; WL2〇~WL27; a memory unit M〇~M7; A A - A

A memory cell block MBb MB3 (memory unit block related to the first embodiment) of a plurality of memory cells MO to M7 is connected in series between the bit 7L line BL 100132261 1003447808-0 23 201222827; A memory cell array (not shown) of memory cell blocks MB1 to MB3. Further, only a part of the memory device 200 related to the first embodiment is shown in Fig. 2 . As shown in FIGS. 2, 3(a) to 3(c) and 4(a), each of the memory cells M0 to M7 is composed of a solid electronic component 10 having a first transistor TR1 and a second transistor TR2. 0 composition. The first transistor TR 1 is a transistor for information memory, and has a first source terminal S1 and a first gate terminal D1 as shown in FIG. 3( a ) to FIG. 3 ( c ) and FIG. 4 ( a ). a channel region 142; a first gate electrode 1 2 2 that controls an on state of the first channel region 142; and a ferroelectric layer formed between the first gate electrode 12 2 and the first channel region 14 2 A gate insulation layer 1 3 2 . The write voltages Vw and -Vw of the first transistor TR1 are set to values satisfying the relationship of [_Vw < -Vcl < 0 < Vcl < Vw] as shown in Fig. 4 (b). Vcl and -Vcl are the head voltages of the first gate insulating layer. The second transistor TR2 is a transistor for information read/write, and has a second source terminal S2 and a second 汲 terminal as shown in FIGS. 3(a) to 3(c) and 4(a). a second channel region 1 44 of D2; a second gate electrode 1 6 4 that controls an on state of the second channel region 1 44; a parasitic region formed between the second gate electrode 164 and the second channel region 1 44 The second gate insulating layer 154 of the layer is formed. The second transistor TR2 is a depleted transistor, and the on-state voltage Von and the off-state voltage V 〇ff are set to satisfy 100132261 1003447808-0 24 as shown in FIG. 4(c). 201222827 [Vof f <Von = 0V] The value of the relationship. The first day of the body TR1 and the second transistor TR2 are as shown in Fig. 2 and Fig. 3(c) 'at the first source terminal S1 and the second source terminal are connected: first - no extreme m and second and extreme D2 is connected, and then the first: 122 and the second gate electrode 164 are respectively connected to the other gate line (the first electrode layer (first word line) 120, the second electrode layer (second word line) 16 〇\ is connected in parallel. j

The first honeycomb body TR1 and the second transistor TR2 are arranged side by side in the stacking direction as shown in Fig. 3 (b), Fig. 4, and Fig. 4 (a). C is a memory cell block (for example, MB1) related to the first embodiment. As shown in FIG. 2, at least one block selection transistor sw is connected to the bit line block to select the transistor sw as shown in FIG. 3(a) and FIG. 3(b) and FIG. 3(d) are composed of a third transistor TR3 having the following members: a third channel region 146; a third gate electrode 166 that controls the conduction state of the third channel region 146; A third gate insulating layer 156 (a layer of the second gate insulating layer 154 构成) composed of a paraelectric layer between the gate electrode 166 and the third channel region 146. The first channel region 142', the second channel region 144 and the third channel region 146 are formed by a conductor layer 140 formed by the same process, and a plurality of memory cells belonging to the same memory cell block (for example, MB1)~M7 The two adjacent memory cells (eg, M7 and M6) are as shown in FIGS. 3(a) and 3(b) by the first channel region 142 extending from the two memory cells and The second channel region 144 is connected by a connection layer formed by a conductor layer 140 formed by the same process as the channel regions 、, 144, and 100132^61 1003447808-0 25 201222827 belong to the same memory cell block (for example The block selects the electric crystal Zhao SW and the memory unit (memory unit M0) adjacent to the block selection transistor sw by the first channel region 142 and the second extending from the memory unit M0 The channel region 144 and the third channel region 146' in the block selection transistor sw are connected by a connection layer formed by a conductor layer 140 formed by the same channel region 142, U4, ι46. The solid state electronic component 1 used in the first embodiment is the first electromorphic problem TR1 and the second transistor TR2, as shown in Figs. 3(b) and 4(a): one of the solid substrates 11 On the surface, the first gate electrode layer 120 constituting the first gate electrode ι 22, and the first gate insulating layer 132 (13 〇), and the conductor layer 14 构成 constituting the first channel region 142 and the second channel region 144, and The gate insulating layer 1 54 (150') is a so-called stacked-separated type two:= sub-element having a structure in which the second gate electrode layer 160 constituting the second gate electrode 164 is formed in this order. 〜 电 In the solid-state electronic component 1 used in the first embodiment, the solid substrate 110 is, for example, an insulating substrate having a Si〇2 layer and a Ti-STO (SrTiO) layer interposed on the surface of the Si substrate. And the foot, 1 θ formation. ^ _ music] I pole layer 12 0 such as the use of Pt. Further, the ferroelectric material used for the first gate % edge layer 132 is, for example, PZT (Pb (Zrx, Th - ooo. Moreover, the conductor layer is made of an indium tin oxide (IT0) oxide conductor. Moreover, & For example, the edge layer 150 is made of, for example, Si〇2. Further, the first gate electrode layer 160 is made of A1. The information of the example is written and read in the memory device 2 of the first embodiment. 100132261 1003447808-0 26 201222827 The figure is for explaining the information writing operation in the reading. FIG. 6 is a diagram for explaining the memory device 20 related to the first embodiment. Intrusion action; Βπ S female material, PCT 1. Round 〇疋m from 5 children" factory 4 six... A related memory Junkou map. The information readout action in 2〇0 is displayed, The _-input of the information writers M0~M7 is as shown in Fig. 5. The connection is applied to the non-selection order and the on-state voltage V〇n is applied to the connection list _U〇~WL27, and the gate insulating layer is coercive. The first word line WL16 of the voltage 兀Μβ is applied more than the first and the first 第73 & V The first write voltage (Vw: Vw &gt; Vcl) of C1 is high. The voltage of the first and second λB voltages after the negative voltage is added to the voltage of the sakisaki V. Vcl is appended with a minus sign, and accordingly, because of the non-selection unit Mn ([-Vw]: [-VW] <-VC1) (10), even if the second transistor TR2 in the second M7 is not used, it is turned on. The body TR2 causes the selection unit M: the transistor TR1' to pass through the second transistor and the bit line BL and the plate line ρΐ~汲 and the second source terminal to destroy the ground potential of the non-selection unit: the same potential. Therefore, the information of the first 曰 曰 τ τ ι τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ τ The unit Μ6 is selected. As a result, the solid state laser-W device 1 〇〇 used in the first embodiment (and the 5 mnemonic &amp; 20 20 related to the first embodiment) becomes not the same as the φ s s [Write interference problem] occurs in solid-state electronic components (and redundant device). And 'in the information read gentleman one by one' Figure 6 is not 'connected to non-selected singles M0~M5, M7 -Bao nrrn - sub 7&quot; lines WL2 〇 WL25, WU7 apply an on-state voltage Von, and an off-state voltage Voff is applied to the second word line ...6 connected to the selection unit M6. Accordingly, due to non-selection The second transistor TR2 in the unit Μου is turned on (0Ν), and the second unit 100132261 1003447808-0 27 201222827 in the selection unit Μ6 is turned OFF, so that the information held in the selection unit M6 can be read. In other words, if a predetermined voltage is applied between the bit line BL and the plate line PL, it is judged whether the information written in the selection unit M6 is [1] or [0] by whether or not the current flows at the time. The information held in the selection unit M6 can be read. Then, at this time, since any one of the second word lines WL2 〇 WL WL27 is not connected to the first transistor TR1, the first transistor TR1 of any one of the non-selected cells M0 M M5, M7 and the selection unit M6 is also Will not destroy the information maintained. As a result, the solid-state electronic component 1 (and the memory device 200 according to the first embodiment) used in the first embodiment is a solid-state electronic component (and a memory device) that does not cause ([Reading interference problem]). Fig. 7 is a view showing a driving waveform at the time of information writing in the memory device 2000 according to the first embodiment. Fig. 7(a) is a view showing a driving waveform for driving the second transistor TR 2 . Fig. 7(b) is a diagram showing the driving waveform of the transistor T R1 which is not used to drive the transistor. Fig. 8 is a view for explaining the driving of the information reading in the memory device 200 in the first embodiment. A waveform is displayed. Fig. 8(a) is a view showing a driving waveform for driving the second transistor TR2, and Fig. 8(b) is a view showing a driving waveform for driving the first transistor TR1. 8 (c) shows the drain current. In addition, in the following description, we will focus on the memory unit Μ 6 to explain the method of reading and writing information. Therefore, in Figure 7 and Figure 8 For the period of selecting the memory unit Μ6 (period 7), the shadow is removed and highlighted In the memory device 200 related to the first embodiment, the driving waveform 2 shown in FIG. 100132261 1003447808-0 28 201222827 7 can be used to write the information connected to the device. That is, as shown in FIG. (a) shows that in the whole period n # memory unit Μ0~Μ7, the second word line WL2〇~WL27 is used to apply the guide, and the sorrow voltage Von (for example, 0V). (b) ', in this state, the 斟, * 吐一字 pairs of the non-selected cells Μ0~Μ5, Μ7, the Ding depth WL·1 〇~flrw, the ground potential is applied to the imaginary m 1 , WLl7 ( For example ον), and

The coercive voltage v of the C-edge layer, the first-to-yuan line WL6, the first write voltage (VW: VW &gt; VC1) and the lower second write than the first gate absolute first gate Into the life-threatening / electric [Vcl after the negative sign of the voltage (-VC1) to connect π 韭 i i V Vw]: [_Vw] &lt; - Vcl). In addition, the first word line WL10~WLl5, the 矫甲巴, the layer of the pedestal voltage Vcl, which is connected to the non-selection unit M〇~ WLJ, are lower than the first gate 'B, The coercive voltage VC1 of the 彖 layer may be added with Luν / Γ ν Ί , and the voltage (VCL-Vcl) of the voltage (-Vcl) after the 彖 layer may be (v &lt; v &lt; Vci). It is also possible to apply the off-state voltage v ff to the flute 〜 and 'to the younger one connected to the selection unit M6. In the recording device 2 relating to the embodiment, by giving the driving waveform as described above to each of the first word % line and the second sub-member line, the non-selecting units M0 to M5, M7 are reduced. The H 冷 冷 H — 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电Each of the second drain and the first source terminal of 兀M6 is at the ground potential of the potential 彳@ RI ητ which is the same as the potential of the line BL and the plate line PL. Therefore, the assets held by the first transistor TR1 of the non-selective unit M0, ... will not be broken. Fl ' can write a new message to the selection unit M6. On the other hand, in the memory device 200 100132261 1003447808-0 201222827 related to the implementation of the taper .n ~, the readout of information can be performed using the drive waveform shown in FIG. That is, as shown in FIG. 8(a), the on-state voltage Von(OV) is applied to the second word lines WL2 to WL25, WL27 connected to the non-selected cells M0 to M5, M7, and the pair is connected to the selection unit M6. The second word line WL26 applies an off-state voltage Vo ff. Further, as shown in Fig. 8 (b), 0 V is applied to the first word lines W LI 0 to W LI 7 connected to the respective first memory cells Μ 0 to Μ 7. Further, the first word lines WLi0 to WLi7 connected to the respective first memory cells Μ0 to Μ7 are applied with a lower coercive voltage V c 1 than the first thyristor layer and the coercive voltage of the first thyristor insulating layer is applied. The voltage V ([-Vcl] &lt; V &lt; Vcl) of the voltage (-Vcl) after Vcl is added with a minus sign is also acceptable. In the memory device 20 according to the first embodiment, by applying the driving waveform as described above to each of the first word line and the second word line, an image is flowed between the bit line and the plate line. 8 (c) shows the bungee current. Therefore, by measuring the magnitude of the current and the magnitude of the polar current, it can be judged that the memory held by each memory is [1] or [〇], and the result can be maintained. Reading of information of each memory unit. [Embodiment 2] Fig. 9 is a view for explaining a memory device 200a according to the second embodiment. 9(a) is a plan view of the memory device 200a, FIG. 9(b) is a cross-sectional view taken along line A1-A1 of FIG. 9(a), and FIG. 9(c) is a cross-sectional view taken along line A2-A2 of FIG. 9(a). 9(d) is a cross-sectional view taken along line A3-A3 of Fig. 9(a). Fig. 10 is a view for explaining the memory device 200a according to the second embodiment. + Fig. 10(a) is an enlarged cross-section of the portion surrounded by the symbol R of Fig. 9(b) (solid-state electronic component 1 0 0 a used in the second embodiment) 100132261 1003447808-0 30 201222827, FIG. b) is a graph showing the relationship between the coercive voltage Vcl of the first gate insulating layer 132 and the write voltage (+Vw, _Vw) of the first germanium transistor tR1, and FIG. 10(c) is a view showing the second transistor TR2. A diagram of the on-state voltage and the off-state voltage Voff. The memory device 200a according to the second embodiment basically has a laminated separation type as in the case of the memory bank 2 according to the first embodiment, but the first transistor TR1 is formed on the second transistor TR2. This upper layer is different from the case of the memory device 2 of the first embodiment. That is, the memory device 20A related to the second embodiment has the first transistor TR1 and the second transistor TR2 as shown in Figs. 9(b), 9(c), and 1(a): On one of the surfaces of the solid substrate 11A, the second gate electrode layer 16B constituting the second gate electrode 164, and the second gate insulating layer ΐ54 (ιπ), and the second channel region 144 and the first channel are formed. The conductor layer 14A of the region 142 and the first gate insulating layer 13 2 2 (1 3 0 ) and the first gate electrode layer 120 constituting the first gate electrode 122 are formed in this order. As described above, in the memory device 2A according to the second embodiment, the memory device is mounted on the upper layer of the second transistor TR2 and the memory device is related to the first embodiment. Nn # & ^ The situation of the 脰农置200 is different, except that the first transistor TR1 for information memory and the second transistor TR2 for information read/write have respective first and second idle electrodes Since the structure connected to the other interrogation line is connected in parallel, the case of the memory device 200 according to the first embodiment does not cause [writing interference problem] and [readout]. Interference problem] The memory device that occurs. Further, the memory device 200a according to the second embodiment has a memory associated with the first embodiment in a point other than the point at which the first transistor 1001 is formed in the upper layer of the second transistor TR2. The configuration of the device 2000 is the same as that of the memory device 2000 according to the first embodiment. [Embodiment 3] FIG. 11 is related to the third embodiment. The circuit diagram of the memory device 2000. Fig. 12 is a view for explaining the memory device 2 0 0 b according to the third embodiment. Figure 1 2 (a) is a top view of the memory device 20 Ob, Figure 12 (b) is a cross-sectional view of A1-A1 of Figure 12 (a), and Figure 12 (c) is a cross-section of A2-A2 of Figure 12 (a) Fig. 12(d) is a cross-sectional view taken along line A3-A3 of Fig. 12(a). Fig. 13 is a view for explaining the memory device 200b according to the third embodiment. Figure 13 (a) is an enlarged cross-sectional view of a portion surrounded by the symbol R of Figure 12 (b) (solid-state electronic component 1 〇〇 b used in the third embodiment), and Figure 13 (b) shows the first gate insulation. A graph showing the relationship between the coercive voltage V c 1 of the layer 1 3 2 and the write voltage (+Vw, -Vw) of the first transistor TR1, and FIG. 13(c) shows the coercive voltage of the second gate insulating layer 150. A graph of the on-state voltage Von and the off-state voltage Voff of Vc2 and the second electro-crystal t body TR2. The memory device 200b according to the third embodiment basically has a configuration similar to that of the memory device 200 according to the first embodiment, but as shown in Fig. 11 and Fig. 13 (c), the second The gate insulating layer 1 5 4 (150) is composed of a ferroelectric layer, which is different from the case of the memory device 200 according to the first embodiment. In this case, the layer thickness of the second gate insulating layer 1 5 4 (150) is thinner than the layer thickness of the first gate insulating layer 1 3 2 (130). 100132261 1003447808-0 32 201222827 Thus, the memory device 2〇〇b related to the third embodiment is characterized in that the iron is formed of a ferroelectric layer in the first closed insulating layer 154 (15〇) and is separated from the implementation shape and the off-state. Memory device 2 0 愔 τ τ τ π π . . . 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电In the case of the connected device of the structure of the β-diameter 20 0, the memory + the bucket π 1 associated with the first embodiment is found, ^ is not caused by [writing interference problem] and [ Read - 0 Interference Calls] The memory device that occurred. "L. Further, since the information is written into the first channel region 142 and the gate insulating layer 132 becomes a ferroelectric layer between the first gate electrodes 1 22 which is written and clamped to obtain stable writing characteristics, The three-input and read-out are performed in the memory device 200b such as S, and the information is written. Fig. 14 is a view showing the third embodiment of the memory device according to the information writing operation in Fig. 20b and the third embodiment. Figure 15 is a diagram for explaining the relationship with 0. The information read operation in the % device 200 is displayed, that is, in the information §; λ g ± l _ yuan MO ~ M7 - 7 as shown in Figure 14, the pair is connected to the non-selected single-to-yuan line WT π and applying a conduction state voltage Von to the WLd, and a first word line WL!6 of the wall stub of the % release unit insulation layer is applied to the first ^V p 1 -λ- and the alignment The first write voltage (Vw: Vw &gt; Vcl) of the first gate 1 and the voltage of the first _ field voltage Vcl of the low (^Vcl) of the 々1 layer are added with a minus sign - the input data This is because of the non-selection pendulum. n _ Hair ([~Vw] ·· [-Vw] &lt;-Vcl ). The second transistor TR2 in Pingchenyuan Μ Μ~Μ7 is turned on to turn on the information of 100132261 1003447808-0 201222827, and new information can be written into the selection unit _', so even if the first transistor TR1 is used, the second transistor can pass through the second The electro-op crystal belly TR2 selects each of the second 汲 terminal and the second source terminal of the early το M6 to have the same ground potential as the potential of the bit line BL and the plate line PL. Therefore, the M6 of the first transistor w in the non-selected cells M0 to M5 and M7 is not destroyed. As a result, the solid-state electron 卩π彳n 1 〇〇b (and the memory device 200b according to the third embodiment) used in the third embodiment does not cause [writing, her y φ ^ - . . „ ^ θ Cognac problem] occurs in solid-state electrons (and memory devices). And 'when the machine is read out, as shown in Figure 1-5-wnwr, the pair is connected to the non-selection Μ0~Μ5, The second word line WL2〇~WL25 of Μ7. The first, s & v WL27 applies a conduction-like nuisance i Von, and the second word line WL26 connected to the 沦 沦 哉 V· 曲- 十 rb The cut-off sad voltage Voff. According to this, the second transistor m is turned on (10)), the selected cell M5, the M7 transistor TR2 is turned on (〇FF), so it can be as early as -M6 - 资m. Also gp, T - * ° ° in the selection unit M6 can also be caused by the application of the % pressure of the two 懕 蛘, plate line PL between the two lines of the bit line忐, whether the current flows at the time; MR recognizes that π*, water and Hungary are written to select the single π M6 as [i] or [〇], so the MR can be held in the selection unit. Μ6's poor news. Then, Because of any .^ to the WL2〇~WL27 Duo-transistor TR1, it is not possible for the non-selective units M0~M5, M7 and &amp; The result is that the solid-state electronic component 100 used in the third embodiment and the memory device 2Q in the third embodiment are solid-state electronic components that do not cause the [readout interference problem] to occur (and FIG. 16 is a diagram showing the driving waveforms of the memory 褒: 2_中100132261 1003447S08-0 34 201222827 in relation to the third embodiment. FIG. 16 (a) is a display for driving the first FIG. 16(b) is a diagram showing driving waveforms for driving the first transistor TR1. FIG. 17 is a diagram for explaining driving waveforms when reading information in the real 200b. Figure 17 (a) is a diagram showing a driving waveform for driving the second transistor TR2, and Figure 17 (b) is a diagram showing a driving waveform for driving the first transistor T R1, Figure 1 7 ( c ) is the display of the drain current. Ο In the memory device 2 〇 0 b related to the third embodiment, The information is written using the driving waveform shown in Fig. 16. That is, as shown in Fig. j 6 (a), the second word lines WLzO to WLs7 connected to all the memory cells m〇~M7 are selected. The conduction state voltage v〇n (for example, + V〇) is applied during the period of 1. The second gate insulating layer is composed of a ferroelectric layer, so that the memory effect (mem〇ry ef fect) is passed, and then (selection period 2~) 8) The second transistor tr2 is always turned ON. Moreover, as shown in Fig. _, 叭 D), in this state, the ground potential (e.g., 〇v) is added to the _th-&amp; connected to the non-selected cells Μ0~Μ5, Μ7, and 斟, 4一一And applying a first input voltage (Vw: Vw &gt; Vcl) and a comparison width higher than the first gate insulating layer to the first gate insulating layer M6, which is higher than the first gate insulating layer, and the weft voltage Vcl, which is connected to the first gate insulating layer M6. -

Vcl m ήα ^ ^ ^ The coercive voltage of the idle insulating layer is added after the voltage is negative (Vcl) low ([seven]: [-Vw] &lt;-Vcl) any one of the brothers - write voltage element (four) ~ M5, The first word line WLi〇~ni5 of M7 has a low coercive voltage Vcl connected to the non-selective single insulating layer and is applied to the first gate than the first gate

The voltage after Vcl is added with a minus sign (_Vcn ancient &amp; - the voltage of the coercive voltage H, V ci of the insulating layer ^ V ([-Vcl] &lt; V &lt; Vcl) 100132261 1003447808-0 35 201222827 is also possible. 'The off-state voltage Vo ff may be applied to the second word line WL 2 6 connected to the selection unit M6. In the memory device 20 0b according to the third embodiment, the above-mentioned driving waveform is given to each A word line and a second word line, the non-selection unit M0~M5 symbol is such that the second transistor TR2 in M7 is always turned ON during the non-F and K-selection periods, so Even if the first-only crystal TR1' is not used, the 筮~~汲 extreme of the selection unit M6 and the second source terminal can be made to be connected to the bit line BL and the plate line pl through the second transistor TR2. The same ground potential. Therefore, the information held by the first transistor TR1 of the non-selected cells M〇 to M5 is not destroyed, and new information can be written into the cell M6. On the other hand, in the embodiment The three related memory devices are placed in 2〇卟, and the driving waveform shown in Figure 17 can be used. Information reading. That is, if you look at the memory unit M6, first refer to Fig., ', Figure 17 (a), in the first period, the second word line WU6 is given the on state. Period

The second transistor TR2 is turned on (ON). Then, during the T-view period 2-6, the second a-line WU6 is only given a voltage of 0V', but the memory effect of the TR子年一电日日体 TR2, the second transistor TR2 is in the period 2~6 Also still turned on (10)). Then, in the period 7, the second word line U is given a state: the electric dust V ff, and the second transistor % in the period 7 is turned off (〇FF). Then, in the period 8, the second word line WL26 is given an on-state voltage, and in the period 8, the second transistor TR2 is turned on again (, υ 。). In the case of other memory cells Μ0~Μ5, Μ7, basically the same drive waveform is used. Therefore, for the memory cell Μ0, the heart ^mh shape period 1 is the selection period, 100132261 1003447803-0 201222827, so the νth word line WLd is from - 〇ff: and, for the memory unit: 7: The period after the removal of the off-state electric dust is given. Therefore, the period 8 is the period Η: state electric house..., and the second character line center in the first word 8 is given the intercept pressure V〇n. Moreover, as shown in the figure WLz7 is not smashed; - the first 3 a picture 1 7 (b) households; + the first treasure that gives the conduction state element M0~M7 _ ',, connected to the long-term phantom WL, # 垵 各 各 记忆 - memory single memory unit Μ 0 ~ Μ 7 of the first - plus 0 V. Further, the oscillating voltage Vc1 connected to each of the first layers is low and a voltage equal to the I 兀 line is applied to the voltage of the first thyristor. ^) The high voltage V([-Vcl]&lt;v&lt;Vcl) can also be driven in the memory device 20 0b which is related to the third embodiment of the control, μ, +, and μ B The waveform will be given to Jingtian, such as the word line and the second word line, so that the drain current shown in Fig. 17 (C) flows between the -, /, plate lines, so it can be measured The size of the immersed current is determined to be [1] or [0], and as a result, the information held in each memory unit can be read.电池 The memory device 20 0b according to the third embodiment has a memory device related to the first embodiment in a point other than the point where the second gate insulating layer 1 54 (150) is formed of a ferroelectric layer. In the case of the case of 200, it has the same effect as that of the memory device 2000 according to the first embodiment. [Fourth Embodiment] The memory device 2 〇〇c according to the fourth embodiment basically has the same configuration as that of the memory device 200 according to the first embodiment. The second 100132261 1003447808-0 37 201222827 transistor What is TR2? «Strong type of electro-crystal έ έ 忆 装置 2 2 2 2 2 2 2 2 和 和 和 和 和 和 和 岛 岛 岛 岛, in the case of the implementation of the first in the /, the knowledge of the * shape can be ± ~ four related to the repentance and readout and the situation with the supervision of the k Zhao 搫 体 农 农 20 _ _ _ _ _ _ _ _ _ _ Set 20 0 c, the information is written as follows.叼§有忆皿... To illustrate and describe Figure 18 is to use the information in 200c to write 虼 form four right p3 implementation form four has two to display. _Off memory is displayed. The memory device: c : 1 is used to explain the information read operation, that is, the _ &lt; _ 1 8 _ ^ a f + ^ ^ ~ of the Gu Yuan M0~M7 when writing The sub-twist line wL2〇~Wl No, the second word of the bridge two early M6 connected to the non-selected single-gate insulation layer-! The pass state voltage v°n' field term voltage Vci is strong, 6 is lower than the first and the opposite pair—the brake, the write-in voltage (VW: Vw &gt; Vcl) (-vci) The second write voltage ([, the voltage after the addition of the minus sign of the ink VC1 is accordingly, because of the non-selection unit M0 to M7 Vw]: Bu Vw] &lt; - Vcl). (ON), so even if the second transistor TR2 that is not used is turned on M TR2^ig^ - the transistor TR1, it can pass through the second transistor and the second source and the second source of the 7&quot; The extreme ground potentials of the potentials of the _ bit line BL and the plate line pL are the same. Therefore, the information held by the first transistor TR1 in the non-selection units Μ0 to Μ5, Μ7 is not destroyed, and new information can be written to the selection unit Μ6. As a result, the solid-state electronic component 1 〇〇c (and the memory device 200c according to the fourth embodiment) used in the fourth embodiment is a solid-state electronic component that does not cause the [writing interference problem] (and the device). ). 100132261 1003447808-0 38 201222827 Moreover, as shown in FIG. 19, when the information is read, the second word line connected to the non-selected units M0 to M5, M7 is applied to the second state, and the ON state voltage V is applied to the WU7. n, and applying a wearing state voltage V〇f to the second word line connected to the selecting unit M6, whereby the second transistor TR2 in the frying selection units M〇 to M5 and Μ are turned on ( ON), the second transistor TR2 in the selection unit Μ6 is turned off (OFF), so that the bellows held in the selection unit Μ6 can be read. That is, by applying a gauge between the bit line BL and the plate line PL

If the voltage of 疋 is current, it is judged whether the information written to the selection unit 兀* M6 is [丨] or [〇] by the current flowing at that time. Therefore, 贝 is read and held in the selection unit M6, and then Neither of the second word lines WL2 〇 WL WLz7 is connected to the first transistor TR1, so neither of the non-selected cells M0 M M5, M7 and the selected cell M R T1 Will destroy the kept beggars. The junction &amp; 'the solid-state electronic component 〇〇c used in the fourth embodiment (and the memory device 2 (10) related to the Bellows form 4 is a solid-state electronic component (and memory that does not cause the [read dry, problem] to occur) Body device) Fig. 2 shows the memory device 2 〇〇c which is not related to the fourth embodiment

A diagram of the drive waveform when the tribute is written. Fig. 20 (a) is a view showing a driving waveform for driving the first transistor TR2, and Fig. 2 (b) is a view showing a driving waveform for driving the first transistor TR1. Fig. 21 is a view for explaining a driving waveform at the time of reading information in the memory device 200c according to the fourth embodiment. Fig. 2 (&amp;) is, &quot;Bei is not used to drive the driving waveform of the second transistor TR2, and Fig. 2(b) shows the driving waveform for the first transistor T R1 for the body movement Figure 21 (c) shows the display and the pole current. 100132261 1003447808-0 39 201222827 In the 赵 装置 装置 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 200 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 That is, as shown in Fig. 2〇(a)^, the second character 硷WL2〇~WU7 of the pair of M0~M7 is attached to all the quotations #, a) Several lines of the ¥ state voltage V〇n (V〇n &gt; 0V). And as shown in Fig. 20(b), 'the skin can be called and the heart is 'connected to the non-selection list; the first word line WL of M0~M5, M7 is applied to the ground potential as early as WU5, wl]7 0V), and the first word line WL丨6 connected to the selected single case ping π Μ6 is higher than the first writing f of the first gate insulating layer & % (Vw:Vw&gt;Vcl) and the comparison of the first-noisy box a. The voltage of the coherent voltage of the closed insulating layer Vcl is lower than the voltage Η(1): the write voltage (Bu vw): [_vw]&lt; Negative any one. Further, 'the first word line wL1〇~wLl5, wLl7 connected to the non-selection cells MQ~M5, M? is applied lower than the coercive voltage Vc1 of the first gate insulating layer and compared The coercive voltage Vci of the gate insulating layer may be a voltage V ([-Vcl] &lt; v &lt; Vcl) of the electric dust (-Vcl) after the negative sign is added. Moreover, the second word connected to the selection unit M6 may be used. The off-state voltage V 〇 ff (for example, 0 V) may be applied to the element line WLz6. In the memory device 200c according to the fourth embodiment, the driving waveforms as described above are given to the respective first word lines and Second character line, making The second transistor TR2 in the minority selection units M0 to M5 and M7 is always in an ON state during the non-selection period, so that the selection can be made through the second transistor TR2 without using the first transistor TR1'. Each of the second and second source terminals of the cell M6 has the same ground potential as the potential of the bit line BL and the plate line PL. Therefore, the first transistor in the non-selected cells M0 to M5, M7 is not destroyed. The information held by T R1 can be written into the selection unit 100132261 1003447808-0 40 201222827 unit M6. On the other hand, in the embodiment, the memory device 200c related to the operation of FIG. 2 can be used. Waveform 袼~- Figure 21 (a) shows the readout of the connection 仃 仃 。 。 。 。 。 。 。 。 。 。 。 。 WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL The selection unit M6 "likes the voltage v〇n (v〇n &gt; 〇v), and the voltage Voff (for example, 0 V). And the word line WL26 applies the off state ^, ^ a . Fig. 21 (b), The first a _ 1L connected to each of the brothers D 隐 卓 卓 卓 卓 M M M M M WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL The first character line WI^O'WLj of the first sputum m _ WT n WT body early 兀MO~M7 is applied lower than the coercive voltage Vcl of the first gate insulating screen s and compared with the first gate insulating layer The voltage Vc 1 is attached to the voltage V ([-Vcl] &lt; V &lt; Vcl) at which the voltage (_Vcl) after the minus port is negative. In the memory device 2〇〇c related to the fourth embodiment, by driving the driving waveform as described above to each of the first word line and the second word line, the flow between the bit line and the plate line is performed. After the gate current shown in Fig. 21 (〇), it can be judged by the magnitude of the drain current that the memory held by each memory cell is [丨] or [〇], and as a result, it can be maintained. The information of each memory cell is read. The memory device 2 〇0 C according to the fourth embodiment has the same function as the first embodiment except that the second transistor TR2 is an enhanced transistor. Since the memory device 20 is configured in the same manner as in the case of the memory device 20, it has the same functions as those of the memory device 200 according to the first embodiment. The memory devices 200 to 200c according to the first to fourth embodiments ( And 100132261 100344:7808-0 201222827 Solid-state electronic components 1 0 0~1 0 0 c) can be fabricated using well-known thin film forming techniques and photolithography' and liquid materials can be used (for example, MOD (Metal Organic Decomposition: Metal Organic) break down A material, a sol-gel material, or a nanoparticle-dispersing liquid material, and can be produced by an embossing technique. <Method for Manufacturing Memory Device 200b According to Third Embodiment> The manufacturing method of the memory device 2000b will be described as an example of a method of manufacturing the memory device 200 to 2000c according to the fourth embodiment. The memory device 200b according to the third embodiment can be used. The first process to the fifth process shown below are manufactured in this order. The process sequence will be described below. Fig. 22 is a view for explaining the method of manufacturing the memory device 200b according to the third embodiment. 22(a) to 22(f) are diagrams of the respective processes. Further, 'Fig. 22(a) to Fig. 22(f) are diagrams corresponding to Fig. 12(b). (1) The first process of the first process is A process of forming the first gate electrode layer 120 in the surface of the solid substrate 110 (refer to FIG. 22 (a) to FIG. 2 2 (b)). As shown in FIG. 22(a) and FIG. 22(b), the use is hidden. The SpUttering method and lithography are based on the formation of the STO (SrT 1 0 ) layer on the surface of the Si substrate via the Si〇2 layer and the butyl layer. The first substrate electrode layer 12 made of platinum (Pt) is formed on the surface of the solid substrate 11 of the substrate. Further, although the sputtering method and the lithography are used in the first process, the solid substrate 1 10 The surface forms a first gate electrode layer 120' composed of platinum (pt) but using vacuum evap〇rati〇n meth〇d (example 100132261 1003447808-0 42 201222827 such as EB steaming method (E 1 Er + rw ώ B eamevap 〇rati ο nmethod : electron beam evaporation method) or CVD method. 1 u ^ Chemical Vap〇r Deposition method: chemical vapor deposition method and lithography, formed on the surface of the solid substrate u〇 The first gate electrode layer 120 composed of platinum (Pt) may be formed of platinum (Ρΐ) on the surface of the solid substrate 110 by using a solvent-solid solution containing white all-material and an embossing forming technique using a concave-convex mold. The first gate electrode layer 120 may be formed. (2) The second process / the second process is a process of forming the first gate insulating layer 132 on the surface of the solid substrate 110 and the first gate electrode layer 12 (see Fig. 22 (c)). As shown in Fig. 22(c), on the surface of the solid substrate 11 turns, I is formed of PZT on the surface of the solid substrate 11〇, and the first gate electrode layer is covered by 俾, and then the CMP method is used (Chemical Mechanical p〇) Ushing meth〇d: chemical mechanical polishing) grinding a layer composed of the PZT to form a first gate insulating layer 132. (3) The third process 〇 third process is to form a connection layer including a first channel region 142, a second channel region 144, and a third channel region 146 on the surface of the first gate insulating layer 132 and continuing in the channel regions. The process of the conductor layer 14 is (see Fig. 22 (d)). As shown in FIG. 22(d), a first channel region 142, a second channel region 144, and a second channel region 146 are formed on the surface of the first gate insulating layer 132 by using a sputtering method and a lithography, and are continued in the channels. The conductor layer 140 of the connection layer of the region. The conductor layer 14 is made of an oxide conductor material composed of indium tin oxide UT0) having a carrier concentration of ixl 〇 18 cm - 3 to 1 x 100 132 261 100 3 447 808 - 0 43 201222827 1 021 cn T3. (4) The fourth process of the fourth process is to include the first gate insulating layer 132 and the first channel region 142, the second channel region 144 and the third channel region 146, and the connection layer continuing in the channel regions. The surface of the conductor layer 140 forms a process of the second gate insulating layer 150 (refer to FIG. 22 (e)). As shown in Fig. 2 2 (e), a layer of 'PZT' is formed on the surface of the first gate insulating layer 132 to cover the above-mentioned conductor layer 140, and then CMP is used to polish the PZT. The layer formed constitutes a second gate insulating layer 150. (5) The fifth process The fifth process is a process of forming the second gate electrode layer 160 on the surface of the second gate insulating layer 50 (refer to Fig. 22 (f)). As shown in Fig. 22 (f), a second gate electrode layer 16A made of the inscription (A1) is formed on the surface of the second gate insulating layer 150 by sputtering and lithography.

Further, although a sputtering method and lithography are used in the fifth process, a second gate electrode layer 160 made of aluminum (A1) is formed on the surface of the second gate insulating layer 150, but vacuum iridium plating is used ( For example, ρ β , , , such as ruthenium plating, or CVD and lithography, on the surface of the second gate insulating layer 150, the second gate composed of aluminum (Α1) is formed. The electrode layer 160 may be formed of a sol-gel solution having a platinum material and a embossing forming technique using a concave-convex mold, and the surface of the insulating layer of the second gate is formed of Ming (Α1). The second gate electric rabbit pole layer 1 60 is also available. As described above, the memory device 100132261 1003447808-0 201222827 200b can be manufactured in relation to the real t-shaped dioxin. Further, in the above manufacturing method, the layer composed of Si (h can be replaced by a layer composed of PZT) The layer is used as the second gate insulating layer 150 to fabricate the memory device 200 related to the first embodiment. Moreover, ^ can be formed on the surface of the solid substrate 110, the second gate electrode layer 160, and the first gate The insulating layer 150, the conductor layer 140, the first gate insulating layer 1 32, and the first gate a β electrode layer 1 2 0 are grown in this order, and are upgraded to a layer composed of Si〇2. The layer formed by ?2&gt;1« is used as the second gate insulating layer! 5 〇, the memory related to the second embodiment is manufactured (1 device 200a. And 'can be formed by PZT by forming a layer composed of si 〇2 The layer is used as the second gate insulating layer 150, and the impurity concentration or layer thickness of the conductor layer 140 is adjusted, and the memory device 2 0 0 c according to the fourth embodiment is manufactured. <Memory related to the third embodiment Another manufacturing method of the body device 2〇〇b> The three related memory devices 20 〇b can be manufactured by the first process to the fifth process shown below in this order. However, in the memory device 2〇〇b related to the third mode In another manufacturing method, the first gate electrode layer 120 and the second gate electrode layer 160 are formed by a layer composed of LN0. Hereinafter, another embodiment of the s-remember device 200b related to the third embodiment will be described in accordance with the process sequence. Fig. 23 to Fig. 2 are views for explaining another method of manufacturing the memory device 2 〇〇b according to the third embodiment. Fig. 23(a) to Fig. 23(f) and Fig. 24(a) ~ Fig. 24(e), Fig. 25(a) - Fig. 25(e), Fig. 26 (&)~ Fig. 26(e) and Fig. 27(a) to Fig. 27(f) are the respective processes Fig. 100132261 1003447808-0 45 201222827 (1) First process The first process is a process of forming a first gate electrode layer 120 on the surface of the solid substrate 110 (refer to FIG. 23). First, 'be prepared by heat treatment. A functional liquid material of lanthanum nickelate (LaNi〇3). Specifically, the preparation contains a metal inorganic salt (meta) l inorganic salt) (lanthanum nitrate (hexahydrate) and nickel acetate (tetrahydrate) solution (solvent: 2 - methoxyethanol (2 - meth) ο X yethan ο 1)) ° Next, as shown in Fig. 23 (a) and Fig. 23 (b), an insulating substrate in which an STO (SrTiO) layer is formed on the surface of a Si substrate via a SiCh layer and a Ti layer. One surface of the solid substrate 110 is coated with a functional liquid material (for example, 500 rpm, 25 seconds) using a spin coating method and then placed on a hot plate by placing the solid substrate 110 on the hot plate (hot) Plate) was dried at 60 ° C for 1 minute to form a precursor composition composition (precursor composition 1ayer) 120' (layer thickness 300 nm) ° followed by 'as shown in Fig. 23 (&lt;:)~ Fig. 23 (e), the embossing process is performed on the precursor composition layer 1 20' at i50 〇c using the embossing mold M1 having a step difference corresponding to the step of the first gate electrode layer 120, in the precursor composition layer 丨2〇' Forms an embossed structure. The pressure applied to the embossing process was 5 MPa. Secondly, by performing the overall etching on the precursor composition layer 1 2 弱 under weak conditions, the precursor composition layer 1 2 0 is completely removed from the region other than the region corresponding to the first gate electrode layer 12〇. , (Comprehensive | Worm 100132261 1003447808-0 46 201222827 Clothing &amp; ) ° The full face engraving process is carried out using a wet etching technique (HF: ΗΠ solution) without using a vacuum process. Most: After the use of RTA (Rapid Thermal Annealing: fast,, clothing straight and high temperature (6 5 0 1:, 1 〇 minutes) on the precursor composition layer 120 finishing heat treatment, as shown in Figure 23 (f) As shown, the first gate electrode layer 12 made of lanthanum nickelate (LaNi〇3) is formed from the precursor composition layer 120. (2) The second process first process is on the solid substrate 110 and the first gate electrode The surface of the layer 120 forms a first insulating layer 1 32 (see FIG. 24). As shown in FIGS. 24(a) and 24(b), the surface of the solid substrate 110 is coated with a ferroelectric holding material. A solution of the raw material (for example, a PZT sol-gel solution) forms a film 1 30' of a raw material containing a ferroelectric material, and covers the first gate electrode layer 120. Then, 'the film 1 containing the raw material of the ferroelectric material 3 〇 'after drying', as shown in Fig. 24 (c) and Fig. 24 (d), the flat mold M2 is pressed against the film 丨 30' of the raw material containing the ferroelectric material to make the original ◎ containing the ferroelectric material. The film 130' of the material is planarized. Next, the film 13' of the raw material containing the ferroelectric material is subjected to heat treatment using an RTA apparatus, as shown in Fig. 24 (e). Forming the first gate insulating layer 132. (3) The third process of the third process is to form a first channel region 142, a second channel region 144, and a third channel region 146 on the surface of the first insulating layer 132. The process of the conductor layer 140 of the connection layer of the channel regions 142, 144, 146 is continued (refer to FIG. 25). 100132261 1003447808-0 47 201222827 First, as shown in Fig. 25(a) and Fig. 25(b) A film 140' containing a raw material of a vaporized conductor material is formed by applying a solution (for example, an IT sol-gel solution) containing a raw material of an oxide conductor material to the surface of the first gate insulating layer 132. In the solution containing the raw material of the oxide conductor material, the concentration of the carrier concentration of the conductor layer 14〇 at the concentration of i X ltTcnT3 to lxl02IcnT3 at the completion of the addition is added. Next, the film of the raw material containing the oxide conductor material is added. 14〇, after drying, as shown in FIGS. 25(c) to 25(4), an area corresponding to the first channel region 142, the second channel region 144, and the third channel region _146 and the connection layer continuing in the transport regions is used. Become a phoenix The embossing mold M3 embosses the film 140 of the film 丨 4 n, */ containing the raw material of the oxide conductor material. At this time, the embossing process for the raw material containing the oxide conductor material is performed. The layer thickness of the channel region 142 and the second channel region "4" and the third channel ... 46 becomes a predetermined layer thickness within the range of y upon completion. Next, by completely engraving the film ".' of the raw material containing the oxide conductor material under weak conditions, the film containing the material of the oxide conductor material is completely removed from the region other than the region corresponding to the conductor layer 14? The film 140 of the raw material containing the oxide conductor material is heat-treated by using an im device, and as shown in FIG. 25(e), the first channel region 142, the second channel region 144, and the third channel are formed. a region $146 and a conductor layer 140 continuing in the connection layer of the channel regions 142, 144, 146. (4) The fourth process of the fourth process is to form a second barrier 100132261 1003447808 on the surface of the first-id insulating layer 132. -0 48 201222827 The formation of the edge layer 150 is referred to Fig. 2 6 ). As shown in Fig. 26 (a) and the surface coating including the ferroelectric 26 (b), the surface layer of the first gate insulating layer 132 is formed. A solution containing a raw material of iron (for example, PZT sol-gel-solubilized film 150' of the raw material of the material. Next, the raw material of the ferroelectric material as shown in Fig. 26(c) and Fig. 23 will be enclosed. After the film 150' is dried, the raw material d) containing the ferroelectric material is dusted by the flat mold 4 The envelope 150 flattens the 骐15〇 of the i, and causes the 包含 包含 of the raw material containing the ferroelectric material to be subsequently subjected to heat treatment using RTa &amp; to form a film 15 〇 for the raw material containing the ferroelectric material. The second gate insulating layer 150. (5) The fifth process of the fifth system is a process for forming the second gate electrode layer 160 on the surface of the gate insulating layer 150 (岌^, 屯, 屯, Referring to Fig. 2 7). First, a functional liquid material which is prepared as a lanthanum nickelate (LaNiCh) by the treatment of ., 'process. Specifically, 1. The clothing contains a metal inorganic salt (niobium nitrate (hexahydrate)). And a solution of nickel acetate (tetrahydrate human Q) (solvent: 2 - decyloxyethanol). Next, as shown in Fig. 7 r , [a) and Fig. 27 (b), in the second gate insulating layer A functional liquid material (for example, 500 rpm, 25 seconds) is applied by spin coating to one of the 150 sheets, and then the solid substrate 11 is placed on the crucible at 60 ° C. The dry 丨8#, i ... τ 丄 knife clock, forms the precursor composition layer 160' of strontium nickelate (layer thickness 30 0nm). Second, as shown in the figure, ( c) to Fig. 27(e), using a concave-convex mold M5 having a step difference corresponding to the step of the second gate electrode layer 160, 15 〇 (: for the precursor composition layer 1 60 0 ' Applying anaerobic, 乂 pressure processing, in the 耵 物 composition layer 1 6 〇, 100132261 1003447808-0 49 201222827 The formation of the face money removal process is carried out on the previous month! J drive 16 0. 20 0b and the real layer implementation 160, and the first layer of the layer is an embossed structure. The pressure applied to the embossing process is 5 Μ P a . Next, the precursor composition layer 160' is completely engraved by weak conditions from the region other than the region corresponding to the second gate electrode layer 160. (Complete etching process). The full etching process uses a wet etching technique (HF: HC1 solution) without using a vacuum process and finally, by using an RTA device and heat treatment at a high temperature (650t, 10 minutes) of the composition layer of the coating, as shown in Fig. 2 As shown in Fig. 7 (f), the bismuth electrode layer r composed of strontium nickelate is formed from the composition layer 160 as described above, and can be produced in accordance with the third embodiment. In this case, a liquid material can be used instead of the memory device 200b associated with the third embodiment. In the above-mentioned manufacturing method, the layer formed of PZT is replaced by a layer formed of BZN as a second gate barrier layer 150, manufactured and shaped. The relevant memory device is 200. In this case, the layer of ruthenium can be formed using a ruthenium sol-gel solution. Further, by the surface of the solid substrate 110, the second gate insulating layer 150, the conductor layer 14C, and the first-'th gate electrode layer 120 are formed in this order and the layer formed by ΡΖΤ is substituted as the first layer. The second memory device 200 a 〇 and 5 can be replaced by a layer formed of Β Ν 作 as the second gate insulating layer 150, and the conductor layer of the conductor layer is adjusted. 1 3 2 Formation 1 5 , 。 , , 制造 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 [Fifth Embodiment] Fig. 28 is a view for explaining the display of a memory device set 200d according to the fifth embodiment. 28(a) is a plan view of the memory device 200d. FIG. 28(b) is a cross-sectional view taken along line A1-A1 of FIG. 28(a), FIG. 28(c) is a cross-sectional view taken along line A2-A2 of the figure, and FIG. 28(d) is a cross-sectional view of FIG. Fig. 28(a) is a cross-sectional view taken along line A3-A3 of Fig. 28(a). Further, the symbol in Fig. 28 indicates a metal layer for resistance reduction. Figure 17〇

Fig. 29 is a view for explaining the display of the memory f 200d according to the fifth embodiment. Figure 29 (a) is an enlarged view of the portion of the symbol r of Figure 29 (d) (the solid-state electronic component 1 〇〇d used in the fifth embodiment). Figure 29 (b) shows the first gate insulation. The coercivity φ of layer 1 32 ( 1 30 ) is only %*

The relationship between Vcl and the write voltage (+Vw, -Vw) of the first transistor TR1 is similar to that of the memory device 200d according to the fifth embodiment. As shown in FIG. 28 and FIG. 29, the solid electronic component is a so-called plane-separated solid-spray Kyoko element in which the first transistor tri and the second transistor TR 2 are separated in a plane. The case of the memory device 2 of the form 1 is different. That is, the solid state electronic component 100 used in the fifth embodiment (1 is the second gate insulating layer 134 is composed of a ferroelectric layer in the same layer as the first gate insulating layer 1 32, the first transistor TR1 and the second transistor The crystal TR2 has a gate electrode layer 120a, 120b' constituting the first gate electrode 122 and the second gate electrode 124 on one surface of the solid substrate 110 and constitutes the first gate insulating layer 132 and the second 100132261 1003447808-0 201222827 The gate insulating layer 1 3 0 of the gate insulating layer 1 3 4 and the so-called plane-separated solid state of the structure formed by the conductor layer 140 constituting the first channel region 1 4 2 and the second channel region 1 44 in this order In the electronic device (lower gate type), the memory device 20 Od according to the fifth embodiment is separated in the plane between the first transistor TR1 and the second transistor TR2, and is related to the first embodiment. The memory device 200 is different in the case of having the first gate electrode 1 2 2 and the second gate electrode 1 24 4 connected to the other gate line (the first word line 120a and the second word element). The structure in which the wires 120b) are connected in parallel, and In the same manner as in the case of the memory device 200, the memory device does not cause the [write interference problem] and the [read disturb problem]. Further, the memory device 20 according to the fifth embodiment In the case where the solid-state electronic components (the first transistor TR1 and the second transistor TR2) are planar-separated solid-state electronic components, the case of the memory device 200 related to the first embodiment is present. The same configuration has the same effect as that of the memory device 2000 according to the first embodiment. [Embodiment 6] FIG. 30 is a view for explaining the memory device 2 according to the sixth embodiment. Fig. 3 (a) is a top view of the memory device 2000, Fig. 30 (b) is a cross-sectional view of A1-A1 of Fig. 30 (a), and Fig. 30 (c) is a view 30(a) is a cross-sectional view of A2-A2, Fig. 30(d) is a cross-sectional view taken along line A3-A3 of Fig. 30(a), and Fig. 30(e) is a cross-sectional view taken along line A4-A4 of Fig. 30(a). It is a diagram for explaining the memory device 100132261 1003447808-0 52 201222827 2〇〇e related to the sixth embodiment. Fig. 31 (a) is surrounded by the symbol R of Fig. 31 (d). An enlarged view of a portion (solid state electronic component 10 〇e used in Embodiment 6), and FIG. 31 (b) shows a grading voltage VC1 of the first gate insulating layer 132 (13 〇) and the first transistor TR1 A diagram of the relationship between the write voltages (+Vw, -Vw). The memory device 200e according to the sixth embodiment is basically the same as the memory device 200d associated with the fifth embodiment, and the solid-state electronic components are separated. The solid-state electronic components of the type, as shown in FIG. 30 and FIG. 31, the case where the 7G piece of Guping Electronics is the upper gate type and the case of the setting 200d related to the fifth embodiment is not (5). = body mount, that is, the solid state electronic component 丨〇〇e used in the sixth embodiment is the second gate insulating layer 134 composed of a ferroelectric layer in the same layer as the first gate insulating layer 32, the first transistor m and The second transistor TR2 has a conductor layer 140 constituting the first channel region 142 region 144, and a gate insulating layer 13 constituting the first gate insulating layer i32 and the insulating layer 134 on one surface of the solid two plates m. 'With the first gate electrode::

C. The idle electrodes |120a, 120b of the second sm are in the order of the so-called planar separation type (upper gate) solid state electronic components. &amp; Thus, the memory device state electronic component trace related to the sixth embodiment has a structure of an upper gate, which is different from the case of the memory device 2_ related to the == solid, but has 2...five poles 122 and Since the two gate electrodes 124 are connected in parallel in a state in which they are connected to 120a and 12Qb, the memory device 200d related to the fifth is a memory that does not: 7, the interference problem, and the [readout interference problem]. Device: L writes 100132281 1003447808-0 53 201222827 In addition, the memory device 2 0 0 e related to the configuration of the sixth embodiment has a point other than the point where the solid electronic component 1 〇〇e has the upper gate. The configuration of the memory device 2〇〇d according to the fifth embodiment has an effect equivalent to that of the memory device 20Od according to the fifth embodiment. In addition, the steam knows the state of the five and six related memory devices 2〇〇d, 200e (and solid state electricity + 亓 phase ^ unH inn, £ 兀仵 兀仵 I00d, l〇〇e) and with the implementation of a ~ For the case where the memory is 200, 9nn /, 1 zuu ~ 20 〇 c (and solid-state electronic components 100, 100a - 100c), the monthly bath inspection can be performed using well-known thin film forming technology and lithography. And can use this material to use liquid materials (such as M0D (Metal

Organic Decomposition: metal right 嫱 姑 λ 蜀 organic knives), sol-gel materials, nanoparticle dispersion liquid materials, and can be manufactured using embossing technology. Manufacturing method of 20000> Manufacturing method of 20000 (memory of the memory of the fifth aspect) Memory I of the fifth embodiment is set to 2 0 0d ' 2 0 0 e as an example for description and implementation Forms 5 and 6 related to the manufacturing method of the 4 y 丨 的 己 体 。 。 device. 200d can be manufactured by the following. In the following, the first to fourth processes of the memory device according to the fifth embodiment are executed in this order. The memories 32(a) to 32(e) of the fifth aspect are the respective process sequences. Fig. 3 is a view for explaining the method of manufacturing the device 20d. Figure. The surface of 0 forms a gate electrode layer (the first process of the first process is on the solid substrate 100132261 1003447808-0 201222827, a 3-pole line 12〇a, a second gate line 120b, a first gate electrode 122, and a The process of the two gate electrode 124) (refer to Fig. 32 (a, Fig. 32(b)). As shown in Fig. 3 2 (a) and Fig. 3 2 (b), sputtering method and lithography are used in [in Si A gate electrode layer (first gate line) made of platinum (pt) is formed on the surface of the solid substrate 11 which is formed by interposing an insulating layer on the surface of the substrate with an Si 2 layer and an n-layer forming an insulating substrate of a ST 〇 (SrTi〇) layer. 1 2 〇a, second gate line 1 2 〇b, first gate electrode 122 and second gate electrode 124). Further, although sputtering and lithography are used in the first process, the solid germanium substrate 110 is A gate electrode layer made of platinum (pt) is formed on the surface, but a gate electrode made of platinum (Pt) is formed on the surface of the solid substrate 110 by vacuum evaporation (for example, EB evaporation) or CVD and lithography. The layer may also be formed of platinum on the surface of the solid substrate 110 by using a sol-gel solution containing a platinum material and an embossing forming technique using a concave-convex mold. Pt) The gate electrode layer may also be formed. (2) The second process first process is to form a gate insulating layer on the surface of the solid substrate 110 and the gate electrode layers 12a, i2〇b, 1 2 2, and 1 2 4 . Process of 1 30 (refer to Fig. 3 2 (c )). As shown in Fig. 32 (c), a layer composed of PZT is formed on the surface of the solid substrate 11 () by using a dry plating method, and the gate electrode layer is covered with germanium ( The first interrogation line 120a, the second gate line 120b, the first gate electrode 122, and the second gate electrode 124) are then polished by a CMP method to form a layer of the PZT to form an interlayer insulating layer 130. (3) The third process of the third process is to form a connection layer including a first channel 100132261 1003447808-0 201222827 region 142, a second channel region 144 and a third channel region 146, and a continuation layer in the channel region of the gate insulating layer 130. The process of the conductor layer 140 (refer to FIG. 32(d)). As shown in FIG. 32(d), a sputtering method and a lithography are used to form a first channel region 142 and a second channel on the surface of the gate insulating layer 13A. a region 144 and a third channel region 146 and a conductor layer 140 continuing the connection layer of the channel regions. The conductor layer 140 is used The oxide conductor material composed of indium tin oxide (ITO) is formed in the range of ixl 〇ucnr3 to lx 1 021cnT3. (4) The fourth process of the fourth process is a predetermined region on the surface of the conductor layer 140. A process for forming the metal layer 170 for resistance reduction is formed (see FIG. 32(e)). As shown in FIG. 32(e), in the connection layer in the conductor layer 140, a region intersecting the first gate line 1 2 0 a or the second gate line 1 2 0 b is formed into a metal for resistance reduction. Layer 170. The memory device 200d according to the fifth embodiment can be manufactured as described above. Further, in the above manufacturing method, the metal layer 170 for the resistance reduction, the conductor layer 14, the gate insulating layer 130, and the gate electrode layer (the first gate line 12A) can be formed on the surface of the solid substrate. a, the second interpolar line a吒, the ^-gate electrode 1 22, and the second gate electrode! 24) formed in this order, and the memory device 2〇〇e related to the sixth embodiment is manufactured. <Another manufacturing method of the memory device 2〇〇d according to the fifth embodiment> 100132261 1003447808-0 56 201222827 The memory device 200d related to the fifth embodiment can also be processed by the first process shown below. ~ The fourth process is manufactured in this order. However, in another manufacturing method of the memory device 2〇〇d according to the fifth embodiment, the gate electrode layer (first gate) is formed by a layer composed of lanthanum nickelate (L an丨〇3). The line 120a, the second gate line 12〇b, the first gate electrode 122, and the second gate electrode 1 24) and the metal layer for resistance reduction are described below. The memory device according to the fifth embodiment is described in accordance with the process sequence. Another method of manufacturing 〇d. Fig. 3 3 to Fig. 3 are diagrams for explaining another method of manufacturing the memory device 20 〇d according to the fifth embodiment. 33(a) to 33(0, 34(&amp;)~Fig. 34(e) and Fig. 35(a) to Fig. 35(f) are diagrams of each process. (1) First process first process The process of forming the gate electrode layer (the first gate line 12a, the second gate line 120b, the first gate electrode 122, and the second gate electrode 1 2 4) on the surface of the solid substrate 11A (refer to FIG. 3) 3) First, a functional liquid material which becomes a lanthanum nickelate (LaNi〇3) is prepared by heat treatment. Specifically, a metal inorganic salt (cerium nitrate (ruthenium hexahydrate) and nickel acetate (tetrahydrate)) is prepared. Solution (solvent: 2-methoxyethanol). Next, as shown in Fig. 33(a) and Fig. 33(b), 'STO is formed by [Si 2 layer and Ti layer on the surface of the Si substrate ( Insulating Substrate of SrTi〇) Layer One surface of the solid substrate 110 is coated with a functional liquid material (for example, 500 rpm, 25 seconds) by spin coating. Then, the solid substrate 110 is placed on a hot plate. 6 (TC is allowed to dry for 1 minute to form a precursor composition layer 1 20' (layer thickness 300 nm). Next, as shown in Fig. 33(c) to Fig. 33(e), the use of the corresponding gate 100132261 1 003447808-0 57 201222827 The concave-convex mode M6 of the step difference of the step of the pole layer (the first gate line 120a, the second gate line 120b, the first gate electrode 122 and the second gate electrode 124), the precursor at 150 ° C The composition layer 1 2 0 ' is subjected to embossing, and an embossed structure is formed in the precursor composition layer 1 20'. The pressure applied to the embossing process is 5 MPa. Second, the precursor is composed by weak conditions. The layer 1 2 0 ' performs a full button engraving, and the corresponding electrode layer (the first gate line 1 2 0 a, the second gate line 1 2 0 b, the first gate electrode 1 2 2 and the second gate electrode 1) The region outside the region of 2 4 ) completely removes the precursor composition layer 1 2 0 ' (full etching process). The overall etching process is performed using a wet etching technique (HF . · HC1 solution) without using a vacuum process. The precursor composition layer 1 2 is heat treated by using an RT A device and at a high temperature (65 ° C, 10 minutes), as shown in Fig. 3 3 (f), from the precursor composition layer 1 2 0 ' forming a gate electrode layer composed of strontium nickelate (first gate line 120a, second gate line 120b, first gate electrode) 122 and the second gate electrode 124). (2) The second process of the second process is on the solid substrate 11 and the gate electrode layer (the first gate line 120a, the second gate line 120b, the first gate electrode 122, and The surface of the second gate electrode 124) forms a process of the gate insulating layer 130 (refer to FIG. 34). As shown in FIGS. 34(a) and 34(b), a solution containing a raw material of a ferroelectric material (for example, a PZT sol-gel solution) is applied onto the surface of the solid substrate 110 to form a film 1 containing a raw material of a ferroelectric material. 30', 俾 covers the gate electrode layer (first gate line 1 20a, second gate line 1 20b, first gate electrode 1 22 and second gate electrode 1 2 4). 100132261 1003447808-0 58 201222827 The film 130 of the raw material is dried by pressing the flat mold M7 to the film 13 of the raw material containing the ferroelectric material, and then 'after the ferroelectric material will be contained' 34(c) and FIG. 34(d), the film 1300' of the film of the ferroelectric material is flattened. Next, the iron containing material is subjected to heat treatment using an RTA apparatus to form a gate insulating layer 130. (3) a third process crack in the open insulating germanium region 142, the second channel region 144, and the third channel region or a conductor layer extending from the connecting layer of the channel regions 142, 144, 146. Process (refer to Fig. 35 (a) ~ Fig. 35 (e)). #First, as shown in Fig. 35 (a) and Fig. 35 (b), by using a solution of a raw material containing an oxide conductor material (for example) The IT sol-gel solution is applied to the surface of the gate insulating layer 130 to form a material containing the oxide conductor material, and further, the solution of the material containing the oxide conductor material is added to the conductor layer 140 at completion. The concentration of the carrier becomes a concentration of impurities in the range of lxl 〇 18 cm_3 to ix O 1 〇 21 cnr3. Next, after drying the film i40 containing the raw material of the oxide conductor material, as shown in Fig. 35 ((〇~图35 ( d) shows a concave-convex mold M8 formed by using four regions corresponding to the first channel region 142, the second channel region 44 and the third channel region 146, and the connecting layer continuing in the channel regions, The film of the raw material of the conductor material is embossed and formed. The embossing process of the film 14A containing the raw material of the oxide conductor material, the layer thickness of the first channel region 142, the second channel region 144 100132261 1003447808-0 59 201222827 and the second channel region 146 are completed. The predetermined layer thickness is in the range of 5 nm to 100 nm. Next, the film 14 0 containing the raw material of the oxide conductor material is completely engraved under weak conditions, and is outside the region corresponding to the conductor layer 1 40. The film of the raw material containing the material of the gas-conducting conductor is completely removed by heat treatment, and the film 140 containing the raw material of the oxide conductor material is subjected to heat treatment by using an RTA apparatus, as shown in FIG. 35(e). A conductor layer 140 including a first channel region 142, a second channel region and a third channel region 146, and a connecting layer continuing through the channel regions 142, ι 44, 146. Further, the first channel region 142 and the second channel The region 144 is separated. (4) The fourth process of the fourth process is a process of forming the metal layer 170 for resistance reduction in a predetermined region on the surface of the conductor layer 14A (see FIG. 35(f)). Shown in the conductor layer 丨40 Forming a resistance layer in connection with the reduced area of the first gate line 20a or a second gate line intersecting a 2〇b

A metal layer 170 is used. The formation of the metal layer 170 for resistance reduction is carried out by the method shown below. First, a functional liquid material which becomes lanthanum nickelate (LaNi〇3) is prepared by heat treatment. Specifically, a solution containing a metal inorganic salt (yttrium nitrate (hexahydrate) and nickel acetate (tetrahydrate)) (solvent: 2-methoxyethanol) is followed by a gate insulating layer 1 q η β _ _ The surface of the layer] ^ k # 130 and the body layer 140 is thinly coated with a functional liquid material (for example, 5 (10) rpm, 25 seconds), and then the solid substrate 110 is placed on a hot plate and dried at 6 Torr for "minutes". : 前 镍 镍 镧 镧 组成 组成 组成 组成 组成 1 1 1 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次 其次The last step of the precursor precursor layer 170 is performed, for example, at 200 d °, the surface of the substrate, 130, and the gate electrode are formed into a metal forming layer 100132261' with a corresponding resistance reduction. The embossing structure is formed by applying a embossing of the metal layer 17〇 to the embossing structure by applying a embossing precursor composition layer 1 70' to the precursor composition layer 170. It is 5 MPa. 'With weak strips The precursor composition layer 170 is subjected to a region precursor composition layer 170 other than the region of the metal layer 170 for resistance reduction (total etching process). The full etching is performed using a wet etching technique (HF: HC1 solution). The heat treatment is performed without using a vacuum 〇 'by using an RTA device and at a high temperature (65 0-1:1, 10 minutes) composition layer 170', as shown in Fig. 33(f), formed by the formation layer 170' The electric resistance reduction by the ruthenium nickelate can be used to manufacture the memory device of the fifth embodiment. The liquid device can be used to manufacture the memory device 2 〇〇d related to the fifth without using a vacuum process. In the above manufacturing method, the metal layer 170, the conductor layer 140, and the gate insulating layer electrode layer (the first gate line 12a, the second gate line i20b, and the 122nd layer) can be formed on the solid substrate 11 The second gate electrode 124) is formed in this order to fabricate a memory device 2 〇〇e. In this case, a recess is provided in a predetermined region of the solid substrate 110 by using embossing, and a low metal layer is formed. 1 70 material buried in the The concave portion forming resistance may be reduced by 170. 1003447808-0 201222827 [Embodiment 7] Fig. 36 is a view for explaining the memory according to the seventh embodiment in comparison with the memory of Fig. 7. Fig. 3 6 (a) FIG. 36(b) is a cross-sectional view taken along line A1-A1 of FIG. 36(a), and FIG. 36(c) is a cross-sectional view of A2-A2 of FIG. 36 (Fig. 36(d) is A36(a) A3-A3 cross-sectional view. The country 'it' is outside the 'paid number 180' to indicate the semiconductor substrate, the symbol 182 is the source [domain, pay 5 tiger 1 8 4 疋 table source area /> and polar region, symbol 186 is the surface bungee region . Fig. 37 is a view for explaining the memory multiplication 200f according to the seventh embodiment. 37(a) is an enlarged view of the same portion (the solid-state electronic component 1 0 0 f used in the seventh embodiment) surrounded by the symbol r of FIG. 36(c), and FIG. 36(b) shows the first gate. The relationship between the susceptibility Vcl of the insulating layer 132 (130) and the write voltage (+Vw, -Vw) of the first transistor TR1 is substantially the same as that of the memory device 20 0 f related to the seventh embodiment. The memory device 20 of the sixth embodiment has an upper gate configuration, but as shown in FIGS. 36 and 37, the first transistor TR1, the second transistor, and the third transistor TR3 are formed in the semiconductor. The MFS (Metal-Ferroelectric-Semiconductor) type transistor structure on the surface of the substrate 180 is different from the case of the memory device 200e according to the sixth embodiment. That is, in the memory device 20 0 f related to the seventh embodiment, the first channel region 142 and the second channel region 144 are located in a predetermined source region 1 8 formed on the surface of the semiconductor substrate 180. Between the source/drain region 1 8 4 and any two of the specified drain regions 1 8 6 , the first gate 100132261 1003447808-0 62 201222827 The insulating layer 1 3 2 is formed, and the first channel is covered by the crucible The region 1 4 2, the second gate insulating layer 134 is formed, and the second gate region 144 is covered, and the first gate electrode 12 2 is opposite to the first channel region 1 4 2 via the first gate insulating layer 13 2 Formed, the second gate electrode 1 24 is formed to face the second channel region 144 via the second gate insulating layer 134. As described above, in the memory device 200 according to the seventh embodiment, the first transistor TR1, the second transistor TR2, and the third transistor TR3 are constituted by MFS type transistors formed on the surface of the semiconductor substrate 180. Different from the case of the memory device 200 0 e related to the implementation mode 6, the first transistor TR1 for information memory and the second transistor TR2 for information read/write have the first gate Since the electrode 122 and the second gate electrode 124 are connected in parallel in a state in which the other gate lines 1 2 0 a and 1 2 Ob are connected in parallel, as in the case of the memory device 200e according to the sixth embodiment, It is a memory device that does not cause [write interference problem] and [read disturb problem] when it is used in a memory cell of a NAND type memory device. Further, according to the memory device 20 0 f related to the seventh embodiment, it is possible to obtain a memory device which can be manufactured at a low cost by using a general semiconductor process. Further, the memory device 2 0 0 f according to the seventh embodiment is composed of the MFS type transistor formed on the surface of the semiconductor substrate 180 in the first transistor TR1, the second transistor TR2, and the third transistor TR3. The point other than this point has the same configuration as that of the memory device 20Oe according to the sixth embodiment, and therefore has an effect equivalent to that of the memory device 200e according to the sixth embodiment. [Embodiment 8] FIG. 38 is a view for explaining a memory device 200g (not shown) according to the eighth embodiment. In Fig. 38, a main portion of a solid-state electronic component 1 〇 〇 g constituting a memory device of the eighth embodiment is enlarged and displayed. The memory device 200 g related to the eighth embodiment basically has a configuration similar to that of the memory device 20 〇f according to the seventh embodiment, but as shown in Fig. 38, 'the first transistor TR1, the second The transistor TR2 and the third transistor TR3 are composed of a MFIS (Metal-Ferroelectric-Insulator-Semiconductor) type transistor formed on the surface of the semiconductor substrate 180, and are related to the seventh embodiment. The memory device 2 0 0 f is different. That is, in the memory device 200g according to the eighth embodiment, the first channel region 142 and the second channel region 144 are formed with the first gate insulating layer 132 and the second gate insulating layer 134. The electric buffer layer 19 is. As described above, in the memory device of the eighth embodiment, the first transistor TR1', the second transistor TR2, and the third transistor TR3 are formed of MFIS type transistors formed on the surface of the U semiconductor substrate 170. This configuration is different from the case of the memory device 20000 according to the seventh embodiment, except that the first transistor TR1 for information memory and the second transistor TR2 for information reading/writing have the first When the gate electrode 122 and the second gate electrode 124 are connected in parallel to each other in the state of being connected to the other gate lines 1 20a and 1 2Ob, the memory device 20 0 f according to the seventh embodiment is used. It is a memory device that does not cause [write 100132261 1003447808-0 64 201222827 into the dry: problem] and [read disturb problem] when it is used in the memory unit of the NAND type memory device. According to the memory device of the eighth embodiment, the semiconductor device 180 (the gate insulating layer 132e* Ba u Si) and the ferroelectric material which forms the first insulating layer 134 between the first and second layers are obtained. Layer (for example, the effect of [bad interdiffusion phenomenon] produced. In addition, due to the implementation of the eighth embodiment, the Thunder TD, &amp; one version of the 200g in the younger day TR1, the second transistor TR2 And the third circuit contact, the private day body TR3 is formed of a MF IS type solid-state electric core element formed on the surface of the +conductor substrate I80, and has a point other than the point ' , the color of the device ~, the memory device 200 f of the same situation, so there are spots to implement the report ^ 〇Λ &quot;, there are eight ^ state seven related memory device 200 f [Embodiment 9] FIG. 39 is a view for explaining a memory device 2〇〇h (not shown) according to the ninth embodiment. FIG. 39 shows a configuration and an embodiment. Nine related memory devices 20 h of solid state electronic components 1 〇〇 h main part section magnification The memory device 20000 related to the only state 9 is basically composed of the memory device 20 〇g related to the implementation of the sorrow, but as shown in FIG. 39, the first The transistor TR1, the second transistor TR2, and the third transistor TR3 are formed of a solid state of the type of MFMISCM et al-Ferroelectric-Metal-lnsulator-Semiconductor: metal-ferroelectric-metal-insulator-semiconductor formed on the surface of the semiconductor substrate 18A. The electronic component configuration is different from the case of the memory device 2000g related to the eighth embodiment. 100132261 1003447808-0 65 201222827 That is, in the memory device 20Oh related to the ninth embodiment, between the paraelectric buffer layer 190 and the first gate insulating layer 133 and the second gate insulating layer 134 A floating electrode 1 9 2 is formed. In the memory device 20Oh according to the ninth embodiment, the first transistor TR1, the second transistor TR2, and the third transistor TR3 are constituted by MFMIS type solid-state electronic components formed on the surface of the semiconductor substrate 180. In the case of the memory device of the eighth embodiment, the case of the second transistor TR1 for information memory and the second transistor TR2 for information read/write have the first gate electrode 122 and the first The structure in which the two gate electrodes 124 are connected in parallel in the state in which the other gate lines 1 2 0 a and 1 2 0 b are connected in parallel is the same as in the case of the memory device 20 0 g related to the eighth embodiment. It is a memory device that does not cause [write interference problem] and [read disturb problem] when it is used in a memory cell of a NAND type memory device. Further, according to the memory device 2〇〇h related to the ninth embodiment, it is also possible to alleviate the area of the capacitor composed of the gate insulating layer 13 〇 and the capacitor composed of the parasitic buffer layer 190 by arbitrarily adjusting. The effect of charge mismatch between the gate insulating layers 132, 134 (130) having a large amount of residual polarization and the semiconductor substrate 180 having a small residual polarization. Further, the memory device 20〇h according to the ninth embodiment is composed of the MF MIS type solid-state electronic components formed on the surface of the semiconductor substrate 180 in the first transistor TR1, the second transistor TR2, and the third transistor TR3. The point other than this point has the same configuration as the case of the memory device 2000g related to the eighth embodiment. Therefore, the memory 100132261 1003447808-0 66 201222827 body device 200g has the same function as the eighth embodiment. A considerable effect. In the above-described sixth to eighth embodiments, the memory devices 200f to 2〇〇h (and the solid-state electronic components 100f to lGGh) can be manufactured using a general semiconductor process, but for the gate insulating layer, the gate electrode layer, and the parasitic buffer layer. Liquid materials can also be used for floating electrodes (eg M〇D (Metal)

Decomposition: metal organic decomposition) material, sol-gel material, nanoparticle dispersion liquid material). [Test Example] . The present invention will be described in more detail below by way of test examples. In the test example, when the separation structure using the first transistor TR1 and the second transistor TR2 is a stacked-separated memory device, when information is written to a predetermined selection unit, the display is [not connected to the selection unit. The second word line is in a floating state, but is preferably a test case in which the second word line ground potential is given. 1. The memory device is tested using a solid-state electronic component having a structure similar to the solid-state electronic component 100 of the memory device 2 of the first embodiment. 2. The evaluation method is according to the following writing method 1 and 2. The information is written to the above solid electronic component. That is, in the writing method 1, in the state in which the source terminals (the first source terminal and the second source terminal) of the solid-state electronic component and the 汲 terminal (the first 汲 terminal and the second 汲 terminal) are given a ground potential, The two gate electrodes are in a floating state and give a positive or negative write voltage to the first gate electrode (Vw = 100132261 1003447S08-0 67 201222827 ±8 V). Further, in the writing method 2, given the ground potentials of the source terminals (the first source terminal and the second source terminal) and the 汲 terminal (the first 汲 terminal and the second 汲 terminal) of the solid state electronic component, The second gate electrode is grounded and gives a positive or negative write voltage to the first gate electrode (Vw = ±8V). Further, in the writing method 1 or the writing method 2, the pulse width of the write pulse is changed in the range of 5x10_4&gt;, ~5xlO_1 second (5/zsec to 500msec). Then, the measurement flows when a predetermined readout potential is given between the source terminal (the first source terminal and the f': '% source terminal) of the solid state electronic component and the 汲 terminal (the first 汲 terminal and the second 汲 terminal) The bungee current. 2. Evaluation results Fig. 40 is a diagram showing the results of the test examples. As is apparent from Fig. 40, even in the case of the writing method 2, a large S/N ratio is obtained even in the case of a pulse width shorter than that in the writing method 1. That is, it is apparent that the writing method 2 can write information at a high speed to the selecting unit as compared with the writing method 1. Although the memory U-body block of the present invention, the method of manufacturing the same, the memory device, and the method of driving the memory device have been described above based on the above embodiments, the present invention is not limited to the embodiments, and does not deviate from The scope of the gist of the gist can be implemented, for example, the following modifications are also possible. (1) In the above embodiments, the solid state electronic component is applied to the NAND type memory, but the present invention is not limited to the NAND type memory. For example, the solid state electronic component can also be applied to other electronic circuits such as a switching circuit (s w i t c h i n g circuit). 100132261 1003447808-0 68 201222827 (2) In the above-mentioned embodiment, the solid-state technique 110 uses insulation such as a Si 〇 2 layer and a layer to form an STO (SrT i 0 ) layer on the surface of the Si substrate. The substrate "is not limited to the insulating substrate". For example, another insulating substrate such as an insulating substrate made of a Si02 substrate can be used. (3) In the sixth embodiment described above, the first gate % pole layer 120 is, for example, pt, but the present invention is not limited to the 颉Pt. For example, a quartz glass substrate, a Si〇2/Si based layer, an alumina (aluraina) (Al2〇3) substrate, an insulating substrate made of an SRO (SrRu(h) substrate or an sTO(SrTiO) substrate, or the like, may be used. a semiconductor substrate such as an s1 substrate or an S1C substrate. (4) In the sixth embodiment, the first gate electrode layer 120 uses, for example, Pt 'second gate electrode layer 16 〇, for example, A1 is used. The invention is not limited to the P t, A1. For example, Au, Ag, A1, Ti, I TO, In2 (h, Sb-Iru) may be used for the first gate electrode layer 120 or the second gate electrode layer 160. 〇3, Nb-Ti〇2, ZnO, Al-ZnO, lanthanum nickelate (LaNi〇3), Ga-ZnO '〇IGZO, Ru(h and Ir〇2, and Nb-STO 'SrRuCh, LaNi〇3, Bapb 〇3, LSCO, LSMO, YBCO and other perovskite type conducting oxides. Also, pyrochlore type conducting oxides and amorphous conductive tellurides can be used. (a) In the above-described first to sixth embodiments, the ferroelectric material used for the first gate insulating layer 132 is used, for example. PZT(Pb(Zrx, Ti^OO3), but the invention is not limited to the PZT (Pb(Zrx, 100132261 1003447808-0 69 201222827)

Ti ι-χ)〇3). For example, Nb-doped yttrium, La-doped yttrium, barium titanate (BaT i〇3), lead titanate (PbTiO〇, BTO(Bi4Ti3〇12), BLT (Bi4-) can be used. xLaxTi3〇12), SBT(SrBi2Ta2〇9), BZN(BiK5Zrii.〇.Nbi.5〇7) or bisinuth ferrite (Bi FeCh). (6) 'In the above embodiment--six In the case of the conductor layer 140, an oxide conductor composed of, for example, indium tin oxide (IT 0 ) is used, but the present invention is not limited to the oxide conductor composed of indium tin oxide (IT 0). For example, indium oxide (I nd i um ox i de ) (I n2〇3), antimony doped tin oxide (Sb-Sn〇2), zinc oxide (ZnO), Aluminum doped zinc oxide (Al-ZnO), gallium doped zinc oxide (Ga-ZnO), ruthenium oxide (Ru〇2), silver oxide (iridium) Oxide (Ir〇2), tin oxide (Sn〇2), tin monoxide (SnO), niobium doped titanium dioxide (Nb-Ti〇2), etc. Oxidation In addition, indium gallium zinc complex oxide (IGZ0), gallium doped indium oxide (In-Ga-O (IGO)), indium doped zinc oxide (indium doped) Zinc oxide) (amorphous conducting oxide) such as In-Zn-0 (IZ0), and strontium titanate (SrTi〇3), yttrium-doped titanate (niobium doped strontium titana1; e) (Nb-SrTi〇3), strontium barium complex oxide (SrBaOs) ' 鹤约复100132261 1003447808-0 70 201222827 strontium calcium complex oxide (SrCa〇3), strontium ruthenate (SrRu〇3), lanthanum nickelate (LaNi〇3), lanthanum ti tanate (LaT i Os), copper acid steel ( 1anthanum copper oxide) (LaCu〇3), neodymium nickelate (KNdNiOs), yttrium nickelate (YNi〇3), Lanthanum Calcium Manganese complex 0xide (LCM0), wrong acid Barium p 1 umbate (BaPb〇3), LSCOCLaxSn-xCuOs) LSMO (Lai-xSrxMn〇3), YBC0 (YBazCusOy-x), LNTO (La(NIi-xTix)〇3), LST0((Lai-x, Srx)Ti〇3), 'STRCKSrCTiHRuOOs), etc. A mineral conductive oxide or a pyrochlore type conductive oxide. (7) In the above-described first to sixth embodiments, the channel layer is a conductor layer made of an oxide conductor, but the present invention is not limited to the conductor layer. For example, a semiconductor layer composed of Si, Ge, SiC, SiGe, GaAs, GaP, GaN, ZnS, ZeSe, ZnO, CdS, CuInSe2 or the like can be used. (8) In the first embodiment, the second gate insulating layer i 5 is made of, for example, Si 02, but the present invention is not limited to the si 〇2. For example, SiOrAhOs'BZiKBiuZnuNbuCMLaAlOpHfOz or the like can also be used. Furthermore, (Bi2-X, Znx)(Znx, Nb2-x)〇7, Bix-Nbh-Oy, B i χ - Z r 1 - χ - 0 y, B i χ - H f 1 - x can also be used. - 0 y, B i X - T a 1 - x - 0 y, L a χ - T i 1 - χ - 0 y, L ax - Z ri - x - 0 y, L ax - H fi - x - 0 Y, L ax — T ai — x − 0 y, L a — — bi bi — x — y , etc. pyrochlore-type crystal or amorphous oxide (amorph〇us oxide), 100132261 1003447808-0 71 201222827 BST ((Bai-x, Srx) Ti〇3) Perovskite crystal or amorphous oxide such as STO (SrTi〇3), Six0y, AL2〇3, LaAHh, La2〇3, Zr〇2, Hf〇 2,

A crystalline or amorphous telluride such as Ta2〇s. (9) In the above-described fifth and sixth embodiments, the conductor layer for resistance reduction is formed in the upper layer or the lower layer of the connection layer, but the present invention is not limited thereto. For example, the conductor layer or the semiconductor layer constituting the connection layer may be made thicker than the conductor layer or the semiconductor layer constituting the first channel region or the second channel region. In this configuration, it is also possible to prevent a defective switching phenomenon in the portion of the connection layer located at a position overlapping the first word line or the second word line. Further, 〇 can also reduce the resistance of the conductor layer or the semiconductor layer constituting the connection layer. In this case, the conductor layer or the semiconductor layer constituting the connection layer can be made thicker than the conductor layer or the semiconductor layer constituting the first channel region or the second channel region by using an embossing technique or the like. (10), in the above-described first to fourth embodiments, the conductor layer or the semiconductor layer constituting the connection layer has the same thickness as the conductor layer or the semiconductor layer constituting the first channel region and the channel region. The invention is not limited thereto: for example, the conductor layer or the semiconductor layer constituting the connection layer may be thicker than the conductor layer or the semiconductor layer constituting the first via region and the second channel region. By such a configuration, the conductor layer or the semiconductor layer constituting the connection layer can also be made low in resistance. In this case, the conductor layer or the semiconductor layer constituting the connection layer can be made thicker than the conductor layer or the semiconductor layer constituting the first channel region and the second channel region by using an embossing technique or the like. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a graph for explaining the structure of each of the solid-state electronic components 100 to 100h in the first to ninth embodiments. Fig. 2 is a circuit diagram of a memory device 20 in accordance with the first embodiment. Fig. 3 is a view for explaining the display of the memory device 200 in accordance with the first embodiment. Fig. 4 is a view for explaining the display of the memory device 200 in accordance with the first embodiment. Fig. 5 is a view for explaining the information writing operation in the memory device 2 0 0 C.) according to the first embodiment. Fig. 6 is a view for explaining the information reading operation in the memory device 2000 according to the first embodiment. FIG. 7 is a view for explaining a driving waveform at the time of information writing in the memory device 200 according to the first embodiment. Fig. 8 is a view showing driving waveforms at the time of information reading in the memory device 20 0 according to the first embodiment. Fig. 9 is a view for explaining the display of the memory device 200a according to the second embodiment. Fig. 10 is a view for explaining the memory device 200a according to the second embodiment. Fig. 11 is a circuit diagram of a memory device 200b according to the third embodiment. Fig. 12 is a view for explaining the display of the memory device 200b according to the third embodiment. Fig. 13 is a view for explaining the memory device 100132261 1003447808-0 73 201222827 200b according to the third embodiment. Fig. 14 is a view for explaining the information writing operation in the memory device 2000b according to the third embodiment. Fig. 15 is a view for explaining the information reading operation in the memory device 2000b according to the third embodiment. Fig. 16 is a view for explaining a driving waveform at the time of information writing in the memory device 2000b according to the third embodiment. Fig. 17 is a view showing driving waveforms at the time of information reading in the memory device 2000b according to the third embodiment. Fig. 18 is a view for explaining the information writing operation in the memory device 200c according to the fourth embodiment. Fig. 19 is a view for explaining the information reading operation in the memory device 2000c according to the fourth embodiment. Fig. 20 is a view for explaining a driving waveform at the time of information writing in the memory device 2000c according to the fourth embodiment. Fig. 21 is a view showing driving waveforms at the time of reading information in the memory device 2000c according to the fourth embodiment. Fig. 2 is a view for explaining a method of manufacturing the memory device 2 0 0 b according to the third embodiment. Fig. 23 is a view for explaining another method of manufacturing the memory device 200b according to the third embodiment. Fig. 24 is a view for explaining another method of manufacturing the memory device 200b according to the third embodiment. Fig. 25 is a view for explaining another method of manufacturing the memory package 100132261 1003447808-0 74 201222827 200b according to the third embodiment. Fig. 26 is a view for explaining another method of manufacturing the memory device 2 0 0 b according to the third embodiment. Fig. 27 is a view for explaining another method of manufacturing the memory device 200b according to the third embodiment. Fig. 28 is a view for explaining the memory device 200d according to the fifth embodiment. Fig. 29 is a view for explaining the memory device 200d according to the fifth embodiment. Fig. 30 is a view for explaining the memory device 200e according to the sixth embodiment. Fig. 3 is a view for explaining the memory device 200e according to the sixth embodiment. Fig. 3 is a view for explaining a method of manufacturing the memory device 200d according to the fifth embodiment. Fig. 3 is a view for explaining another method of manufacturing the memory device set 50d according to the fifth embodiment. Fig. 34 is a view for explaining another method of manufacturing the memory device 200d according to the fifth embodiment. Fig. 35 is a view for explaining another method of manufacturing the memory device 200d according to the fifth embodiment. Fig. 36 is a view for explaining the memory device 200f according to the seventh embodiment. Fig. 37 is a view for explaining the memory device 100132261 1003447808-0 75 201222827 200f according to the seventh embodiment. Fig. 38 is a view for explaining the display of the memory device 200g according to the eighth embodiment. Fig. 39 is a view for explaining the memory device 200h according to the ninth embodiment. Figure 40 is a graph showing the results of the test examples. Fig. 41 is a view for explaining a conventional solid state electronic component 900. Fig. 4 is a view for explaining the switching operation in the conventional solid-state electronic component 900. Fig. 4 is a view for explaining the hysteresis characteristics of the gate insulating layer 930. Fig. 44 is a view showing how the information is written to the gate insulating layer 930. Fig. 45 is a view showing a state when information is read by the gate insulating layer 930. Fig. 46 is a view showing a problem of a case where a conventional solid-state electronic component 900 is used for a memory cell of a NAND-type memory device. Fig. 47 is a view showing a problem of a case where a conventional solid-state electronic component 900 is used for a memory cell of a NAND-type memory device. [Description of main component symbols] 100 to 100h: solid state electronic component 11 0 : solid substrate 120, 120a, 120b, 120c, 160, 160a, 160b, 160c: gate electrode layer 100132261 1003447808-0 76 201222827 1 20': strontium nickelate Precursor composition layer 1 2 2, 1 6 2 : first gate electrode 124, 164: second gate electrode 1 2 6 , 1 6 6 : third gate electrode 13 0, 150, 9 3 0 : gate insulating layer 1 31 : ferroelectric layer 132, 152: first gate insulating layer 134, 154: second gate insulating layer 〇 1 3 6 , 1 5 6 : third gate insulating layer 140: conductor layer 142: first channel region 144: Second channel region 146: third channel region 1 7 0 : metal layer 180 for resistance reduction: semiconductor substrate 1 8 2, 9 5 0 : source region Q 1 8 4 : source region / drain region 186, 960: The drain region 1 9 0 : the parasitic buffer layer 1 9 2 : the floating electrode 20 0 to 20 0h: the memory device 91 0 : the insulating substrate 9 2 0 : the gate electrode 9 4 0 : the channel layer 100132261 1003447808-0 77 201222827 BL : Bit line BSO : Block selection line D1 : First 汲 · Extreme D 2 : Second no extreme MO, M5, M6, M7 : Memory unit MB1, MB2, MB3 : Memory unit Block PL: plate line S1: first source terminal S 2 : second source terminal SW: block selection transistor TR1: first transistor TR2: second transistor TR3: third transistor + Vc, -Vc: correction Recalcitrant

Vcl: first bridge voltage V ο η : conduction state voltage

Vof f : off-state voltage soil Vw : write voltage WL0, WLi5, WL 〖6, WLi7: first word line WL2 〇, WL25, WL26, WL27: second word line 100132261 1003447808-0 78

Claims (1)

201222827 VII. Patent application scope: 1. A memory unit block' characterized by: a first transistor for information memory having the following components: a first channel region having a _ source terminal and a first 汲 extreme, and a first gate electrode for controlling an on state of the first channel region, and a first gate insulating layer formed of a ferroelectric layer formed between the first gate electrode and the first channel region; information reading having the following components a second transistor for outputting/writing: having a dipole-source terminal and a -> and an extreme brother-channel region, and a second gate electrode that controls the first _: (the conduction state of the ! channel region) a second gate insulating layer between the second dummy electrode and the second channel region, comprising: being connected to the first source terminal and the first source terminal at the first source terminal The first 汲 extreme is connected to the second, and the extreme, and the first gate electrode and the second gate electrode are respectively connected to another gate line, and the plurality of solid electronic components connected in parallel are composed of plural Memory list The plurality of memory cells are connected in series, wherein: the first channel region and the second channel region are formed by a conductor layer or a semiconductor layer formed by the same process, and adjacent to the plurality of memory cells Two memory cells are connected layers formed by a conductor layer or a semiconductor layer formed by the first channel region and the second channel region continuing in the two memory cells and formed in the same process as the channel regions The memory cell block of claim 1, wherein the first channel region and the second channel region and the connecting layer are composed of an oxide material 100132261 1003447808-0 201222827. The memory cell block of claim 1 or 2, wherein the gate electrode layer constituting the first gate electrode and the second gate electrode, and the first gate insulating layer and the second gate are formed The gate insulating layer of the insulating layer is formed of a liquid material together with the conductive layer or the semiconductor layer. 4. The memory cell block of claim 3, wherein the gate electrode layer And the insulating layer of the gate, and the conductor layer or the semiconductor layer are not formed by using a vacuum process. 5. The memory cell block according to any one of claims 1 to 4, wherein the first a gate electrode and a gate electrode layer of the second gate electrode, and a gate insulating layer constituting the first gate insulating layer and the second gate insulating layer, and the conductor layer or the semiconductor layer are both made of an oxide material. The memory cell block of claim 5, wherein the gate electrode layer and the gate insulating layer and the conductor layer or the semiconductor layer both have a perovskite structure. 7. Patent Application No. 1 to 6 The memory cell block of any one of the preceding claims, wherein the second gate insulating layer is formed by a ferroelectric layer in the same layer as the first gate insulating layer, the first transistor and the second transistor having: a gate electrode layer constituting the first gate electrode and the second gate electrode, and a gate insulating layer constituting the first gate insulating layer and the second gate insulating layer on one surface of the solid substrate a channel area and the second channel area and Configuration formed in this order connecting conductor layer or semiconductor layer. 8. The memory of any one of the first to sixth aspects of the patent application 100132261 1003447808-0 80 201222827 unit area i ghost, the layer of the first layer of the ferroelectric layer and the connecting layer and the first The second gate of the second gate 9' is like a block, which is the direction of the degree. 10, such as the polar layer in the body element block, the pole layer in the body substrate, and the insulating layer of the two-channel region, the formed structure 11, such as the pole layer in the body unit block substrate, and the insulation between the two channel regions Layer, formed structure 100132261, wherein the first gate insulating layer is formed by the first gate insulating layer, and the transistor and the second transistor have: the upper channel in the solid substrate constitutes the first channel region and The conductor layer or the semiconductor layer in the second channel region, the gate insulating layer constituting the first gate insulating layer insulating layer, and the structure in which the first gate electrode and the interlayer electrode layer are formed in this order. ^Please note that the memory unit area of the seventh or eighth aspect of the patent unit and the second transistor are arranged side by side in the memory of any one of items i to 6 of the channel width application patent. The first transistor and the second transistor have: a first gate electric gate insulating layer constituting the first gate electrode on a surface of the solid, and the first channel region and the first and the connecting layer a conductor layer or a semiconductor layer, and the second and second closed electrode layers constituting the second idle electrode are in this order from 1 to 6 6 W - the memory 2 of the first transistor and the second The transistor has: a second galvanic second insulating layer constituting the second interlayer electrode on a solid-side surface; and a conductor layer or a semiconductor layer constituting the first channel region and the first and the connection layer, And the first and the first electrode layer constituting the first electrode are in this order 〇1003447808-0 201222827 1 2. The memory unit block of claim 10 or 11 of the patent scope, wherein the The second gate insulating layer is composed of a paraelectric layer. 1 . The memory unit block of claim 10 or 11, wherein the second gate insulating layer is composed of a ferroelectric layer. The memory cell block of claim 1, wherein the second gate insulating layer is composed of a ferroelectric layer in the same layer as the first gate insulating layer, the first channel region and the first a second channel region is formed between a predetermined source region formed on a surface of the semiconductor substrate and a predetermined drain region, the first gate insulating layer is formed to cover the first channel region, and the second gate insulating layer covers the second region Forming a channel region, the first gate electrode is formed opposite to the first channel region via the first gate insulating layer, and the second gate electrode is opposite to the second channel region via the second gate insulating layer And formed. The memory cell block of claim 14, wherein the first channel region and the second channel region are formed between the first gate insulating layer and the second gate insulating layer. Paraelectric buffer layer. 1 . The memory unit block of claim 14 or claim 15, wherein a floating buffer layer is formed between the first gate insulating layer and the second gate insulating layer. Connect the electrodes. 17. A memory device, comprising: a bit line; a plate line; a first word line; a second word line; a plurality of memory sheets connected in series between the bit line and the board line 100132261 1003447808-0 82 201222827 memory cell block; and a memory cell array provided with a plurality of the memory cell blocks, the memory cell being connected to the first word line at the first gate electrode The second gate electrode is connected in parallel with the second word line, wherein the memory unit block includes the memory unit block of any one of claims 1 to 16. . 18. The memory device of claim 17, wherein the memory cell block is connected to the bit line or the plate line through at least one block selection transistor. 1 . The memory device of claim 17 or claim 18, wherein the memory unit block comprises the memory unit block of any one of claims 7 to 9. Among the connection layers, a conductor layer for resistance reduction is formed in an upper layer or a lower layer of the connection layer which is located at a position intersecting the first word line or the second word line. Q 2 0. The memory device of claim 17 or claim 18, wherein the memory unit block comprises the memory unit block of any one of claims 7 to 9. The conductor layer or the semiconductor layer constituting the connection layer is thicker than the conductor layer or the semiconductor layer constituting the first channel region or the second channel region. (2) The memory device of claim 17 or claim 18, wherein the memory unit block includes the memory unit block of any one of claims 10 to 13 of the patent application, 100132261 1003447808-0 83 201222827 The conductor layer or the semiconductor layer constituting the connection layer is thicker than the conductor layer or the semiconductor layer constituting the first channel region and the second channel region. 2 . A method of driving a memory device, comprising: using a memory device according to any one of claims 17 to 21, wherein the memory unit block includes a patent application scope 2 The memory device of the memory unit block according to any one of the items 5 to 5, wherein the predetermined memory unit (hereinafter referred to as a selection unit, and is also referred to as a memory unit of the same memory unit block as the selection unit) Writing a message to the memory cell other than the selected cell is a non-selecting cell, wherein the first state in the non-selected cell is caused by applying at least a second state word line Von connected to the non-selected cell The second transistor is turned on (0N), and by applying a second word line ground potential connected to the selection unit, applying a higher coercive voltage Vcl than the first gate insulating layer to the first word line connected to the selection unit a first write voltage (Vw: Vw &gt; Vcl) and a second write voltage ([-Vw]: [-Vw] &lt;- which is lower than a voltage (-Vcl) to which a negative sign is added to the coercive voltage Vcl. Any one of Vcl) Message:: Write action. A method of manufacturing a memory cell block, characterized in that: a method of manufacturing a memory cell block for fabricating a memory cell block comprising: a first device for information memory having the following components a crystal: a first channel region having a first source terminal and a first terminal, and a first gate electrode for controlling a conduction state of the first channel region, and a first gate electrode formed by the first gate electrode 100132261 1003447808-0 84 201222827 The ferroelectric layer between the first channel regions constitutes a first closed insulating layer for information read/write with the following components; the second source region of the second source terminal and the second drain region of the second drain terminal - transistor: having a channel a second electrode of the conductive state of the region, and a second gate insulating layer between the shape/control (four) second pole and the second channel region, wherein the second gate electrode comprises: the first transistor and the The second transistor is connected to the second source terminal, 嗲筮a. The first source must be connected to the terminal, and the first gate electrode and the second gate and the q/pole path are each connected to a gate line, and the solid state elements connected in parallel are connected. a plurality of memory cells, wherein the plurality of memory cells 70 are configured to be connected in series, wherein the two channel regions form the first channel region and the first channel by the same process of the memory cells Connecting two adjacent connection layers among the plurality of memory units. 2 4. The method of claim 2, wherein the first conductive region of the oxide conductive material and the connecting layer are used. The manufacturing of the memory cell block of the item forms the first channel region and the 25th method of the 23rd item of the patent application scope, the 戋 仏 仏 及 及 及 及In the middle of the wave type / '肀 hook using the liquid material to form the first gate and the fifth electrode of the second gate electrode" W% diameter increase constitutes the first gate insulation layer the second gate insulation Layer of gate insulating layer ' # the conductor layer or semiconductor Zhan. The manufacture of the memory cell block of the 25th patent circumstance No. 25 does not use a vacuum process to form the gate electrode layer, the gate insulating layer, and the conductor layer or the semiconductor layer. The method for manufacturing a memory cell block according to any one of claims 2 to 2, wherein an oxide material is used to form the first gate electrode and a gate electrode layer of the second gate electrode, and a gate insulating layer constituting the first gate insulating layer and the second gate insulating layer, and the conductor layer or the semiconductor layer. 100132261 1003447808-0 86