JP2000340759A - Nonvolatile semiconductor memory and drive method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an NAND type nonvolatile semiconductor memory of high integration, high-speed, and low power consumption and moreover having little disturbance. SOLUTION: A memory cell comprises a dual gate transistor, where a ferroelectric is connected to one gate part, a plurality of the memory cells are connected in series to constitute a memory block, and a plurality of memory blocks are arranged to form a memory cell array. The dual gate transistor uses a thin-film transistor, wherein first gate electrodes Wf1, Wf2, and Wf3 are provided on one surface of a semiconductor thin film 1 via a first gate insulating film 2 and a ferroelectric thin-film 3, while second gate electrodes Wd1, Wd2, and Wd3 are provided counterposed to face the first gate electrodes Wf1, Wf2, and Wf3 on the other surface of the semiconductor thin-film 1 via a second gate insulating film 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory using a ferroelectric and a method of driving the same.

[0002]

2. Description of the Related Art A ferroelectric memory is a non-volatile memory capable of high-speed rewriting utilizing high-speed polarization reversal of a ferroelectric thin film and its residual polarization. This ferroelectric memory is of a type using a ferroelectric capacitor (FeRAM).
Type) and a type (ferroelectric gate type) in which a ferroelectric is connected to the gate portion of a transistor. Among them, the ferroelectric gate type is excellent in terms of cell area and nondestructive readout. As this ferroelectric gate type nonvolatile memory, MFS (Metal-Ferroelectrics-Semiconductor)
Type, MFIS (Metal-Ferroelectrics-Insulator-Semic
onductor) type and MFMIS (Metal-Ferroelectrics)
-Metal-Insulator-Semiconductor) type is known.

As described above, the ferroelectric gate type nonvolatile memory has the advantage of being excellent in cell area and non-destructive readout.
Since the transistor type is driven by a simple matrix,
When the ferroelectric of the selected memory cell is polarized, there is a problem of disturbance that the ferroelectric of the unselected memory cell is affected. That is, FIG. 13 shows a part of a memory cell array of a one-transistor ferroelectric gate nonvolatile memory. MC11 ', MC12', MC21
, MC22 'are memory cells composed of ferroelectric gate type transistors, B1a', B1b ', B2a
And B2b 'indicate bit lines, and W1' and W2 'indicate word lines. In this example, since simple matrix writing is performed, the gate of the ferroelectric gate type transistor has −V _w
/ 3 (where, V _w the voltage required for the polarization inversion of the ferroelectric) disturb voltage is applied to every write to other memory cells. In this case, data can be written at a lower voltage and in a shorter time as compared with a flash memory in which electric charges are injected into a floating gate, but this causes a weakness in disturb. Furthermore, in order to suppress the disturb voltage -V _w / 3, it is necessary to transistors of non-selected memory cell is also made conductive to form a channel. For this reason, the fluctuation width of the threshold voltage due to the ferroelectric material is greatly restricted, and the range of characteristics required for the ferroelectric material is narrow. Further, since wiring connection to the source region and the drain region is required for each transistor of the memory cell, the cell area is increased as compared with the NAND type, and at the same time, fine processing of the ferroelectric is required, and the ferroelectric characteristics are increased. And it becomes difficult to use a ferroelectric material which is difficult to dry-etch such as reactive ion etching (RIE) such as SBT.

The above-mentioned disturb problem can be solved by adding a selection transistor to the memory cell. However, in this case, the cell area becomes large, so that high integration becomes difficult. Newly arise.

On the other hand, a flash memory is known as a nonvolatile memory. In a flash memory, information is stored by injecting and extracting electrons from and to a floating gate. In this flash memory, the injection of electrons requires a larger voltage and takes longer time than the polarization inversion of the ferroelectric, but this reduces the disturb problem. In this flash memory, a NAND type in which a plurality of transistors are arranged in series has been developed as a method in which a cell area is small and high integration is possible.

[0006]

Since the basic structure of a ferroelectric gate type nonvolatile memory is similar to that of a flash memory, the cell area is expected to be small when a NAND type is adopted. As described above, there is a problem of disturbance, and the transistor is turned on / off without inverting the polarization.
Since it is difficult to turn off the gate voltage and the fluctuation direction of the gate voltage and the threshold voltage of the transistor is opposite to that of the flash memory, the NAND type cell arrangement in the ferroelectric gate type nonvolatile memory has been It was difficult.

Japanese Patent Application Laid-Open Nos. 5-136377 and 5-136378 propose NAND-type nonvolatile semiconductor memories. However, these NAND-type nonvolatile semiconductor memories have extremely complicated structures and are difficult to realize. it is conceivable that.

Accordingly, an object of the present invention is to provide a highly integrated
NAN with high speed, low power consumption and little disturbance
An object of the present invention is to provide a nonvolatile semiconductor memory capable of realizing a D-type nonvolatile semiconductor memory and a driving method thereof.

[0009]

In order to achieve the above object, a nonvolatile semiconductor memory according to a first aspect of the present invention has a memory cell comprising a dual gate transistor having one gate connected to a ferroelectric. And a plurality of the memory cells are connected in series to form a memory block, and a plurality of the memory blocks are arranged to form a memory cell array.

In the first aspect of the present invention, typically, a plurality of memory cells are connected in series, and a select transistor is connected to at least one end of the series connection to form a memory block. The number of memory cells that constitute a memory block is basically arbitrary, and the higher the number of memory cells, the higher the integration.However, the path through which current flows through the transistors of the memory cells becomes longer, and a voltage drop occurs. The optimal number is selected according to the use of the nonvolatile semiconductor memory. Also, one end of the memory block
Typically, it is connected to a bit line via a selection transistor. The dual gate transistor forming the memory cell is typically a thin film transistor. More specifically, in this dual-gate transistor, for example, a first gate electrode is provided on one surface of a semiconductor thin film via a first gate insulating film and a ferroelectric thin film,
A thin film transistor in which a second gate electrode is provided on the other surface of the semiconductor thin film with a second gate insulating film interposed therebetween so as to face the first gate electrode. In this case, the dual gate transistor forming the memory cell is switched by changing the voltage of the second gate electrode. The ferroelectric thin film is provided as a continuous film over at least a plurality of memory cells, typically over the entire memory cell array.

According to a second aspect of the present invention, a memory cell is formed by a dual gate transistor having one gate connected to a ferroelectric, and a plurality of memory cells are connected in series to form a memory block. A memory cell array is formed by arranging a plurality of the memory blocks, and a dual gate transistor forming the memory cell is formed on one surface of the semiconductor thin film via a first gate insulating film and a ferroelectric thin film. A non-volatile semiconductor memory in which a first gate electrode is provided, and a second gate electrode is provided on the other surface of the semiconductor thin film via a second gate insulating film so as to face the first gate electrode; In the driving method, the direction of polarization of the ferroelectric thin film is aligned during erasing, and the selection transistor connected to the bit line during writing. Therefore, the dual gate transistors forming the plurality of memory cells connected in series in the selected memory block are made conductive by the second gate electrode, and the memory cell at the intersection of the memory block and the selected word line is formed. Data is written by inverting the polarization of the ferroelectric connected to the gate part of the dual gate transistor, and at the time of reading,
The dual gate transistors constituting the memory cells other than the selected memory cell of the memory block selected by the selection transistor connected to the bit line are made conductive by the second gate electrode, and the value of the bit line current at that time is expressed as Data is read by reading a polarization direction of a ferroelectric substance connected to a gate portion of a dual gate transistor constituting a selected memory cell.

It should be noted that JP-A-7-161854, JP-A-8-335645 and JP-A-7-1834.
Japanese Patent Application Publication No. 01-301, proposes a ferroelectric gate type dual-gate thin film transistor in which gate electrodes are provided on both surfaces of a semiconductor thin film and at least one of these gate electrodes is connected to a ferroelectric substance. It is not intended to be applied to non-volatile memories. Japanese Patent Application Laid-Open No. 10-12887 discloses an example in which a ferroelectric substance is used for applying a bias to a dual gate transistor. However, this ferroelectric substance is not used for holding data but for applying a bias. This is basically different from the present invention.

In the present invention configured as described above, since the memory cell is constituted by a dual gate transistor having one gate connected to a ferroelectric, the gate voltage applied to the other gate electrode is changed. This makes it possible to turn on / off the transistor without changing the polarization direction of the ferroelectric. Therefore, the disturbance can be suppressed, and the N of the memory cell can be reduced.
An AND type array becomes possible. In this NAND type array,
Since it is not necessary to make a wiring contact with the source region / drain region for each memory cell, no wiring space is required, and the cell area can be reduced. Further, the polarization inversion of the ferroelectric is fast, and the voltage required for the polarization inversion is considerably lower than the voltage required for injecting electrons into the floating gate in the flash memory.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

FIG. 1 shows an NA according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of a memory cell array of the ND type nonvolatile semiconductor memory.

As shown in FIG. 1, in the NAND type nonvolatile semiconductor memory according to this embodiment, a memory cell constituted by a ferroelectric gate type dual gate thin film transistor having a ferroelectric material connected to one gate portion. Are connected in series to form a memory block, and k memory blocks are arranged to form a memory cell array. MCij (where i = 1 to k, j =
1 to n) indicate memory cells forming the i-th memory block. One end of the i-th memory block is connected to a common source line S via a selection transistor STi1,
The other end is connected to the bit line Bi via the selection transistor STi2.
Is connected to Select transistors STi1, STi
Reference numeral 2 is not a ferroelectric gate type dual gate thin film transistor, but a thin film transistor having a normal single gate electrode.

The upper gate electrode on the ferroelectric side of the ferroelectric gate type dual gate thin film transistor constituting the memory cell MCij at the corresponding stage of all the memory blocks, and the lower gate electrode facing the upper gate electrode are:
Each is constituted by word lines Wfj and Wdj. Also, the selection transistors S of all the memory blocks
The gate electrode of Ti1 is constituted by a common selection line WS1, and the gate electrode of the selection transistor STi2 is constituted by a common selection line WS2.

Next, a specific example of the structure of the NAND nonvolatile semiconductor memory according to the embodiment will be described.

FIG. 2 is a plan view showing a part of the memory cell array, FIG. 3 is a sectional view taken along the line III-III of FIG.
FIG. 4 is a sectional view taken along the line IV-IV of FIG. 2, and FIG. 5 is a sectional view taken along the line VV of FIG.

As shown in FIGS. 2, 3, 4 and 5, a word line Wfj is provided on one surface of a semiconductor thin film 1 with a gate insulating film 2 and a ferroelectric thin film 3 interposed therebetween. A word line Wdj is provided on the other surface of the semiconductor device 1 via a gate insulating film 4 so as to face the word line Wfj. Semiconductor thin film 1 in a portion between adjacent word lines Wfj
Is provided with an n ⁺ -type region 5 constituting a source region / drain region of a ferroelectric gate type dual gate thin film transistor. The portion of the semiconductor thin film 1 other than the n ⁺ type region 5 is p type, and the word lines Wfj,
The p-type region sandwiched between Wdj forms a channel region.

The semiconductor thin film 1 is, for example, a polycrystalline Si thin film. The gate insulating films 2 and 4 are made of, for example, SiO ₂ , Si
It is made of an insulator such as N, CeO ₂ , Al ₂ O ₃ , and Ta ₂ O ₅ . These gate insulating films 2 and 4 are provided continuously over the entire surface of one side and the other side of the semiconductor thin film 1, respectively. The ferroelectric thin film 3 is, for example, SB
It is made of a ferroelectric such as T or PZT. The ferroelectric thin film 3 is provided continuously over the entire memory cell array. The word lines Wfi and Wdi are made of, for example, polycrystalline Si, Ta, W, or the like.

In one example of the NAND type nonvolatile semiconductor memory according to this embodiment, the gate insulating films 2 and 4 are made of a SiO ₂ film having a thickness of 6 nm, and the ferroelectric thin film 3 is made of an SBT film having a thickness of 60 nm. Become. This SBT has a coercive electric field E
_c is 6 × 10 ⁴ V / cm, the residual polarization P _r is 7 .mu.C / cm
^{2. The} dielectric constant is 200. Further, the ferroelectric coercive voltage V
_c is 0.36 V, ferroelectric inversion voltage 2 V _c is 0.72
V and the cell inversion voltage is 4.4V. The variation width of the threshold voltage _Vth of the ferroelectric gate type dual gate thin film transistor is ± 2.4 V.

Next, an example of a method of manufacturing the NAND-type nonvolatile semiconductor memory according to this embodiment having the above-described structure is a cross-sectional view corresponding to the cross-sectional view shown in FIG.
This will be described with reference to FIGS.

First, as shown in FIG. 6, after polycrystalline Si, Ta, W, etc. are formed on the support substrate 6, this film is patterned into a predetermined shape by etching to form the word line Wd.
form j.

Next, as shown in FIG.
The recesses between them are filled with a flattening film 7 to flatten the surface.

Next, as shown in FIG. 8, SiO ₂ , SiN, CeO ₂ , Al
_A gate insulating film 4 made of ₂ O ₃ or the like is formed.

Next, as shown in FIG.
A semiconductor thin film 1 is formed thereon.

Next, as shown in FIG.
Then, n-type impurities are selectively ion-implanted using, for example, a resist pattern (not shown) as a mask to form an n ⁺ -type region 5.

Next, as shown in FIG.
After the gate insulating film 2 and the ferroelectric thin film 3 are sequentially formed thereon, the ferroelectric thin film 3 in a portion other than the memory cell array portion is formed.
Is removed by etching. Next, in the same manner as the word line Wdj, a word line Wfj is formed on the ferroelectric thin film 3 in the memory cell array portion, and a select line WS is formed on the gate insulating film 2 in a portion other than the memory cell array portion.
1. WS2 is formed.

Thereafter, the support substrate 6 and the flattening film 7 are removed. Thereby, as shown in FIG. 2, FIG. 3, FIG. 4, and FIG. 5, the intended NAND nonvolatile semiconductor memory is manufactured.

Next, a method for erasing, writing, and reading the NAND nonvolatile semiconductor memory according to the embodiment will be described.

First, erasing is performed not for each memory cell but for each memory block. The voltage required for the polarization reversal of the ferroelectric is defined as V _w (for example, 4.4 V). To do erased, applying a -V _w to the word line Wf1~Wfn.
The word lines Wd1 to Wdn and the selection lines WS1 and WS2 are all set to 0V. As a result, the ferroelectrics of all the memory cells in the memory block all have the same polarization direction,
The threshold voltage of the transistor constituting the memory cell rises to V _th E as shown in FIG. This state is defined as data “0”.

Writing is performed in order from the word line Wf1 to the word line Wfn in the memory block. Further, the memory cells connected to the same word line perform writing simultaneously.

As an example, consider a case where data "1" is written to memory cell MC11 and data "0" is written to memory cell MCk1. In this case, the selection line WS1 is set to 0 V to turn off the selection transistor STi1, and a voltage higher than the threshold voltage is applied to the selection line WS2 to turn on the selection transistor STi2. Further, the memory cell M
Bit line B1 connected to the memory block including C11
It is a 0V, the bit line Bk connected to the memory block including a memory cell MCk1 applying a V _w. on the other hand,
A voltage V _th E required to turn on the transistors forming the memory cells is applied to all of the word lines Wd1 to Wdn. Then, applying a V _w to the word line Wf1 the memory cell MC11, MCk1 are connected. Thereby, in the memory cell MC11, this memory cell MC11
When the channel region of the transistor constituting the transistor becomes 0 V, polarization inversion of the ferroelectric substance occurs, and the threshold voltage of the transistor _drops to V _th W as shown in FIG. 12A, and data “1” is written. . On the other hand, the memory cell MCk
In 1, since V _w is applied to both the channel region of the transistors constituting the word lines Wf1 and the memory cell MCk1, polarization inversion does not occur in the ferroelectric field in the vertical direction is canceled, the data "0 Is held. In this way, data is simultaneously written to all the memory cells connected to the word line Wf1.

Next, data "0" is stored in the memory cell MC12.
For writing data “1” to the memory cell MCk2. Also in this case, the selection line WS1 is set to 0 V to turn off the selection transistor STi1, and the selection line W1
S2 is set to be higher than the threshold voltage and the selection transistor STi
2 is turned on. A voltage V _th E required to turn on the transistors is applied to all of the selection lines Wd2 to Wdn. At this time, in order not to apply an inversion voltage to the memory cell on the word line Wf1 to which writing has been performed previously, V _th W as shown in FIG. The transistor forming the cell is turned off. As a result, the bit line voltage becomes the word line Wf1
No data is applied to the upper memory cell, and the previously written data is retained. The V _w is applied to the bit line B1, the bit line Bk is a 0V. And, applying a V _w to the word line Wf2. As a result, in the memory cell MCk2, polarization inversion of the ferroelectric substance occurs, and data "1" is written. On the other hand, in the memory cell MC12,
Since _Vw is also applied to the channel region of the transistor constituting the transistor, the electric field in the vertical direction is canceled out, and the polarization inversion of the ferroelectric does not occur, and the data "0" is retained. In this way, data is simultaneously written to all the memory cells connected to the word line Wf2.

In the same manner, writing is performed for each word line up to the word line Wfn while turning off the transistor of the memory cell to which writing has been performed previously so that the data does not change.

By performing writing as described above, it is possible to perform writing that is not random writing but has little disturbance.

When writing to another memory block, the selection transistor STi2 is turned off to completely prevent disturbance.

Reading is performed as follows. For example,
When reading data from the memory cell connected to the bit line B1, a voltage higher than the threshold voltage is applied to the selection lines WS1 and WS2 to turn on the selection transistors ST11 and ST12. First, when reading data of the memory cell MC11 is to apply the V _th E to turn on the transistor constituting the memory cell MC1j (j = 2~n) to the word line Wd2～Wdn. Then, a predetermined read voltage is applied to the bit line B1, and a current between the source and the drain, that is, a current flowing through the bit line B1 is checked. When a current flows, the data of the memory cell MC11 is “1”. When no current flows, the data of the memory cell MC11 is “0”.

Next, when reading data from the memory cell MC12, V _th is applied to the word lines Wd1, Wd3 to Wdn.
E is applied to the memory cells MC11 and MC1j (j = 3 to
The transistor constituting n) is turned on. Then, a predetermined read voltage is applied to the bit line B1, and a current between the source and the drain, that is, a current flowing through the bit line B1 is checked. When a current flows, the data of the memory cell MC12 is “1”, and when no current flows, the memory cell MC12
The data of C12 is “0”.

Thereafter, data of each memory cell can be read out in the same manner. Thus, random access is possible at the time of reading.

As described above, according to this embodiment,
A memory cell is formed by a ferroelectric gate type dual gate thin film transistor, a plurality of the memory cells are connected in series to form a memory block, and a plurality of the memory blocks are arranged. It is possible to realize a NAND nonvolatile semiconductor memory which consumes less power and has less disturbance problem which is a drawback of the ferroelectric gate nonvolatile memory. Further, since it is not necessary to finely process the ferroelectric thin film 3 for each memory cell, the characteristics of the ferroelectric thin film 3 are not deteriorated, and the manufacture of the NAND nonvolatile semiconductor memory is easy.

As described above, one embodiment of the present invention has been specifically described. However, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. .

For example, the numerical values given in the above-described embodiment,
The structures, shapes, materials, processes, and the like are merely examples, and different numerical values, structures, shapes, materials, processes, and the like can be used as needed.

For example, in the above-described embodiment, the gate insulating film 2 is provided on the semiconductor thin film 1 and the ferroelectric thin film 3 is provided thereon. The dielectric thin film 3 may be provided, and the gate insulating film 2 may be provided thereon.

Also, the NAN described in the above-described embodiment is used.
The method of manufacturing the D-type nonvolatile semiconductor memory is only an example,
A different manufacturing method may be used.

[0047]

As described above, according to the present invention, a memory cell is constituted by a dual-gate transistor having one gate connected to a ferroelectric, and a plurality of memory cells are connected in series to form a memory. A block is formed, and a plurality of the memory blocks are arranged to form a memory cell array. Therefore, a NAND having high integration, high speed, low power consumption, and little disturbance is provided.
Type nonvolatile semiconductor memory can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a NAND nonvolatile semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a plan view showing a structural example of a part of a memory cell array of a NAND nonvolatile semiconductor memory according to one embodiment of the present invention;

FIG. 3 is a sectional view taken along the line III-III in FIG. 2;

FIG. 4 is a sectional view taken along the line IV-IV in FIG. 2;

FIG. 5 is a sectional view taken along the line VV in FIG. 2;

FIG. 6 is a cross-sectional view for explaining an example of a method for manufacturing a NAND nonvolatile semiconductor memory according to one embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining an example of a method for manufacturing a NAND nonvolatile semiconductor memory according to one embodiment of the present invention.

FIG. 8 is a cross-sectional view for explaining an example of a method for manufacturing a NAND nonvolatile semiconductor memory according to one embodiment of the present invention.

FIG. 9 is a cross-sectional view for explaining an example of a method for manufacturing a NAND nonvolatile semiconductor memory according to one embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining an example of a method for manufacturing a NAND nonvolatile semiconductor memory according to one embodiment of the present invention.

FIG. 11 is a cross-sectional view for explaining an example of the method for manufacturing the NAND nonvolatile semiconductor memory according to the embodiment of the present invention.

FIG. 12 is a schematic line for explaining an operation method of the NAND-type nonvolatile semiconductor memory according to the embodiment of the present invention;

FIG. 13 is a circuit diagram showing a one-transistor ferroelectric gate nonvolatile memory.

[Explanation of symbols]

MC11 to MC1n, MCk1 to MCkn ... memory cells, ST11, ST12, STk1, STk2 ...
Selection transistors, Wf1 to Wfn, Wd1 to Wdn.
..Word lines, WS1, WS2... Select lines, B1 to B
k ... bit line, 1 ... semiconductor thin film, 2, 4 ...
Gate insulating film, 3 ... ferroelectric thin film, 5 ... n ⁺ type region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/788 H01L 29/78 371 29/792 F term (Reference) 5B025 AA07 AC01 AD03 AE00 AE05 AE06 AE08 5F001 AA17 AB02 AB20 AD12 AD20 AD41 AD51 AD52 AD53 AD70 AE02 AE08 AF10 5F083 EP22 EP28 EP33 EP34 EP49 EP76 FR06 FR10 GA01 GA05 GA09 GA11 GA30 HA02 JA02 JA06 JA14 JA15 JA17 JA19 JA39 KA01 LA16

Claims (8)

[Claims] 1. A memory cell is constituted by a dual gate transistor having a ferroelectric material connected to one gate portion, and a plurality of memory cells are connected in series to constitute a memory block. A non-volatile semiconductor memory, wherein a memory cell array is formed. 2. The non-volatile memory according to claim 1, wherein a plurality of said memory cells are connected in series, and a selection transistor is connected to at least one end of said series connection portion to form a memory block. Semiconductor memory. 3. The nonvolatile semiconductor memory according to claim 1, wherein one end of said memory block is connected to a bit line. 4. The nonvolatile semiconductor memory according to claim 1, wherein said dual gate transistor is a thin film transistor. 5. The dual gate transistor according to claim 1, wherein a first gate electrode is provided on one surface of the semiconductor thin film via a first gate insulating film and a ferroelectric thin film, and the other surface of the semiconductor thin film is provided on the other surface. 2. The nonvolatile semiconductor memory according to claim 1, wherein a second gate electrode is a thin film transistor provided so as to face the first gate electrode via a second gate insulating film. 6. The nonvolatile semiconductor memory according to claim 1, wherein said dual gate transistor forming said memory cell is switched by changing a voltage of said second gate electrode. 7. The nonvolatile semiconductor memory according to claim 1, wherein said ferroelectric thin film is provided in a continuous film form over at least a plurality of said memory cells. 8. A memory cell is constituted by a dual gate transistor in which a ferroelectric substance is connected to one gate portion, and a plurality of memory cells are connected in series to constitute a memory block, and a plurality of memory blocks are arranged. The dual gate transistor constituting the memory cell is provided with a first gate electrode on one surface of a semiconductor thin film via a first gate insulating film and a ferroelectric thin film. A method for driving a non-volatile semiconductor memory, which is a thin film transistor in which a second gate electrode is provided on the other surface of the semiconductor thin film via a second gate insulating film so as to face the first gate electrode. During erasing, the polarization direction of the ferroelectric thin film is aligned, and during writing, the select transistor connected to the bit line is used. The dual gate transistors constituting the plurality of memory cells connected in series in the selected memory block are turned on by the second gate electrode, and the memory at the intersection of the memory block and a selected word line is selected. The data is written by inverting the polarization of the ferroelectric connected to the gate portion of the dual gate transistor constituting the cell, and at the time of reading, the memory block selected by the selection transistor connected to the bit line is selected. The above-mentioned dual gate transistor constituting a memory cell other than the memory cell made conductive by the second gate electrode,
Reading data by reading a polarization direction of a ferroelectric substance connected to a gate portion of the dual gate transistor constituting the selected memory cell from a value of the bit line current at that time; For driving a volatile semiconductor memory.