TW201208022A - Flip chip package assembly and process for making same - Google Patents
Flip chip package assembly and process for making same Download PDFInfo
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- TW201208022A TW201208022A TW100105363A TW100105363A TW201208022A TW 201208022 A TW201208022 A TW 201208022A TW 100105363 A TW100105363 A TW 100105363A TW 100105363 A TW100105363 A TW 100105363A TW 201208022 A TW201208022 A TW 201208022A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
201208022 六、發明說明: 【發明所屬之技術領域】 本發明係有關於封裝裝置,且特別是有關於一種具 有較佳的熱效能之封裝裝置及其製造方法。 【先前技術】 現今對於先進電路的一般性需求,且特別是對於在 半導體製程中製造的積體電路(IC),係為使用基材或 轉接板,以安裝於終端上具有凸塊或用於積體體電路連 接之“覆晶,,積體電路。在覆晶封裝t,焊料凸塊包括含 鉛或無鉛的焊料組成物,其設置於積體電路上並朝下面 對基材,以及使用熱回焊製程來完成焊料連接。這些 體電路裝置可具有數十或數百個輸人或輸出終端,^以 接收或送出訊號及/或用以連接至電源供應器。 在覆晶封裝的應时,積體f路設置於朝下面對 ipped)所對應之基材。積體電路係 ,材。基材具有-芯部(―,其鑛有自晶= We)延伸至電路板側之貫穿孔連接。 同時在上側及下财多層金屬連線。介電層可 it物I:包含聚亞醯胺、有機物、無機物、樹脂、 %軋化物及其類似物。 曰 設置於基材之晶片側之導電凸塊塾 (:—s),,。這些凸塊塾與位在導塾= 材料(P㈣此峽灿)電性連接。預焊材料 形成於阻焊材财的開口中,這些區域稱為防烊又開:
0503-A35492TWF/JEFF S 201208022 (solder resist openings,SR0s )。自基材之晶片側上的 夕層金屬圖案穿過芯部至基材之電路板側,形成連線。 每些連線可由例如填入導電插塞至電鍍之貫穿孔中形 成。基材之金屬層可使用鍍銅技術形成,可無電電鍍晶 種層至基材之額外的堆疊層或其他介電層上。 …覆晶積體電路可面朝下的設置,並使積體電路上之 焊料凸塊或焊條沿著所對應之凸塊墊對齊’以使焊料及 預焊材料相接觸。使用熱回焊來進行晶片連接製程,融
解烊料及預知材料並接著讓其冷卻。在回焊時,焊料及 預焊材料在積體電路晶片及基材之間形成電性及機械連 接。 在晶片連接之後,於積體電路底下塗佈(dispense) 底部填充材料。在習知技術中,底部填充材料係與積體 電路、焊料凸塊及阻焊材料之表面接觸。 如本領域所熟知,熱失配(thermal响邮灿)通常 發生在積體電路封裝中之不同材料之間。例如,孰失配 會在積體電路、半導體及基材之間發生。材料具有、不同 (coefficient of thermal expansion > GTE) ==操作裝置及材料溫度變化日铸致機械應力。通 书’底。卩填充材料係為在熱回焊製程後 及基材之間。通常,會選擇能釋放機械應力之 力對裝置造成損傷。選用底部填充材料,能在 熱應力發生時幫助保護晶片及 壞(例如凸塊破裂等)的可紐。I以少機械破 儘管如此,熱致機械應力依舊存在於f知的覆晶封
0503-A35492TWF/JEFF 201208022 裝積體電路中’例如可觀察到凸塊破料、鄰近凸塊間的 橋接短路及在底部填充材料及介電層中(脫層)的破裂 等知壞。底部填充材料與基材上之阻焊材料仍具有實質 上不同的熱膨脹係數性f,以使熱膨脹係數的失配仍舊 存在。因此’在習知技術中,就算使用底部填充材料仍 會有熱損壞發生。 【發明内容】 本發明之一實施例提供一種封裝裝置,包括:一封 ,基材’包含·-介電層’位於該基材之—晶片侧表面; 複數個導電藝,形成於該介電層之表面;及—阻焊層, 設置於該導電塾及該介電層上,其中該阻焊材料包含複 =第-開口及複數個第二開口,該些第一開口暴露該 t電墊’該些第二開口暴露介於該些導電塾之間的該 介電層的表面’該些第二開σ與該些導㈣具有至少1〇 微米之間距。 、本發明之另-實施例亦提供—種封裝裝置之製造方 包括:形成—介電層於—封裝基材之—晶片側表面, 其中該介電層之表面上具有複數個導電凸塊墊與該介電 層中之金屬導電層連接;以—阻焊材料覆蓋該介電層及 該些導電凸塊墊;依照該些導電凸㈣在該阻焊材料中 形=,個第-開口;以及在該些導電凸塊塾之間形成 二開口,該些第二開口延伸穿越該阻焊材料且 •j、路該"電層之表面。 本發明之又一實施例更提供一種封裝裝置,包括:
0503-A35492TWF/JEFF 6 201208022 一封裝基材,包含.—八^ 侧上,·複數個導電墊,=二立於-基材之芯部之兩 積體電路曰片 :該介電層之表面;至少一 電路日日片,黏著㈣ / 於該些導電藝及該介電層上上,阻知層,設置 置於至少一積體電 ,及一底部填充材料,設 包含暴露該該阻焊層 二Π之表㈣ 第一開口中之該介雷 T/、成一
^ a 冤層之表面相接觸,該些第二開口盥 該些導電塾具有至少1G微米之間距。 ” 為讓本發明之上述和其他目的、特徵、和優 :;易懂,下文特舉出較佳實施例,並配合所附圖式, 作詳細說明如下: Λ 【實施方式】 本發明接下來將會提供許多不同的實施例以實施本 發明中不同的特徵。,然而,這些實施例並非用於限定本 發明。以下所討論之特定實施例僅用於舉例本發明實施 例之製造及使用,但不限定本發明之範疇。 在此,將詳細描述本發明實施例,提供新穎的方法 及裝置來減少積體電路封裝中的熱應力。基材係用於設 置具有焊料凸塊之覆晶積體電路。防焊開口暴露出一部 分之基材介電層,以使底部填充材料與基材介電層物理 接觸。相較於先前的封裝體結構,藉由減少熱循環中的 機械應力增進整個封裝體的熱效能。 在第1圖中’顯示為本發明一實施例之剖面圖。首 0503^A35492TWF/JEFF 7 201208022 先,提供基材π。基材u可具有貫穿孔25之芯部19形 成貝穿孔25鑛有例如銅及其合金、或鍍有其他導電金 屬及其合金的導體。貫穿孔25中係填有導電插塞或填充 材料21。介電層16可為額外的堆積層或其他絕緣體,在 圖中其顯示為覆蓋芯部19的兩側。多層金屬層18為例 如形成在水平及垂直方向之導電通路。阻焊材料15位於 電路板之兩側,圍繞球焊盤(balllandS)24。球焊盤(ball lands)24位在晶片側上(第1圖中基材之上側),係設 計用於承接焊球以製造封裝積體電路至外部之電性連 接。凸塊墊17位於介電層16之上部或晶片側表面,並 由具有防焊開 π ( s〇lder resist 〇penings,SR〇s )於其中 之阻焊材料15所覆蓋。在阻焊材料15中,係填有預焊 材料27。 一=焊開口 33形成於第1圖之基材11之晶片侧上。 在/實施例中’在阻谭材料15上進行雷射鑽孔製程步驟 ^成防焊開口 33。在此實施例中,此步驟可在於凸塊 π上&置預焊材料27之後進行。在任何情況下,阻 f材料15現在被圖案化為阻焊環(solder mask rings, MR) 3卜其為中心在凸塊墊17上之孔環。防焊開口 % =於凸塊墊之間,並暴露出介電層之上部表面。阻焊 m在於凸塊墊17上設置預焊材料27之後,使用額 外的雷射鑽孔圖案化步驟完成。 ㈣本!明另一實施例中’係為在於凸塊墊上設置預焊 ;:月'以微衫製卷步驟同時定義阻焊環3】及防谭開 口㈣成如第1圖所示之轉環及防焊開口 ^匕實施
S
〇503-A35492TWF/JEFF 201208022 例中,可以微影技術進行 防焊開口 33。在此方法中,義阻焊環31及 ^ 0 ^ , 。又置預知材至凸塊墊17上 之則,係已完成對於阻焊材料15 防焊結構可由微影製程形成,且接= 二丄此方法中, ,P,J (stencupnnung) J5 t ^ ,31或防知開口 33之目的在於使底部填充材料塗佈 於積體電路晶片底下,積體電路晶片可設置在基材^上
ί與介電層物理接觸。此種新穎性的特徵減低了本發明 貫施例所提供之封裝體中的熱機械應力,如以下所詳述。
第1圖所示之距離D,係為阻焊環31之延伸的水平 厚度’且其可變化。在第—實施例中,此距㈣可為銅 凸塊墊17之外部邊緣録焊環31邊緣的輯,並且有 ,10 μη!之最小距離。半導體製程節點、積體電路上終 端的數量、及凸塊塾17之直徑將隨特定應用而變化,並 可具有不同的合適延伸距離D。距離D雖可變化,然而, 較佳為使用較小的距離D,這是因為當塗佈底部填充材 料時,使用厚度較小的阻焊環31可避免底部填充材料中 有氣泡產生。在這些實施例中,包含大於或等於約1〇μιη 之阻焊環之距離D。在其他實施例中,阻焊環之距離D 可介於約ΙΟμιη至20μιη之間、約2(^„1至3〇μπι之間、 3〇μιη至40μπι之間、4〇μηι至50μπι之間,且在其他未 受限制之實施例中,距離D可大於50 μιη。 第2圖顯示完整的組件4〇之另一剖面圖,此組件4〇 包含第1圖之基材11,且其已進行額外的製程步驟來連 接晶片13及底部填充材料41,例如以焊球22連接。需 0503^A35492TWF/JEFF 9 201208022 左思的是,如第2圖所示,底部填充材料41直接位於介 電層16之上表面上並與其物理接觸。此種結構與習知技 術之組件形成鮮明的對照,習知技術的底部填充材料基 本上疋接觸阻焊材料之上表面。相較於底部填充材料與 阻焊材料之間的熱係數差異,底部填充材料及介電層的 熱膨脹係數有較佳的B。在—實施射,第2圖之组 成之、、’σ構,各知技術的結構相較,不但熱效能較佳, 且由熱效應(thermal effects)戶斤導致的機械應力較低。 在例如第2圖所示之實施例中,任何可能存在的執 膨脹係數失配,相較於習知技術均已減少。在使用此種 結構之實施例中,積體電路13在實用上對於降低熱膨服 係數失配及所導狀機顧力的效果將極為顯著。告制 程節點持續微縮,且晶圓現已被薄化至可使用例如石= 孔(TSVs),則需額外注意關於晶片龜曲的問題 明實施例所提供之方法及裝置對於這些薄化的晶片且有 勢:對:小於45 μ之半導體製程節點來說, —應力疋非常重要的。由於對於持續薄化的, 晶片翹曲是很需注意的問題。本發明實施例想知 技術提供了較㈣熱效能,且降低了簡材料破裂 ^填充材料破裂、介電層破裂、球破裂及橋接短路的發 成丄3 SI示:7另一實施例,其為將多個晶片組 成、,.。5至阻知裱中。在第3圖中,基材u 之基材’阻焊材料15中具有防焊開σ 33。底填: 41塗佈至每個晶片底下’且由於使用了防焊開= 0503-A35492TWF/JEFF ^ 201208022 :==電層16之上表面相接觸。雖然第3圖顯 :兩個曰曰片依覆晶封裝的方向設置於基材上,如需特定 應用’可設置更多晶片於基材上。 如而特疋 雖然本發明已以數個較佳實施例揭露如上,秋 =用^限定本發明’任何所屬技㈣財具有通常'ς識 者在不脫離本發明之精神和範圍内,當可作任意之 =與潤飾’因此本發明之保護範圍當視後附之申ς 範圍所界定者為準。 寻利 再者,本發明之範圍不僅限於說明書中所 =列::法及步驟。因此,任何所屬技術領域中具 有通吊知識者’在不脫離本發明之精神和範_,當可 更動與潤飾。熟知本領域技藝人士將可依:本 f明所揭不之現有或未來所發展之特定方法或步驟達成 目同的功此或相同的結果。因此本發明之保護 這些方法或步驟。
0503-A35492TWF/JEFF 11 201208022 【圖式簡單說明】 第1圖顯示本發明一實施例之剖面圖。 第2圖顯示第1圖之實施例之用於積體電路組成之 實施例中之剖面圖。 第3圖顯示本發明另一實施例之具有兩覆晶積體電 路晶片設置於其上之基材組成之剖面圖。 【主要元件符號說明】 13〜晶片; 16〜介電層; 18〜金屬層; 21〜填充材料; 24〜球焊盤; 27〜預焊材料; 33〜防焊開口; 41〜底部填充材料; 62〜晶片。 11〜基材; 15〜阻焊層; 17〜凸塊墊; 19〜芯部; 22〜焊球; 25〜貫穿孔; 31〜阻焊環; 4 0〜組成; 61〜晶片, 0503-A35492TWF/JEFF 12
Claims (1)
- 201208022 七、申請專利範圍: 1·一種封裝裝置,包括: 一封裝基材,包含: 一介電層,位於該基材之一晶片侧表面; 複數個導電墊,形成於該介電層之表面;以及 一阻焊層,設置於該導電墊及該介電層上; 其中該阻焊層包含複數個第1 口及複數個第二開 口’該些第-開口暴露該些導電藝,該些第二開口暴露 •介於該些導電墊之間的該介電層的表面,該些第二開口 與該些導電墊具有至少10微米之間距。 2·如申請專利範圍第i項所述之封裝裝置,其中該些 第二開口與該些導電墊具有至少50微米之間距。 3. 一種封裝裝置之製造方法,包括: 形成-介㈣於-封裝基材之—日日日片側表面,其中 該介電層之表面上具有複數個導電凸塊塾與該介電層中 之金屬導電層連接; • 以一阻焊材料覆蓋該介電層及該些導電凸塊墊; 依照該些導電凸塊墊在餘焊材财形成複數個第 一開口;以及 在該些導電凸塊墊之間形成複數個第二開口,該些 第二開口延伸穿越該阻焊材料且暴露該介電層之表面。 4. 如申請專利範圍第3項所述之封裝裝置之製造方 法,更包含: 設置-具有數個焊料凸塊位於該些導電凸塊塾 覆晶積體電路; 0503^A35492TWF/JEFF 13 201208022 仃—熱回焊’以使該些焊料凸塊*該此導電凸塊 墊電性及機械連接;及 n料0 底部填充材料於該覆晶積體電路下方; 觸。”該底部填充材料與該介電層之表面具有物理接 法,專利範㈣3項所述之封裝裝置之製造方 :嘵;:=! 一開口係經圖案化以使該阻焊材料形成 圍繞該導電凸塊塾之孔環。 專利範圍第3項所述之封裝裝置之製造方 /、開口與該些導電凸塊 微 米之間距。 ,、7甘如/請專利範㈣3項所述之封裝裝置之製造方 法’、形成該第二開口包含在該阻焊材料上進行雷射 鑽孔。 8.—種封裝裝置,包括: 一封裝基材,包含: 一介電層,位於一基材芯部之兩側上; 複數個導電墊,形成於該介電層之表面; 至;一積體電路晶片,黏著於該些導電墊上; 一阻焊層,設置於該些導電墊及該介電層上;以及 一底部填充材料,設置於至少—積體電路晶片及該 基材之間; 其中該阻焊層包含暴露該些導電墊之第一開口;及 暴露該些導電墊之間的介電層之表面的第二開口,該底 部填充材料與該些第二開口中之該介電層之表面相接 0503^A35492TWF/JEFF 201208022 觸’該些第二開口與該些導電 〇 ^ ^ 亍电蛩昇有至少10微米之間距。 弓如申印專利範圍第8項所述之封褒裝置,其中該也 第-開D與該些導電墊具有至少%微米之間距。 10.如申請專利範圍第8項所述之封裝裝置,更包含 複數個積體電路晶片設置其所對應之該些導電墊中。5 0503-A35492TWF^EFF 15
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-
2011
- 2011-02-18 TW TW100105363A patent/TWI496259B/zh active
- 2011-03-08 CN CN2011100585204A patent/CN102376667A/zh active Pending
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KR101333801B1 (ko) | 2013-11-29 |
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