TW201133735A - Connection pad structure for an electronic component - Google Patents

Connection pad structure for an electronic component Download PDF

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Publication number
TW201133735A
TW201133735A TW099124705A TW99124705A TW201133735A TW 201133735 A TW201133735 A TW 201133735A TW 099124705 A TW099124705 A TW 099124705A TW 99124705 A TW99124705 A TW 99124705A TW 201133735 A TW201133735 A TW 201133735A
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Taiwan
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electronic component
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TW099124705A
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English (en)
Inventor
Pierre Fereyre
Vincent Hibon
Yann Henrion
Patrick Lariviere
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E2V Semiconductors
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Publication of TW201133735A publication Critical patent/TW201133735A/zh

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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201133735 六、發明說明： 【發明所屬之技術領域】 本發明係有關電子組件在變薄的半導體基板上之製作 技術。其係主要相關於在變薄的矽基板上之背面照明式影 像感測器來做敘述。 【先前技術】 在變薄的基板上之影像感測器已被設計出，特別是改 善即將從非常薄的矽層之背面所照明的比色性能。 影像感測器製作於變薄的基板上通常包括以下步驟： 能夠進行約十至二十公分直徑的晶圓之工業性批量處理之 普通具有數百微米厚度的矽基板係在該正面上塗覆有單晶 矽之磊晶層，在絕緣層上覆矽（SOI)基板的情況中，該磊 晶層藉由氧化物層而與該基板之其餘部分選擇性地絕緣。 爲該感測器（本質上爲影像捕捉）之各種功能所需要的電子 電路係製作於此單晶層之正面上。該基板然後經由其支承 此電路之正面而被接合至足以供工業處理之厚度的轉移基 板上，且該起始的矽基板係變薄至數微米之厚度》最終非 常小的矽厚度阻礙工業晶圓處理，且這就是該接合之轉移 基板出現的成因。 由這些組件所造成的問題之一爲如何形成用於該組件 之外部連接的連接墊。將該組件安裝於封裝組件中通常需 要連接導線而能夠被接合。於設在該組件上之金屬連接墊 與該封裝中所提供的金屬墊片之間。 201133735 因爲在其中已形成有該等電子電路的基板係經由其正 面而被接合至轉移基板，該正面係不再可接達。因此，目 標爲藉由切成該變薄的基板直至到達預先在該等正面製作 步驟期間所形成之導電區域爲止來建立經過該背面的連接 〇 特別是，矽及形成在該正面上之絕緣層可被切薄（cut into)，直至抵達該第一鋁層爲止。然後，金連接導線以習 知的打線接合技術而被接合至暴露出之鋁區域。然而，此 區域係位在一杯形物內，因爲其需要覆蓋其之該矽及絕緣 層切薄。這排除了楔形接合方法之使用，其與球形接合方 法相反，其中，待接合之導線（通常由鋁所製成）因爲太傾 斜而不能夠被接合至杯形物的內側。這就是爲什麼其需要 繼續使用金導線接合，甚至在鋁導線將會是較佳的情況中 。除此之外，該杯形物係形成在半導體材料中，而不是絕 緣材料，且因此在該導線與該杯形物的邊緣之間有短路的 風險，除非該杯形物之側壁被製成爲絕緣的，這將使生產 複雜化。 再者，亦應指出使用於該打線接合之鋁區域原則上必 須比被使用於積體電路中之一般互連功能的鋁層更厚。然 而，上面所說明之技術使其可能實際上獲得僅只接達至第 一鋁層（除非期望甚至切割得更深），但在沒有理由此層要 厚到足以允許接合。爲了使此解決方法適合工業操作，因 此需要提供比通常所需要的更厚之第一鋁層，其多少需要 改變該標準的製作程序，而這是不所期望的。 -6- 201133735 另外，積體電路之製作需要能夠藉由晶圓測試機 (wafer prober)來進行電氣測試。該等測試探針被應用來接 達該積體電路上之墊片。這些墊片可被特別設置以供該測 試使用，但實際上它們亦隨後供連接導線之接合。希望能 夠在該正面製作步驟之後測試該積體電路，且能夠在接合 及變薄之後從背面再次測試該積體電路。而且如果可能的 話，其將爲有利的是能夠以在該正面製作步驟結束時所使 用的相同之測試探針組態來測試背面。 這意指著需要在正面上製作測試墊，該等測試墊具有 與背面上之外部連接墊相同的幾何組態或至少相同的地理 位置。其結果是，需要在該等連接墊之位置處製作形成於 該正面上且構成該測試墊之導電（鋁）層的至少一區域、與 形成在該背面上且構成該連接墊之另一導電層的區域之疊 加。甚至有可能具有數個金屬層之疊加，而該等金屬層係 形成在該正面上、連接在一起且具有與該測試墊及該連接 墊相同之幾何形狀。 假設某些連接墊必須能夠通過大電流（例如，一般的 電源墊片），在各種重疊的墊片間之連接被配置成，它們 被做成爲寬的或者在層之間有許多導電通孔。 然而，這些多個通孔快速地變得有問題，這是因爲它 們產生能夠減弱導線與墊片間之後續接合的離隙（relief) ° 這些離隙係由於允許接達至正面上之導電層的變薄之矽的 蝕刻爲一化學蝕刻之事實，該化學蝕刻形成具有傾斜側壁 之孔洞，而鋁下降進入該等孔洞而與導電層相接觸。 201133735 然而，已經了解到即使希望通過大電流，提供少數個 導電通孔（從1到4個）係足夠的，假設這些通孔係充分地 加長。這是因爲對於給定之墊片金屬厚度而言，比起與其 面積的關係，該通孔之整個電阻率與其長度更有關係。這 源自於該金屬係沈積於具有幾乎恆定之厚度的通孔中之事 實，且其爲如此之小的金屬厚度，其將會造成可觀的電阻 抗，即使是當該通孔具有大的面積時。 【發明內容】 本發明之目的在於提供一墊片組態，其致使接合的導 線與小巧的墊片之連接更容易，且其允許用與使用於正面 測試相同之測試探針組態而從背面來測試該等連接墊。 根據本發明，這就是爲什麼要提供一電子組件，其包 括在變薄的第一半導體基板之正面上所製作的積體電路， 該變薄的基板包括約2至10微米厚之薄的半導體層，該 第一基板係經由其正面而被安裝至轉移基板上，該組件包 括： -在該第一基板之正面上，藉由導電層的區域所形成 之測試墊沈積在該正面上；及 -在該半導體層之可接達的背面上，供外部連接用之 墊片係由沈積在此背面上之金屬層部份所形成，與該測試 墊相重疊且經由直接切穿過該變薄的半導體層之厚度的至 少一伸長開口而被電連接至該測試墊，而該金屬層通過該 開口，該連接墊具有大致上呈矩形之形狀（該‘矩形’ 一 -8 - 201133735 詞在此被考慮爲包含‘方形，），帶有允許外部連接導線 之接合的平面式第一表面部份與至少一第二表面部份’而 該伸長開口係位於該第二表面部份中，其特徵在於該半導 體層在該平面式第一表面部份的下方沒有開口’且在於此 第一部份包括至少一連續部位，而佔有該矩形面積之至少 5 0%的圓形碟片可以被內接在該連續部位中。 當該積體電路晶片被封裝時，該平面式第一表面部份 爲連接導線將被接合於其上之處；該等導電開口或通孔並 不位在此部份中；此區域之圓形部位實際上代表可用以固 定該導線且同時將該導線正確地中心定位在該墊片上之區 域。最終之墊片組態爲一小巧之墊片組態。此組態確保源 自於蝕刻該連接墊及該等在下方的層間之通孔的凹入離隙 (relief)不會與連接導線之後續接合造成問題。此組態允許 該測試墊及該連接墊之疊加，而不會過度膨脹，且因此允 許以用於該正面及背面測試之相同的探針組態之探針測試 〇 如同將被看到的，按照本發明之數個實用的組態可被 採用，且特別是下面的較佳組態的其中之一： -該墊片具有大致上呈矩形之形狀，其一個側邊比另 一個側邊更長出5與20%之間，該伸長開口沿著該矩形之 短的側邊且平行於此側邊而延伸；該連續之圓形部位而後 可佔有該矩形面積的75%至65% ;或，該開口沿著該矩形 之該二個短的側邊且平行於這些側邊而延伸，且該圓形部 位可佔有該矩形面積的6 5至7 0 % ; 201133735 一該墊片具有正方形之形狀，且該伸長開口沿著該正 方形之二個鄰接側邊且平行於這些側邊而延伸，該圓形部 位可接著佔有該墊片之面積的60%至70%;該伸長開口之 寬度較佳爲在該正方形之側邊長度的2%與9%之間； _該墊片具有正方形之形狀，且該長開口係沿著該正 方形之四個鄰接側邊且平行於這些邊緣而分佈；該圓形部 位可佔有該矩形墊片之面積的55%至65% ;該伸長開口之 寬度較佳爲在該正方形之側邊長度的1 %與5%之間；及 -該墊片具有正方形之形狀，且該長開口係分佈遍及 四個分開部份，每一個分開部份係位於該正方形之個別角 落中，該圓形部位佔有該墊片之面積的5 5 %至65%。 【實施方式】 圖1及2顯示用於電子組件的連接墊之可能的示範結 構。該電子組件爲形成在接合至轉移基板20上之變薄的 半導體基板12中之積體電路。該基板原則上係由矽所製 成。該組件特別可爲一意欲經過該變薄的基板之背面照明 的影像感測器。 在圖1中，該背面係面朝向上，該正面係面朝向下。 於該製作過程中，首先有正面製作步驟，特別地是使層摻 雜、沈積及蝕刻絕緣、導電與半導體化、接著經由其正面 而接合該半導體基板至轉移基板20上，而後自半導體基 板12之背面使其變薄，直至到達數微米（典型上爲自2至 5微米）之半導體厚度爲止，最後爲背面製作步驟等步驟。 -10- 201133735 圖1顯示該組件在此製作階段之示意剖面。在背面處理步 驟之後，其依然藉由接合該組件之連接墊與封裝組件的墊 片間之連接導線而將該組件安裝於封裝組件中。 於該正面製作步驟中，特別是交替地形成幾層之導電 (一般爲金屬，譬如鋁）及絕緣（一般爲氧化矽）層。不同的 導電層被蝕刻，以界定積體電路中之內部連接的圖案；該 等絕緣層被蝕刻，以界定能夠使導電通孔被建立於該等不 同層的導電層間之開口，其視這些層之間所需要的連接而 定。絕緣鈍化層覆蓋所有的金屬層；此層具有與轉移基板 20緊密接觸之平面式表面。 金屬導電層係標示以參考數字Ml、M2、M3、M4， 並且按照它們在正面之處理期間被沈積於半導體基板上之 順序；應注意的是所沈積之第一層爲Μ1，且該最後一層 係Μ4，已知基板12被顛倒顯示於圖1中。 嵌入有該等金屬層Ml至Μ4於其中之該組絕緣層係 標示以參考數字1 4。 圖1之右側顯示該組件的連接墊3 0之可能的結構。 其主要係由沈積及蝕刻於半導體基板的一部份22上之金 屬層（主要由鋁所製成）所形成。金屬係自該基板之背面而 被沈積。該部份22係藉由完全包圍此部份之溝槽24而與 該基板1 2之其餘部份電絕緣。此溝槽係自該背面而被直 接切穿該變薄的半導體基板12之厚度，向下直至該絕緣 層14。 連接墊30係電連接至下層的積體電路，且更精確的 -11 - 201133735 說法是經由分佈在該墊片之區域下方的導電通孔32而被 電連接至該等導電層Ml至M4的至少其中一層。該等導 電通孔爲直接穿過該變薄的基板12之厚度及通過該絕緣 層14的一部份之厚度而到達由該正面所形成之導電層的 開口。這些開口係塡充以金屬，而金屬（鋁）被沈積以形成 墊片3〇。於所顯示之範例中，該等導電通孔32與第一導 電層Ml形成實體接觸，且部份的層Ml、M2、M3與M4 係位在該墊片30的下方，且實質上具有與該墊片30相同 之幾何形狀及相同之水平位置。這些層係藉由分佈遍及該 區域之對應於此幾何形狀的範圍之其他導電通孔34而被 連接在一起。 圖2顯示分佈遍及該連接墊30之區域的導電通孔32 之可能組態的頂視圖。 導電通孔之存在在該墊片的表面中產生一離隙（relief) ，尤其是當矽基板係以液體蝕刻劑來予以蝕刻時。此離隙 基本上包括位在該等導電通孔的中心之凹部。如果該等通 孔係伸長的，則該凹入區域沿著長方向。 這些凹部可能會損壞將被接合至該墊片的連接導線之 接合的品質。 圖3及4顯示具有根據本發明之墊片結構的組件。 在此實施例中，分佈於該墊片區域的下方之導電開口 或通孔被幾乎延伸遍及該墊片的一個側面之全長的單一伸 長通孔32所替換。該墊片稍微呈係矩形的，具有長度A 之短側邊及長度B之長側邊。該通孔沿著短側邊而延伸。 -12- 201133735 因此可考慮，該墊片包括具有一完全平面式表面而不含有 導電通孔的側邊長度A之正方形第一表面部份、與非—致 地平面式且由於該通孔而具有凹入離隙的寬度B-A和長度 A之矩形第二表面部份。 該平面式正方形表面部份被保留以供連接導線之接合 用，且其可被考慮在此正方形區域中係內接直徑D = A之 圓形碟片（在圖形中以交叉影線來顯示），而更精確的說法 是其被保留以接合該導線，且其必須爲足夠大到足讓此種 接合能夠是可靠與可重現的。 根據本發明，該墊片被構成，使得內接於該平面式表 面中及可供使用於導線接合之圓形碟片的面積Sc(Sc = nD2/4) 佔有該矩形墊片之總面積St(St = AxB)的至少50%，且較佳 在於6 0 %與7 5 %之間。 較佳地是，於圖4之組態中，可用以嵌入該伸長通孔 之剩餘區域的寬度B-A延伸遍及等於該墊片的短側邊A 之大約5 %至2 0 %的寬度。然後，該墊片佔有一面積，該 面積爲大於正方形墊片之面積（A2)的5 %至20%，連同通孔 係完全位在該圓形接合區之下方。 如果需要使更多電流通過該導電通孔’則具有二伸長 通孔之組態可被採用，如圖5(沿著該長方形墊片之二短側 邊的每一個之邊緣的伸長通孔）或圖6(沿著正方形墊片之 二鄰接側邊的一個別伸長通孔）的其中之一所示。 於圖5之組態中，該墊片面積較佳被選擇’而使得該 圓形碟片之面積Sc佔有該墊片之面積St的65 %與70 %之 -13- 201133735 間，且爲了達成此目的，用以嵌入一個別通孔的每一側邊 之剩餘寬度將爲（B-A)/2，等於該墊片之短側邊的値A之 大約5%至10%。該墊片然後佔有一面積，該面積爲大於 如果該等通孔係位於該接合區的下方將佔有之面積的10% 至 20%。 於圖6之組態中，該墊片爲正方形的，A = B，且D小 於A;該墊片面積較佳被配置，而使得該圓形碟片之面積 Sc(Sc = nD2/4)佔有該墊片St = B2之面積的大約60%及70% 之間；爲了達成此目的，用以嵌入該等通孔之剩餘寬度B -D爲該直徑D之大約5 %至1 4 %。 該等通孔於圖6中被顯示爲分開的，但它們可爲盡可 能地在其鄰接之角落被接合。 如果該狹窄的通孔長度仍然不足夠，則其可另外試著 在該墊片之三或四側邊上放置一通孔，該墊片的中心含有 保留以供接合用之碟片。圖7顯示一具有四個伸長通孔之 組態，每一個通孔沿著該墊片的一側邊。該墊片爲正方形 的，其側邊長度B大於該碟片之直徑D。保留給該等通孔 之寬度爲（B-D)/2，且其被配置成此寬度爲D之大約5至 10% ;保留給該碟片之圓形面積則爲該墊片之面積的55% 至 6 5%。 在圖4至7之所有組態中，該等伸長通孔實際上佔有 該墊片的一側邊之全長。 最後，圖8顯示最佳使用該墊片之角落的解決方法。 該等伸長的導電通孔並不平行於該墊片（較佳爲矩形）之側 14 - 201133735 邊，反而被嵌入該等角落中，於直徑D之圓的外側所留下 之自由空間中。該側邊長度B係稍微大於該直徑D。直徑 D之碟片的面積St然後較佳在該墊片之面積的5 5 %及65% 之間。於圖8之圖形中，該等通孔具有延伸平行於該圓形 區域的圓形之形狀；它們亦可具有L形或三角形之形狀。 在頂視圖中具有圖4至8的組態的其中之一的圖3之 連接墊較佳突出於金屬接合區（land)之上，該等接合區具 有實質上與該墊片30相同的面積及相同的水平位置。該 等金屬接合區係形成在該等不同的導電層Ml至M4中， 且係藉由該等通孔34而被電連接，如圖1所示。該等通 孔34可被分佈遍及這些接合區之整個區域，且可爲極多 且爲極小的尺寸。這是因爲該等通孔係藉由不產生具有傾 斜側壁（不像該矽蝕刻）的開口之製程而被蝕刻於絕緣層中 ，但無論如何它們不被使用來接合連接導線。 於該製作期間，這些呈墊片的形式之金屬接合區可被 使用作爲探針測試操作用之測試墊。特別是，導電層M4 較佳包括構成測試墊40之區域，而在完成正面製作步驟 之後、並在絕緣鈍化平面化層被沈積在該正面上之前允許 測試。已知連接墊及測試墊具有相同之幾何形狀，用於該 正面及背面測試之測試探針組態可爲相同的（具有但書， 即該晶片組件具有對稱放置之墊片）。 顯示在圖2之組態中者爲連接墊30，其突出於該金屬 接合區之上。也有可能使用一組態，其中，該墊片係相對 於該等金屬接合區或該測試墊而被局部橫向地偏置（該連 -15- 201133735 接通孔32當然保持在該金屬接合區的上方，其必彡頁與_ 金屬接合區相接觸）。對於該正面及該背面而言’這 防礙該測試探針組態爲相同的，譬如藉由配置用於所有該 等墊片而在同一方向上偏置有相同之數量。 【圖式簡單說明】 本發明之其他特色及優點將在閱讀以下參考所附圖面 所給與之詳細敘述時變得明顯，其中： -圖1顯示在一變薄的基板上之積體電路結構的剖面 ，具有一連接墊，設有分佈在該墊片的下方並使該墊片連 接至在下方之導電層的通孔； 一圖2顯示圖1之連接墊的頂視圖； _圖3顯示根據本發明之墊片結構的剖面； -圖4至8顯示根據本發明之數個連接墊組態的頂視 圖。 【主要元件符號說明】 1 2 :半導體基板 1 4 :絕緣層 20 :轉移基板 22 :部份 24 :溝槽 30 :連接墊 3 2 :通孔 -16- 201133735 3 4 :通孔 4 0 :測試墊 Μ 1 :導電層 M2 :導電層 M3 :導電層 Μ 4 :導電層

Claims (1)

  1. 201133735 七、申請專利範圍： 1. 一種電子組件，包括在變薄的第一半導體基板（12) 之正面上所製作的積體電路，該變薄的基板包括約2至10 微米厚之薄的半導體層，該第一基板係經由其正面而被安 裝至轉移基板（20)上，該組件包括： -在該第一基板之該正面上，藉由導電層（M4)的區域 所形成之測試墊（40)係沈積在該正面上；及 -在該半導體層之可接達的背面上，供外部連接用之 墊片（3 0)係由沈積在此背面上之金屬層部份所形成，與該 測試墊（40)重疊且經由直接切穿過該變薄的半導體層之厚 度的至少一伸長開口（3 2)而被電連接至該測試墊，而該金 屬層通過該開□，該連接墊（30)具有大致上呈矩形之形狀 ，帶有允許外部連接導線之接合的平面式第一表面部份與 至少一第二表面部份，而該伸長開口係位於該第二表面部 份中，其特徵在於該半導體層在該平面式第一表面部份的 下方沒有開口，且在於此第一部份包括至少一連續部位’ 而佔有該矩形面積之至少50%的圓形碟片可以被內接在該 連續部位中。 2. 如申請專利範圍第1項之電子組件，其中’該墊片 具有大致上呈矩形之形狀，其一個側邊（B)比另一個側邊 (A)更長出5與20%之間，該伸長開口沿著該矩形之短的 側邊且平行於此側邊而延伸。 3 .如申請專利範圍第1項之電子組件’其中’該墊片 具有矩形之形狀，且該圓形部位之面積佔有該矩形面積的 -18- 201133735 7 5 % 至 6 5 %。 4 ·如申請專利範圍第1項之電子組件，其中，該墊片 具有矩形之形狀，其一個側邊比另一個側邊更長出5與 2 0%之間，該伸長開口沿著該矩形之該二個短的側邊且平 行於這些側邊而延伸。 5 .如申請專利範圍第1項之電子組件，其中，該墊片 具有矩形之形狀，該伸長開口沿著該矩形之該二個短的側 邊且平行於這些側邊而延伸，且該圓形部位之面積佔有該 矩形面積的65至70% » 6 .如申請專利範圍第1項之電子組件，其中，該墊片 具有正方形之形狀，且該伸長開口沿著該正方形之二個鄰 接側邊且平行於這些側邊而延伸，並具有寬度在該正方形 之側邊長度的2%與9%之間。 7 .如申請專利範圍第1項之電子組件，其中，該墊片 具有正方形之形狀，且該伸長開口沿著該正方形之二個鄰 接側邊且平行於這些側邊而延伸，並且該圓形部位之面積 佔有該墊片之面積的60%與70%之間。 8 .如申請專利範圍第1項之電子組件，其中，該伸長 開口係沿著該正方形之四個鄰接側邊且平行於這些邊緣而 分佈，並具有寬度在該正方形之側邊長度的1 %與5%之間 〇 9.如申請專利範圍第1項之電子組件，其中，該伸長 開口係沿著該正方形之四個鄰接側邊且平行於這些邊緣而 分佈，並且該圓形部位之面積佔有該墊片之面積的55%至 •19- 201133735 65%。 1 0 .如申請專利範圍第1項之電子組件，其中，該墊 片具有正方形之形狀’且該伸長開口係分佈遍及四個分開 部份，每一個分開部份係位於該正方形之個別角落中，該 圓形部位佔有該墊片之面積的5 5 %至6 5%。
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Publication number Priority date Publication date Assignee Title
US8987851B2 (en) * 2012-09-07 2015-03-24 Mediatek Inc. Radio-frequency device package and method for fabricating the same
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KR20220028675A (ko) * 2020-08-31 2022-03-08 주식회사 디비하이텍 후면 조사형 이미지 센서 및 그 제조 방법
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Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03200349A (ja) * 1989-12-27 1991-09-02 Sanyo Electric Co Ltd 不揮発性メモリ装置の測定方法
US5248903A (en) * 1992-09-18 1993-09-28 Lsi Logic Corporation Composite bond pads for semiconductor devices
JPH08213422A (ja) * 1995-02-07 1996-08-20 Mitsubishi Electric Corp 半導体装置およびそのボンディングパッド構造
KR100267105B1 (ko) * 1997-12-09 2000-11-01 윤종용 다층패드를구비한반도체소자및그제조방법
US20050134857A1 (en) * 2003-12-22 2005-06-23 Chartered Semiconductor Manufacturing Ltd. Method to monitor silicide formation on product wafers
US7361581B2 (en) * 2004-11-23 2008-04-22 International Business Machines Corporation High surface area aluminum bond pad for through-wafer connections to an electronic package
US20080122105A1 (en) * 2006-07-13 2008-05-29 Ping-Chang Wu Structure for preventing pad peeling and method of fabricating the same
FR2910705B1 (fr) * 2006-12-20 2009-02-27 E2V Semiconductors Soc Par Act Structure de plots de connexion pour capteur d'image sur substrat aminci
US8212328B2 (en) * 2007-12-05 2012-07-03 Intellectual Ventures Ii Llc Backside illuminated image sensor
JP4799543B2 (ja) * 2007-12-27 2011-10-26 株式会社東芝 半導体パッケージ及びカメラモジュール

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FR2948815A1 (fr) 2011-02-04
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CH701487B1 (fr) 2015-07-31
FR2948815B1 (fr) 2012-02-03
US20110024744A1 (en) 2011-02-03

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