TW200937590A - Wafer level chip scale package and process of manufacture - Google Patents

Wafer level chip scale package and process of manufacture Download PDF

Info

Publication number
TW200937590A
TW200937590A TW097150806A TW97150806A TW200937590A TW 200937590 A TW200937590 A TW 200937590A TW 097150806 A TW097150806 A TW 097150806A TW 97150806 A TW97150806 A TW 97150806A TW 200937590 A TW200937590 A TW 200937590A
Authority
TW
Taiwan
Prior art keywords
wafer
semiconductor
electrode
semiconductor devices
region
Prior art date
Application number
TW097150806A
Other languages
English (en)
Other versions
TWI399836B (zh
Inventor
Tao Feng
Francois Hebert
Ming Sun
Yueh-Se Ho
Original Assignee
Alpha & Omega Semiconductor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha & Omega Semiconductor filed Critical Alpha & Omega Semiconductor
Publication of TW200937590A publication Critical patent/TW200937590A/zh
Application granted granted Critical
Publication of TWI399836B publication Critical patent/TWI399836B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06183—On contiguous sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Description

200937590 九、發明說明： 【發明所屬之技術領域】 曰本發鶴有關—種半導體封裝結構，制是指—種低成本的晶圓級 日曰片尺寸封裝（wafer level chip scale package ; WLCSP)之製程。 【先前技術】 发半導體裝置通常具備⑽封裝阻抗與良好祕絲^特殊的例子為 金氧半場效電晶體（metal oxide semiconductor fie 丨 d effect trans 丨 stor; mosfet)裝置，尤其垂直式傳導功率金氧半場效電晶體打） ❹裝置’其具有閘極與源極於半導體晶片的-個表面，並在該表面的對面 具有汲極。醉導體裝置的封裝製程…般期望__簡單、快速與 有效率的方法。因此，已經有許多的封裝構想與方法陸續被發展出來。 在過去十年’矽製程技術已經大幅演進，而有數十年之久的一樣的 封裝技術及主要的封裝手段卻—纽續舰在。糊娜或焊錫所進行 的B曰粒貼附以及用銘或金來打線接合到導線框架，仍然為目前主流的半 導體封裝方法。然而，半導體製程技術的演進，將會使得寄生效應 =aras_ (譬如電阻、電容及電感）伴隨著具有許多效能限制因素的 ，統封裝技術而產生。由傳統覆晶技術賴子來說，其巾—項缺點是不 ❹容易電性連接至晶粒的背側。這些限制在譬如為功率切換裝置的高電流 應用上會變得相當明顯。 美國專利第6,767,820號揭露一種半導體金氧半閘控⑽心卵㈣ 裝置之晶圓級“尺寸封裝。金氧半_(MC)S.gated)裝置晶片的源極 ，是由鈍化層所覆蓋，鈍化層的選擇可選自光敏性液態樹脂 (Photosensitive丨iquid epoxy)、或氮化矽（由此加汕卩丨舶）薄膜之類 等等為較佳。然後，將鈍化層材料乾燥，而披覆有純化層的晶片是使用 標準的光微影技術進行曝光，將晶片顯影並在鈍化層上產生開孔，使得 y方的源極金屬產生複數個露出的表面區域以及相似的開孔並露出在 日日片上每-個晶粒的下方之閘極。鈍化層的開孔之製作通常是穿過習知 200937590 鈍化層下方之可焊接的金屬，譬如為鈦（titanium)、鎢（tungsten)、 錄（nickel)、或銀（silver)。在開孔形成之後，晶片就會接著進行切割 或者用不同方法來分開為個別的晶粒。然後，晶粒上可焊的汲極侧就會 連接到U型或杯型汲極夾片（C|jp)，使用導電封膠或焊錫或類似的元 件’以接合晶粒的底部汲極至汲極夾片。 美國公開第2003/0052405號揭露一種垂直式功率金氧半場效電 晶艎（MOSFET)裝置，其具有汲極形成於矽基板的底表面並連接至 没極上方的導線框架，而閘極與源極則露出於此裝置的底部。此金氧半 場效電晶體（MOSFET)裝置是以合成樹脂（seal)進行封合，樹脂譬 ❹ 如為環氧樹脂（epoxy)或矽利康(silicone)，使得金氧半場效電晶體 (MOSFET)裝置與導線框架的内部被覆蓋住。在金氧半場效電晶體 (MOSFET)裝置的底表面，合成樹脂的表面概略和導線框架及閘極/ 源極的表面齊平。也就是說’在半導體裝置的底表面上，導線框架的外 導線部伤之底表面以及閘極/源極之底表面是露出來的，以連接至封裝 基板的一個導電部位（封裝表面）。然後’這些閘極/源極的周圍會由合 成樹脂所覆蓋。 美國專利第6,133,634號揭露一種具有功率金氧半場效電晶體 (MOSFET)裝置之覆晶封裝，其包含有一汲極端、一源極端與一閘極 © 端。汲極端連接至導電載體與焊接錫球之外部陣列，源極端與閘極端則 連接至焊接錫球之内部陣列。導電載體與焊接錫球之外部陣列提供了印 刷電路板和汲極端之間的電性連接。 美國專利第6,469,384號揭露一種半導體裝置之封裝方法，半導體 裝置譬如為金氧半場效電晶體(MOSFET)裝置，它並不需要成型機構。 金氧半場效電晶體(MOSFET)裝置是耦接至基板，使得晶粒的源極區域 與閘極區域可以耦接至基板。金氧半場效電晶髏(MOSFET)裝置安裝於 印刷電路板（PCB)上，且晶粒的表面是使用了錫膝或合適的電性傳導 内連接物質來直接耦接至印刷電路板（PCB)，並作為汲極的連接。晶 200937590 表面Μ接至基板基板包含有晶粒的閘極區域與源極區域。因此， 的焊接錫球是用來將晶粒的閑極_合至印刷 Γ ) 將焊魏義域紛1合緣讀極區域 至印刷電路板（PCB)。 之切技㈣㈣直式功率錢半場效電晶體 (MOSFET)裝置的封裝設計，可以提供給個別的金氧半場效電晶體 (MOSFET)的源極、閘極與汲極之電性内連接。然而，在晶圓被分 開為個別的晶粒之後，將需要額外的安裝步驟。此外，用來提供給從晶 粒的背側至前侧的汲極接觸之金屬夾片的使用，會縮小在印刷電路板 ® (PCB)上的晶粒的可用空間。所以期望發展—種封裝設計與製造它的 程序，可以讓晶圓級製程具有較低成本並縮短每個部份的步驟。 【發明内容】 請參見本發明之實施例所揭露的内容，即實現了以上先前技術中所 期望的封裝設計及製造程序。 本發明之其他目的與優點，係可⑽由卿接下來所詳細描述之内 容與配合圖式之說明將變得更為清楚。 【實施方式】 ❹ 以下詳細說明係為本發明之最佳實施例，且以下說明並非用以限制 本發明之_請專利範圍，僅為配合圖式制騎本發明之中心思想，而 主張之權利範圍為定義於接續的申請專利範圍中。 ，請參閱第1A圖〜第1B圖’其繪示根據本發明之一個較佳實施例 之半導體裝置100的前側和背侧之示意圖。本實施例中，半導體裝置 100可以為垂直式功率金氧半場效電晶體（M〇SFET)e如第1A圖所 不、’源極（S) 108與閘極（G) 110是設置於半導體裝置彳〇〇的前側， 並透過在鈍化層102上的開口視窗來連接至源極（s) 1〇8與閘極（g) 11 〇下方的源極連接墊與閘極連接墊，而鈍化層彳〇2是沉積在由半導體 材料（譬如，矽）所製成的半導體基板112上。源極連接墊與閘極連 7 200937590 接墊連接至位在垂直式功率金氧半場效電晶體（m〇sfet)之前側上 方的源極區域與閘極區域，且垂直式功率金氧半場效電晶艘 (MOSFET)具有汲極區域，而錄區域通常位在此半導體裝置 的背侧。在如第1A騎緣示之例子中，汲極（D) 1〇7可以設置在半 導體裝置1〇〇之前側的修整邊緣（tri麵ed c〇mer) 1〇6。如第从圖 〜第1B 緣示，藉由在半導體基板112 _上方以及半導趙基板 112的側壁105上方之修整邊緣鄕處的電性傳導屠IQ*，汲極⑼ 107係電性連接至鄰近半導體裝置1〇〇背側之汲極區域。傳導層1〇4 可以使用譬如為銅（Cu)之金屬，细選擇性電鍍方法來鍍於半導體 ❹裝置100的多個部位上，或者，使用譬如為錄/金（Nl7Au)之金屬組合 物，利用無電鍍方法來鍍在所選擇的半導體裝置1〇〇部位上。鎳/金包 含-層鎳，以及包含-層相當薄的金在鎳上面用來防止氧化。没極1〇7 之女裝可以延伸過被純化層所覆蓋之半導體裝置前側的部份主動元件 區域114，這樣的安裝方法可使得主動元件區域的損失最小化，也可以 形成較大的源極108與閘極110的區域，並且獲得較小的阻抗。在一 些實施例中，汲極107可以予以省略，且可以透過修整邊緣（trjmmed corner)106側壁上的傳導層1〇4來電性連接到汲極區域，見第扣圖。 請參閱第2A圖〜第2P圖，其繪示根據第1A圖〜第ΐβ圖中所描 © 述的類型之半導體裝置（例如，垂直式功率金氧半場效電晶體 (MOSFET ))的晶圓級晶片封裝製程的一個實施例之示意圖。如第2A 圖所繪示，其步驟一開始為在一基板206上方製作複數個元件構造。 根據本實施例’基板206可以是半導體晶片，譬如矽晶片，其包含有 複數半導體晶粒。鈍化層（圖中未示）可以沉積在基板2〇6之上，且 閘極連接墊（G) 202與源極連接墊（S) 204是透過在半導體晶片上 表面之鈍化層上的視窗開口而露出來〇金屬種子層208沉積在基板206 上表面的多個選擇的部位，並覆蓋住閘極區域（G)202與源極區域（s) 204’如第2B圖。種子層208可以是一層薄的金屬或是金屬合金層， 8 200937590 用來和之後會沉積在種子層208上方的金屬材料相匹配。根據本發明 之實施例，金屬材料為銅（Cu)的情況，是使用在電極材料，種子廣 208可以由一層鈦銅所形成’且其厚度少於4微米（从。多個孔洞 210是透過一罩幕及利用蚀刻方法來形成在種子層208上，如第2C圖 所繚示。接著’如第2D圖所繪示’光阻罩幕212是設置於種子層208 之上。光阻層212可以藉由在閘極連接墊202與源極連接塾204上方 之多個開口而被圖案化。厚的金屬層214可以鍍在種子層208上，以 形成閘極213與源極215 ’如第2E圖所緣示。根據本發明之實施例， 銅（Cu)可以電鍍於種子層208上方，並具有少於1微米（从m)的 ❹厚度’而在光阻層212之開口處的銅鍍層厚度最好大於1〇微米（私 m)。基板206可以背研（back-grind)至預期的厚度，如第2f圖所繪 示，並以少於400微米（#m)為較佳。 在背研（back-grind)之後，一個或更多的穿孔a彳可以透過基板 206來蝕刻形成，如第2G圖所繪示，譬如，使用光阻層212與厚金屬 層214 (譬如，罩幕）。第2N圖是在第2(3途中所描述的具有穿孔211 之晶片之頂視或底視圖^然後，基板2Q6可以進行等向性_，例如， 在氧化物_ (濕式操作）之後接著等向性梦姓刻，去形成具有圓形邊 緣209的穿孔211於基板206的背侧，如第2H圖所緣示。這會將在 後續步釋中在穿孔211之被表面和内壁上所形成的傳導層，增加其機 械強度並改善不均勻度4外，金屬種子層216形成於基板216的背 面與穿孔211的側壁，如第2丨圖所繪示。 層厚的金屬層218 ’譬如，銅可以被鍍在種子層2彳6之上方，如 第2J圖所繪示。然後，光阻層212會在侧種子層2〇8之後被移除掉， 如第2K圖〜第2L圖所緣示，以形成分離的閘極217與源極219，其 二另二立於閘極連接塾2。2與源極連接塾⑽上方。請參閱第圖〜 前士 為如第2L圖中所描述之晶片的頂視圖與底視圖。如第2〇 、不’沒極214是位於每個金氧半場效電晶體（M〇SFET)結 200937590 構的角落處’並且部分覆蓋住半導體裝置的一些主動區域215。汲極 214是藉由披覆於穿孔211之背侧與侧壁之金屬層2彳8,而電性連接至 汲極區域並鄰近於半導鱧基板2〇6的背側。 然後’如第2Μ圖中所縿示，會將晶片切割成個別的半導鱧裝置。 切割的過程中是將穿孔211切開，但保留了穿孔211的側壁部位以及 鍵在侧壁之金屬層218的對應雜，而提供了背酿極區域姐極214 之間的電性内連接。 穿孔211並不會限定為圓形樣式。譬如，第2q圖會是一種本發明 之可替代實施例，其中穿孔211具有非圓形樣式，但替代的是加號 ❹（_-_)形狀。穿孔2仂的其它樣式皆在本發明之實施例所保護 的範圍内。 請參閱第3A圖〜第3丨圖’其緣示-種製造半導體裝置之功率晶圓 級晶片尺寸封裝的可替代程序的示意圖。如第3A圖所緣示，晶片包含 複數半導體裝置結構（譬如，垂直式功率金氧半場效電晶艎 (MOSFETs)) ’半導體裝置結構則包含半導體基板3〇6。鈍化層（圖 中未示）可以沉積於矽基板3〇6之上，且閘極連接墊（G) 3〇2與源極 連接塾（S) 304經由在晶壯表面祕化層上的開口視窗而露出。 光阻罩幕3Q8沉積於晶片之上表面，並覆蓋住閘極區域⑹302 ©與源極區域（S) 304以及位於兩個或更多的結構之間的交叉點的孔洞 310，如第3B圖所緣示。然後，基板306可以背研（back grjnd)至 預期的厚度，如第3C圖所繪示。 基板306是透過孔洞310來蚀刻，以形成穿孔π，如第3D圖所 繪不。然後，將矽基板306進行等向性蝕刻，譬如，在氧化物蝕刻（濕 式操作）之後接著使用矽蝕刻，去形成圓形邊緣3〇9的穿孔311在^ 板306的背側，如第3E圖所燴示。第一金屬層312會形成於 的背側以及穿孔311，且第-金屬層312鍍在穿孔311的侧壁，如第 3F圖所繪示。根據本發明之實施例，第一金屬層312可以為任何適合 200937590 用來無電鍍錄之披覆作業的金屬，譬如為銘(Al)或銘合金沉積於鈦(丁丨) 層的上面。第-金屬層312之總厚度可以大於]微米（_)，並以大 於2微米Um)為較佳。在形成第一金屬層312之後，光阻罩幕3〇8 接著會被移除掉，如第3G圖所繪示。第二金屬層314，譬如為無電鍍 鎳/金（Ni/Au) ’無電鍍於第一金屬層312上方，如第3H圖所繪示。 根據本發明之實施例，鎳的厚度可以在彳〜川微米之間，且金 的厚度可以小於1微米（_)，並具有總厚度小於彳彳微米（从m)。 形成第二金屬層314的步驟可以僅為一個，將金屬成長在閘極連接墊 302、源極連接墊304上方並覆蓋住金屬層312，來形成閘極M3、源 © 極315與汲極317。最後’將晶片分割以形成個別的垂直式功率金氧半 場效電晶體（MOSFET) 316，如第3丨圖所繪示。 對照於習知製程，包含有閘極、源極之前側通常與後側分隔開來， 因此，於前侧金屬沈積時，後側需要被保護，且前侧與後侧使用不同的 金屬沈積。前側通常使用鋁-梦-銅合金，而後侧使用鋁，導致於在固定 於電路板時難以焊接。對照於前述實施例中，源極、閘極與汲極使用相 同金屬來連接，使得製程被簡化並且降低成本。 請參照第4A圖〜第4B圖，其繪示本發明將在第1C圖中之垂直 式功率金氧半場效電晶體（MOSFET)之晶圓級晶片尺寸封裝安裝至 © 印刷電路板的可替代程序的示意圖。 如第4A圖所示，在第1C圖中描繪的晶圓級晶片尺寸封裝 (WLCSP) 400具有前側閘極402、源極404以及側壁汲極406，而 可安裝結合至電路板401，藉由覆晶方式將裝置設置於電路板401之 後，錫膠408可以沈積於電路板401的電極410。接著，錫膠408逛 焊而形成閘極402、源極404、汲極406以及電路板401之相對應電 極410之間的電性内連接，如第4B圖。迴焊後，錫膠408也可以在側 壁之修整邊緣上溼潤汲極金屬電極406，來形成小的阻抗。 本發明所提出之上述實施例，避免使用金屬接觸墊，譬如金屬帽或 200937590 是其他結構，或是貼片切割製造程序來提供半導體裝置晶片之前側、後 側之間的連接墊。且本發明實施例，於晶圓尚未被切割為個別裝置晶片 時，允許半導體裝置的前側、背側形成電性接點。本發明提供之實施例 使得半導體裝置之晶圓等級晶片封裝更加簡化、有效率且成本降低。 儘管上述實施方式所闞述為垂直功率金氧半場效電晶體(m〇sfet) 裝置，但是本發明同樣也可以應用於其他各種的垂直半導體裝置，譬如 為絕緣栅雙極電晶體（Insulated Gate Bipolar Trans丨stor，IGBT)、或 是底部源極的金氧半場效電晶艎(M0SFET)裝置、雙極功率電晶體等。 雖然本發明以前述之實施例揭露如上，然其並非用以限定本發明。 © 在不脫離本發明之精神和範圍内，所為之更動與潤飾，均屬本發明之專 利保護範@。_本發0麟狀之紐範圍請參考所狀_請專利範 圍。 【圖式簡單說明】 第1Α圖係綠示根據纟發明之一個實施例之半導體裝置的前側（源極與 閘極側）的示意圖； / 第1Β圖係繪示根據本發明第认圖之半導體裝置的背側（及極侧）的 示意圖； 第1C圖係繪示根據本發明之一個實施例之半導體裝置的前侧之可替 ^ 結構的示意圖； 第2Α圖〜第2Q圖係繪示根據本發明之一個實施例之製造第1Α圖〜 第1Β圖之垂直式功率金氧半場效電晶體（M0SFET)之晶圓級晶片尺 寸封裝的程序的示意圖； 第3Α圖〜第3丨圖係繪示根據本發明之另一個實施例之製造第π圖之 垂直式功率金氧半場效電晶體（M0SFET)之晶圓級晶片尺寸封裝的 可替代程序的示意圖；以及 =4Α圖〜第4Β圖係緣示本發明將在第1C圖中之垂直式功率金氧半 觀1：0¾¾ CM0SFET)之晶SJ級晶狀寸封裝安裝至印刷電路板的 12 200937590 可替代程序的示意圖。 【主要元件符號說明】 100半導體裝置 102鈍化層 104傳導層 105側壁 106修整邊緣 107汲極 108源極 © 110閘極 112半導體基板 114主動元件區域 202閘極連接墊 204源極連接墊 206基板 208種子層 209 圓形邊緣 210孔洞 ❹211穿孔 212光阻罩幕 214金屬層 215主動區域 216種子層 217閘極 218金屬層 219源極 302閘極連接墊 200937590 304源極連接墊 306半導髏基板 308光阻罩幕 309 圓形邊緣 310孔洞 311穿孔 312第一金屬層 313 閘極 314第二金屬層 φ 315源極 316垂直式功率金氧半場效電晶體 317汲極 400晶圓級晶片尺寸封裝 401電路板 402閘極 404源極 406汲極 408錫膠 © 410電極

Claims (1)

  1. 200937590 十、申請專利範面： 1. 一種半導體裝置，其包含： 一半導體基板，具有一第一連接墊與一第二連接墊，該第一連接墊 與該第二連接墊分別電性連接至位於該半導體基板之一前側上的 一第一區域與一第二區域； 一第一電極，電性連接至該第一連接墊； 一第一電極’電性連接至該第二連接墊；以及 一第三電極’包含一傳導層，該傳導層位於一修整邊緣（trjmrned comer)之一側壁並延伸至該半導體基板之一背側，其中該傳導 〇 層係電性連接至位於該半導體基板之該背側之一第三區域。 2·如申請專利範圍第1項所述之半導體裝置，更包含一垂直式功率金 氧半場效電晶體(vertical power M0SFET) 3·如申請專利範圍第2項所述之半導體裝置，其中該第 '一區域包含·一 源極區域’該第二區域包含一閘極區域，且該第三區域包含一沒極 區域。 4_如申請專利範圍第3項所述之半導體裝置，其中該源極區域與該閘 極區域係位於鄰近該半導體基板之該前側，該汲極區域係位於鄰近 該半導體基板之該背侧。 © 5.如申請專利範圍第]項所述之半導體裝置，其中該第一電極、該第 二電極與該第三電極係由相同導電材料所製成。 6. 如申請專利範圍第1項所述之半導體裝置，其中該第一電極、該第 二電極與該第三電極係由選自銅或無電鍍鎳/金層之群組組合的導 電材料所製成。 7. 如申請專利範圍第1項所述之半導體裝置，其中該第三電極更包含 -傳導層’該傳導層延伸至該半導艘基板之該前側的一部分。 8. 如申請專利範圍第7項所述之半導體裝置，其巾該第三電極之設置 係使得該傳導層延伸覆蓋於該半導體基板之該前側上的一主動區域 15 200937590 的一部分。 9.如申請專利範圍第1項所述之半導體裝置，其中該半導體裝置之設 置係安裝於一印刷電路板上，並使得該第一電極、第二電極與該= 三_藉由相對及電性接觸該印刷電路板上的對應連接處，來^成 該印刷電路板至該第-電極、第二電極與該第三電極之間的電性連 接0 ίο. —種製造複數半導體裝置之方法，其步驟包含： 提供一晶片，該晶片包含複數半導體晶粒，其中每一半導體晶粒包 含第連接塾與一第一連接塾，該第一連接塾電性連接至一第 © 一區域，該第二連接墊電性連接至位於該晶片之一前表面之一第 二區域與位於該晶片之一背表面之一第三區域； 形成複數穿孔，該些穿孔係穿過該晶片並位於該些半導體晶粒之間 的複數交叉點（comer丨ntersections);以及 形成一傳導層，於該晶片之該背表面與該些穿孔之複數側壁上並延 伸至該晶片之該前表面。 11. 如申請專利範圍第10項所述之製造複數半導體裝置之方法，其中 該步驟b)包含有： 沉積一光阻罩幕，覆蓋於該晶片之該前表面，其中該光阻罩幕包含 © 複數孔洞，其中每一孔洞係位於該些半導體晶粒之間的該些交又 點；以及 透過該光阻罩幕上之該些孔洞去蝕刻該晶片，以形成該些穿孔穿過 該晶片。 12. 如申請專利範圍第彳彳項所述之製造複數半導體裝置之方法，更包 含移除該光阻罩幕。 13. 如申請專利範圍第項所述之製造複數半導體裝置之方法，更包 含研磨該晶片之該背表面至一預定厚度。 14·如申請專利範圍第1〇項所述之製造複數半導體裝置之方法，更包 16 200937590 含在步驟b)之後’等向性蝕刻該晶片，以在該晶片之該背表面形成 具有圓角的該些穿孔。 15. 如申請專利範圍第1〇項所述之製造複數半導體裝置之方法，其中 該步驟c>更包含利用一罩幕，沉積一第一傳導層於該晶片之該背表 面與該些穿孔之側壁並覆蓋該晶片之該前表面。 16. 如申請專利範圍第15項所述之製造複數半導體裝置之方法更包 含無電鍍一第二傳導層於該第一連接墊與該第二連接墊上以及該第 一傳導層上。 ° 17. 如申請專利範圍第16項所述之製造複數半導體裝置之方法，其中 © 該第二傳導層包含複數無電鍵錄/金（Ni/Au)層。 18. 如申請專利範圍第10項所述之製造複數半導體裝置之方法，更包 含在步驟C)之後’切割該晶片以形成複數個別的半導體裝置。 19·如申請專利範圍第10項所述之製造複數半導體裝置之方法更包 含有： 在步驟b)之前沉積一種子層於該晶片之該前表面上；以及 形成複數孔洞於該種子層上，其中每一孔洞係位於該些半導體裝置 結構之間的交叉點。 20_如申請專利範圍第19項所述之製造複數半導體裝置之方法，更包 © 含電鍍銅於該種子層。 21. 如申請專利範圍第20項所述之製造複數半導體裝置之方法，更包 含背向餘刻該種子層。 22. 如申請專利範圍第10項所述之製造複數半導體裝置之方法，其中 該傳導層包含電鍍鋼。 23. 如申請專利範圍第1〇項所述之製造複數半導體裝置之方法，更包 含在步驟b)之後，沉積一種子層在該晶片之該背表面與該些穿孔之 該些側壁上。 24·如申請專利範圍第項所述之製造複數半導體装置之方法，其中 17 200937590 步驟C)更包含在無電鍍鎳/金之後接著沉積一鋁合金覆蓋於一鈦薄 層上。
TW097150806A 2008-01-31 2008-12-26 晶圓級晶片尺寸封裝及製造方法 TWI399836B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/023,921 US7955893B2 (en) 2008-01-31 2008-01-31 Wafer level chip scale package and process of manufacture

Publications (2)

Publication Number Publication Date
TW200937590A true TW200937590A (en) 2009-09-01
TWI399836B TWI399836B (zh) 2013-06-21

Family

ID=40930851

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097150806A TWI399836B (zh) 2008-01-31 2008-12-26 晶圓級晶片尺寸封裝及製造方法

Country Status (4)

Country Link
US (3) US7955893B2 (zh)
CN (1) CN101904004B (zh)
TW (1) TWI399836B (zh)
WO (1) WO2009099834A2 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI467721B (zh) * 2010-07-29 2015-01-01 Alpha & Omega Semiconductor 晶圓級晶片尺寸封裝
US9761464B2 (en) 2015-04-15 2017-09-12 Excelliance Mos Corporation Power MOSFET and manufacturing method thereof

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7955893B2 (en) * 2008-01-31 2011-06-07 Alpha & Omega Semiconductor, Ltd Wafer level chip scale package and process of manufacture
US8373257B2 (en) * 2008-09-25 2013-02-12 Alpha & Omega Semiconductor Incorporated Top exposed clip with window array
US8222078B2 (en) * 2009-07-22 2012-07-17 Alpha And Omega Semiconductor Incorporated Chip scale surface mounted semiconductor device package and process of manufacture
US20110075392A1 (en) * 2009-09-29 2011-03-31 Astec International Limited Assemblies and Methods for Directly Connecting Integrated Circuits to Electrically Conductive Sheets
US9263406B2 (en) * 2009-11-10 2016-02-16 Rohm Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US8362515B2 (en) * 2010-04-07 2013-01-29 Chia-Ming Cheng Chip package and method for forming the same
US8987878B2 (en) 2010-10-29 2015-03-24 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
CN102403236B (zh) * 2010-09-07 2015-03-04 万国半导体(开曼)股份有限公司 芯片外露的半导体器件及其生产方法
TWI427717B (zh) * 2010-12-28 2014-02-21 Alpha & Omega Semiconductor Cayman Ltd 一種倒裝晶片的封裝方法
JP6024076B2 (ja) * 2011-01-13 2016-11-09 セイコーエプソン株式会社 シリコンデバイスの製造方法
CN102122671B (zh) * 2011-01-31 2012-09-19 江阴长电先进封装有限公司 后通孔互联型圆片级mosfet封装结构及实现方法
CN102122670B (zh) * 2011-01-31 2012-07-25 江阴长电先进封装有限公司 沟槽互联型圆片级mosfet封装结构及实现方法
US8518748B1 (en) 2011-06-29 2013-08-27 Western Digital (Fremont), Llc Method and system for providing a laser submount for an energy assisted magnetic recording head
US8450188B1 (en) * 2011-08-02 2013-05-28 Micro Processing Technology, Inc. Method of removing back metal from an etched semiconductor scribe street
US8288204B1 (en) * 2011-08-30 2012-10-16 Western Digital (Fremont), Llc Methods for fabricating components with precise dimension control
CN103165524B (zh) * 2013-04-03 2015-07-15 株洲南车时代电气股份有限公司 一种igbt芯片及其正面铜金属化结构的制作方法
US20160322342A1 (en) * 2014-01-15 2016-11-03 Panasonic Intellectual Property Management Co. Lt Semiconductor device
US10008473B2 (en) 2014-06-02 2018-06-26 Qorvo Us, Inc. Power package lid
US9666498B2 (en) 2014-06-02 2017-05-30 Qorvo Us, Inc. Ring-frame power package
US10199313B2 (en) 2014-06-02 2019-02-05 Qorvo Us, Inc. Ring-frame power package
GB2534204A (en) * 2015-01-17 2016-07-20 Melexis Technologies Nv Semiconductor device with at least one truncated corner and/or side cut-out
FR3040532B1 (fr) * 2015-08-31 2017-10-13 St Microelectronics Tours Sas Puce a montage en surface
US10083888B2 (en) * 2015-11-19 2018-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US10910233B2 (en) * 2018-04-11 2021-02-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN110277321B (zh) * 2019-05-30 2021-04-20 全球能源互联网研究院有限公司 功率芯片预封装、封装方法及其结构、晶圆预封装结构
CN110310931A (zh) * 2019-07-15 2019-10-08 深圳市泛宜微电子技术有限公司 一种芯片及封装元件
CN110349842A (zh) * 2019-07-24 2019-10-18 四川科尔威光电科技有限公司 一种芯片的制作方法
DE102019120886A1 (de) * 2019-08-02 2021-02-04 Infineon Technologies Ag Halbleitergehäuse mit einem Hohlraum in seinem Gehäusekörper
CN111508922A (zh) * 2020-04-26 2020-08-07 深圳市昭矽微电子科技有限公司 Mosfet芯片
US12087682B2 (en) * 2020-06-22 2024-09-10 Intel Corporation Power delivery structures
CN113555289A (zh) * 2021-06-28 2021-10-26 无锡市乾野微纳电子有限公司 一种降低wlcsp芯片的rdson的阻值的方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4729815A (en) * 1986-07-21 1988-03-08 Motorola, Inc. Multiple step trench etching process
JP2800884B2 (ja) 1995-10-27 1998-09-21 日本電気株式会社 横型ｄｓａパワーｍｏｓｆｅｔを備えた半導体装置
US6164523A (en) * 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US6133634A (en) 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
JP3614030B2 (ja) * 1999-04-02 2005-01-26 株式会社村田製作所 マザー基板，子基板およびそれを用いた電子部品ならびにその製造方法
KR100608611B1 (ko) * 1999-06-02 2006-08-09 삼성전자주식회사 비아 홀을 이용한 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법
EP1258040A4 (en) 2000-02-10 2009-07-01 Int Rectifier Corp VERTICAL-CONDUCTING PROTUBERANCE CHIP WITH CONTACT PLOTS ON ONE SURFACE
US6624522B2 (en) 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
US6355502B1 (en) * 2000-04-25 2002-03-12 National Science Council Semiconductor package and method for making the same
US6469384B2 (en) 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6646329B2 (en) 2001-05-15 2003-11-11 Fairchild Semiconductor, Inc. Power chip scale package
JP3868777B2 (ja) 2001-09-11 2007-01-17 株式会社東芝 半導体装置
US6784540B2 (en) 2001-10-10 2004-08-31 International Rectifier Corp. Semiconductor device package with improved cooling
TWI271866B (en) * 2005-05-18 2007-01-21 Au Optronics Corp Thin film transistor and process thereof
US7585750B2 (en) * 2007-05-04 2009-09-08 Stats Chippac, Ltd. Semiconductor package having through-hole via on saw streets formed with partial saw
US7955893B2 (en) * 2008-01-31 2011-06-07 Alpha & Omega Semiconductor, Ltd Wafer level chip scale package and process of manufacture

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI467721B (zh) * 2010-07-29 2015-01-01 Alpha & Omega Semiconductor 晶圓級晶片尺寸封裝
US9761464B2 (en) 2015-04-15 2017-09-12 Excelliance Mos Corporation Power MOSFET and manufacturing method thereof
TWI690083B (zh) * 2015-04-15 2020-04-01 杰力科技股份有限公司 功率金氧半導體場效電晶體及其製作方法

Also Published As

Publication number Publication date
TWI399836B (zh) 2013-06-21
US20140239383A1 (en) 2014-08-28
WO2009099834A3 (en) 2009-10-01
WO2009099834A2 (en) 2009-08-13
US20090194880A1 (en) 2009-08-06
US20110108896A1 (en) 2011-05-12
CN101904004B (zh) 2013-01-02
US7955893B2 (en) 2011-06-07
US8981464B2 (en) 2015-03-17
US8716063B2 (en) 2014-05-06
CN101904004A (zh) 2010-12-01

Similar Documents

Publication Publication Date Title
TW200937590A (en) Wafer level chip scale package and process of manufacture
US7541681B2 (en) Interconnection structure, electronic component and method of manufacturing the same
US6830959B2 (en) Semiconductor die package with semiconductor die having side electrical connection
TWI395277B (zh) 晶圓水準的晶片級封裝
KR101561684B1 (ko) 반도체 다이 패키지 및 그의 제조 방법
TWI440151B (zh) 使用薄晶粒和金屬基材之半導體晶粒封裝
JP4195380B2 (ja) 冷却を改善した半導体デバイスのパッケージ
US7838978B2 (en) Semiconductor device
JP2011171768A (ja) 半導体ダイ・パッケージ及びその製造方法
KR20040111395A (ko) 웨이퍼 레벨의 코팅된 구리 스터드 범프
WO2006076143A2 (en) Semiconductor die package including universal footprint and method for manufacturing the same
JP2001085368A (ja) 半導体ダイと概ね同じ大きさのフットプリントを有する半導体デバイス用パッケージ及びその製造プロセス
JP2005506691A5 (zh)
JP2008502156A (ja) 接触抵抗が低減された半導体デバイス
JP4829224B2 (ja) 表面実装のためのフロント接点の形成
US20200365483A1 (en) Plating for thermal management
US20080296690A1 (en) Metal interconnect System and Method for Direct Die Attachment
US11222858B1 (en) Semiconductor package having enlarged gate pad and method of making the same
US20240112992A1 (en) Semiconductor device and method for manufacturing semiconductor device
JP2024042182A (ja) 半導体装置、および半導体装置の製造方法
TW201301454A (zh) 雙面外露的半導體裝置及其製造方法