CN101904004B - 晶圆级芯片尺寸封装及制造方法 - Google Patents

晶圆级芯片尺寸封装及制造方法 Download PDF

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CN101904004B
CN101904004B CN200980101261XA CN200980101261A CN101904004B CN 101904004 B CN101904004 B CN 101904004B CN 200980101261X A CN200980101261X A CN 200980101261XA CN 200980101261 A CN200980101261 A CN 200980101261A CN 101904004 B CN101904004 B CN 101904004B
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wafer
electrode
semiconductor
liner
manufacturing
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CN101904004A (zh
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冯涛
弗兰茨娃·赫尔伯特
孙明
何约瑟
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Ltd
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Abstract

本发明涉及一种功率半导体的晶圆级芯片尺寸封装(wafer level chipscale package；CSP)及制造方法，晶圆级芯片尺寸封装包含源极、栅极与漏极，且所有的源极、栅极与漏极都位于装置的一侧，以便于利用锡膏来安装到印刷电路板(PCB)上。

Description

晶圆级芯片尺寸封装及制造方法
技术领域
本发明涉及一种半导体封装结构，特别是指一种低成本的晶圆级芯片尺寸封装(wafer level chip scale package；WLCSP)的制程。 
背景技术
半导体装置通常具备低的封装阻抗与良好的热效能。特殊的例子为金属氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistor；MOSFET)装置，尤其垂直式传导功率金属氧化物半导体场效应晶体管(MOSFET)装置，其在半导体芯片的一个表面具有栅极与源极，并在该表面的对面具有漏极。而半导体装置的封装制程，一般期望能够利用简单、快速与有效率的方法。因此，已经有许多的封装构想与方法陆续被发展出来。 
在过去十年，硅制程技术已经大幅演进，而有数十年之久的一样的封装技术及主要的封装手段却一直延续到现在。利用封胶或焊锡所进行的晶粒贴附以及用铝或金来打线接合到导线框架，仍然为目前主流的半导体封装方法。然而，半导体制程技术的演进，将会使得寄生效应(Parasitics)(比如电阻、电容及电感)伴随着具有许多效能限制因素的传统封装技术而产生。由传统覆晶技术的例子来说，其中一项缺点是不容易电性连接至晶粒的背侧。这些限制在比如为功率切换装置的高电流应用上会变得相当明显。 
美国专利第6,767,820号揭露一种半导体金属氧化物半导体栅极控制(MOS-gated)装置的晶圆级芯片尺寸封装。金属氧化物半导体栅极控制(MOS-gated)装置晶圆的源极侧是由钝化层所覆盖，钝化层的选择可选自光敏性液态树脂(photosensitive liquid epoxy)、或氮化硅(silicon nitride)薄膜之类等等为较佳。然后，将钝化层材料干燥，而披覆有钝化层的晶圆是使用标准的光微影技术进行曝光，将晶圆显影并在钝化层上产生开孔，使得下方的源极金属产生若干个露出的表面区域以及相似的开孔，并露出在晶圆上每一个晶粒的下方的栅极。钝化层的开孔的制作通常是穿过公知的钝化层下方 的可焊接的金属，比如为钛(titanium)、钨(tungsten)、镍(nickel)、或银(silver)。在开孔形成之后，晶圆就会接着进行切割或者用不同方法来分开为单独的晶粒。然后，晶粒上可焊的漏极侧就会连接到U型或杯型漏极夹片(clip)，使用导电封胶或焊锡或类似的组件，以接合晶粒的底部漏极至漏极夹片。 
美国公开第2003/0052405号公开了一种垂直式功率金属氧化物半导体场效应晶体管(MOSFET)装置，其具有漏极，该漏极形成于硅衬底的底表面并连接至漏极上方的导线框架，而栅极与源极则在该装置的底部露出。此金属氧化物半导体场效应晶体管(MOSFET)装置是以树脂进行封合，树脂比如为环氧树脂(epoxy)或硅有机树脂(silicone)，使得金属氧化物半导体场效应晶体管(MOSFET)装置与导线框架的内部被覆盖住。在金属氧化物半导体场效应晶体管(MOSFET)装置的底表面，合成树脂的表面大约和导线框架与栅极/源极的表面齐平。也就是说，在半导体装置的底表面上，导线框架的外导线部份的底表面与栅极/源极的底表面是露出来的，以连接至封装衬底的一个导电部位(封装表面)。然后，这些栅极/源极的周围会由树脂所覆盖。 
美国专利第6,133,634号揭露一种具有功率金属氧化物半导体场效应晶体管(MOSFET)装置的覆晶封装，其包含有漏极端、源极端与栅极端。漏极端连接至导电载体与焊接锡球的外部数组，源极端与栅极端则连接至焊接锡球的内部数组。导电载体与焊接锡球的外部数组提供了印刷电路板和漏极端之间的电性连接。 
美国专利第6,469,384号揭露一种半导体装置的封装方法，半导体装置比如为金属氧化物半导体场效应晶体管(MOSFET)装置，它并不需要成型机构。金属氧化物半导体场效应晶体管(MOSFET)装置是键合至衬底，使得晶粒的源极区域与栅极区域可以键合至衬底。金属氧化物半导体场效应晶体管(MOSFET)装置安装在印刷电路板(PCB)上，且晶粒的表面是使用了锡胶或合适的电性传导内连接物质来直接键合到印刷电路板(PCB)上，并作为漏极的连接。晶粒的表面键合在衬底上，衬底包含有晶粒的栅极区域与源极区域。因此，在衬底的栅极区域上的焊接锡球是用来将晶粒的栅极区域键合至印刷电路板(PCB)，同时，持续将焊接锡球经由衬底键合晶粒的源极区域到印刷电路板(PCB)上。
前面所提到的现有技术对于垂直式功率金属氧化物半导体场效应晶体管(MOSFET)装置的封装设计，可以提供给单独的金属氧化物半导体场效应晶体管(MOSFET)的源极、栅极与漏极的电性内连接。然而，在晶圆被分开为单独的晶粒之后，将需要额外的安装步骤。此外，用来提供给从晶粒的背面到前面的漏极接触的金属夹片的使用，会缩小在印刷电路板(PCB)上的晶粒的可用空间。所以期望发展一种封装设计与制造它的程序，可以让晶圆级制程具有较低成本并缩短每个部份的步骤。 
以下结合本发明的具体实施方式进行说明。 
发明内容
本发明提供了一种半导体装置，该装置可以让晶圆级制程具有较低成本并简化每个部份的步骤，使得半导体装置的晶圆等级芯片封装更加简化、有效率且成本降低。 
为了达到上述目的，本发明提供了一种半导体装置，其包含： 
半导体衬底，其具有第一衬垫与第二衬垫，该第一衬垫与第二衬垫分别电性连接至位于该半导体衬底前面的第一区域与第二区域； 
第一电极，其电性连接至所述的第一衬垫； 
第二电极，其电性连接至所述的第二衬垫；以及 
第三电极，其包含传导层，该传导层位于修整边缘(trimmed corner)的侧壁并延伸到该半导体衬底的背面，其中该传导层电性连接至位于该半导体衬底背面的第三区域。 
所述的半导体装置包含垂直式功率金属氧化物半导体场效应晶体管(vertical power MOSFET)。所述的第一区域包含源极区域，所述的第二区域包含栅极区域，且所述的第三区域包含漏极区域。所述的源极区域与栅极区域位于邻近该半导体衬底的前面，该漏极区域位于邻近该半导体衬底的背面。 
所述的第一电极、第二电极与第三电极是由同一种导电材料所制成。 
所述的第一电极、第二电极与第三电极是由选自铜或化学镀镍/金层的群组组合的导电材料所制成。 
所述的第三电极还包含传导层，该传导层延伸至该半导体衬底的前部。 
所述的第三电极的设置使得所述的传导层延伸覆盖于该半导体衬底前部 的主动区域。 
所述的半导体装置安装在印刷电路板上，并使得该第一电极、第二电极与该第三电极由于相对及电性接触该印刷电路板上的对应连接处，以形成该印刷电路板至该第一电极、第二电极与该第三电极之间的电性连接。 
另外，本发明还提供了一种制造若干半导体装置的方法，其步骤包含： 
a)提供晶圆，该晶圆包含若干半导体晶粒，其中每个半导体晶粒包含第一衬垫与第二衬垫，该第一衬垫电性连接至第一区域，该第二衬垫电性连接至位于该晶圆前表面的第二区域与位于该晶圆背表面的第三区域； 
b)形成若干穿孔，所述穿孔穿过该晶圆并位于所述的半导体晶粒之间的交叉点(corner intersections)；以及 
c)形成传导层，该传导层位于该晶圆的底表面与所述穿孔的侧壁上并延伸至该晶圆的前表面。 
进一步地，该步骤b)包含： 
沉积光阻掩膜，使其覆盖于该晶圆的前表面，其中，该光阻掩膜包含 
若干孔洞，其中每个孔洞位于所述半导体晶粒之间的交叉点；以及 
透过该光阻掩膜上的孔洞去蚀刻该晶圆，以形成若干穿孔穿过该晶圆。 
进一步地，所述步骤还包含移除该光阻掩膜。 
进一步地，所述步骤还包含研磨该晶圆的背表面至预定厚度。 
所述步骤还包含：在步骤b)之后且步骤c)之前，等向性蚀刻该晶圆，以在该晶圆的背表面形成具有圆角的所述穿孔。 
所述步骤c)还包含在该晶圆的底表面与所述穿孔的侧壁上沉积第一传导层并利用掩膜覆盖该晶圆的上表面。 
所述步骤还包含化学镀第二传导层于该第一衬垫与该第二衬垫上以及该第一传导层上。 
所述第二传导层包含若干化学镀镍/金(Ni/Au)层。 
所述该步骤还包含：在步骤c)之后，切割该晶圆以形成若干独立的半导体装置。 
进一步地，所述步骤还包含： 
在步骤b)之前且步骤a)之后，在该晶圆的前表面上沉积种子层；以及 
在该种子层上形成若干孔洞，其中每一个孔洞位于所述的半导体装置 结构之间的交叉点。 
所述步骤还包含在该种子层上电镀铜。 
所述步骤还包含蚀刻该种子层的背面。 
所述的传导层包含电镀铜。 
所述步骤还包含：在步骤b)之后且步骤c)之前，在所述晶圆的背表面及所述穿孔的侧壁上沉积种子层。 
所述步骤c)所述的形成传导层包含：在位于该晶圆的底表面与所述穿孔的侧壁上并延伸至该晶圆的前表面上，沉积钛薄层，然后，沉积铝合金层，最后化学镀镍/金。 
本发明提供的半导体装置，源极、栅极与漏极使用相同金属来连接，使得制程被简化并且降低成本。而且，由于本发明的装置避免使用金属接触垫，比如金属帽或是其它结构，或是贴片切割制造程序来提供半导体装置晶圆的前面与后面之间的衬垫。且，在晶圆尚未被切割为单独装置芯片时，允许半导体装置的前面、背面形成电性接点。本发明提供的制程方法使得半导体装置的晶圆等级芯片封装更加简化、有效率且成本降低。 
附图说明
参考以下附图和具体实施方式的描述可以清楚明了本发明的其他目的和优点： 
图1A是根据本发明的一个实施例的半导体装置的前面(源极与栅极面)的示意图； 
图1B是根据本发明图1A的半导体装置的背面(漏极面)的示意图； 
图1C是根据本发明的一个实施例的半导体装置的前面的可替代结构的示意图； 
图2A～图2Q是根据本发明的一个实施例的制造图1A～图1B的垂直式功率金属氧化物半导体场效应晶体管(MOSFET)的晶圆级芯片尺寸封装的程序的示意图； 
图3A～图3I是根据本发明的另一个实施例的制造图1C的垂直式功率金属氧化物半导体场效应晶体管(MOSFET)的晶圆级芯片尺寸封装的可替代程序的示意图；以及 
图4A～图4B是本发明将在图1C中的垂直式功率金属氧化物半导体场 效应晶体管(MOSFET)的晶圆级芯片尺寸封装安装到印刷电路板上的可替代程序的示意图。 
具体实施方式
以下的详细说明包含的具体细节是为了阐述本发明的目的，本领域的普通技术人员应该理解为对下述实施例的任何变动和修饰都包含在本发明的范围中。相应地，以下描述的发明的实施例并非用以限制本发明的申请专利范围，仅为配合图式说明阐述本发明的中心思想，而主张的权利范围为后续的申请专利范围中。 
图1A～图1B是根据本发明的一个较佳实施例的半导体装置100的前面和背面的示意图。本实施例中，半导体装置100可以为垂直式功率金属氧化物半导体场效应晶体管(MOSFET)。如图1A所示，源极(S)108与栅极(G)110设置在半导体装置100的前面，并穿过在钝化层102上的开口窗口来连接到源极(S)108与栅极(G)110下方的源极衬垫与栅极衬垫，而钝化层102沉积在由半导体材料(比如，硅)所制成的半导体衬底112上。源极衬垫与栅极衬垫连接到位于垂直式功率金属氧化物半导体场效应晶体管(MOSFET)的前面的源极区域与栅极区域，且垂直式功率金属氧化物半导体场效应晶体管(MOSFET)具有漏极区域，而漏极区域通常位在该半导体装置100的背面。在如图1A所示的例子中，漏极(D)107可以设置在半导体装置100的前面的修整边缘(trimmed corner)106。如图1A～图1B所示，通过在半导体衬底112背面以及半导体衬底112的侧壁105上方的修整边缘106处的电性传导层104，漏极(D)107与邻近半导体装置100背面的漏极区域电性连接。传导层104可以使用比如为铜(Cu)的金属，利用选择性电镀方法来镀在半导体装置100的多个部位上，或者，使用比如为镍/金(Ni/Au)的金属组合物，利用化学镀方法来镀在所选择的半导体装置100部位上。镍/金包含一层镍，以及包含一层相当薄的金在镍上面用来防止氧化。漏极107的安装可以延伸过被钝化层所覆盖的半导体装置前面的部份主动组件区域114，这样的安装方法可使得主动组件区域的损失最小化，也可以形成较大的源极108与栅极110的区域，并且获得较小的阻抗。在一些实施例中，漏极107可以予以省略，且可以透过修整边缘(trimmed corner)106侧壁上的传导层104来电性连接到漏极区域，如图1C所示。 
图2A～图2P是根据图1A～图1B中所描述的类型的半导体装置(例如，垂直式功率金属氧化物半导体场效应晶体管(MOSFET))的晶圆级芯片封装制程的一个实施例的示意图。如图2A所示，其步骤首先在衬底206上方制作若干个组件构造。根据本实施例，衬底206可以是半导体晶圆，比如硅晶圆，其包含有若干半导体晶粒。钝化层(图中未示)可以沉积在衬底206上，且栅极衬垫(G)202与源极衬垫(S)204通过半导体晶圆上表面的钝化层上的窗口开口而露出来。金属种子层208沉积在衬底206上表面的多个选择的部位，并覆盖住栅极区域(G)202与源极区域(S)204，如图2B所示。种子层208可以是一层薄的金属或是金属合金层，用来和之后会沉积在种子层208上方的金属材料相匹配。根据本发明的实施例，金属材料为铜(Cu)作为电极材料，种子层208可以由一层钛铜所形成，且其厚度少于4微米(μm)。通过掩膜采用蚀刻方法在种子层208上形成多个孔洞210，如图2C所示。接着，如图2D所示，光阻掩膜212设置在种子层208之上。光阻层212可以通过在栅极衬垫202与源极衬垫204上的多个开口而被图案化。厚的金属层214可以镀在种子层208上，以形成栅极213与源极215，如图2E所示。根据本发明的实施例，铜(Cu)可以电镀在种子层208上，并具有少于1微米(μm)的厚度，而在光阻层212的开口处的铜镀层厚度最好大于10微米(μm)。衬底206可以将背面研磨(back grinded)到预期的厚度，如图2f所示，并以少于400微米(μm)为较佳。 
在背面研磨之后，可以透过衬底206来蚀刻形成一个或更多的穿孔211，如图2G所示，比如，使用光阻层212与厚金属层214(比如，掩膜)。图2N是图2G所描述的具有穿孔211的晶圆的俯视或仰视图。然后，衬底206可以进行等向性蚀刻，例如，在氧化物蚀刻(湿式操作)之后接着等向性硅蚀刻，以在衬底206的背面形成具有圆形边缘209的穿孔211，如图2H所示。这会使得在后续步骤中在穿孔211的背面和内壁上所形成的传导层的机械强度增加且不均匀度得到改善。另外，金属种子层216在衬底216的背面与穿孔211的侧壁形成，如图2I所示。 
一层厚的金属层218，比如，铜可以被镀在种子层216上，如图2J所示。然后，光阻层212会在蚀刻种子层208之后被移除掉，如图2K～图2L所示，以形成分离的栅极217与源极219，其分别位于栅极衬垫202与源极衬垫204上。图2O～图2P，为图2L中所描述的晶圆的俯视图与仰视图。如图2O所示，漏极214位于每个金属氧化物半导体场效应晶体管(MOSFET)结构的角落处，并且部分覆盖住半导体装置的一些主动区域215。漏极214是通过覆盖在穿孔211的背面与侧壁的金属层218，而与邻近半导体衬底206背面的漏极区域电性连接。
然后，如图2M所示，将晶圆切割成单独的半导体装置220。切割的过程中是将穿孔211切开，但保留了穿孔211的侧壁部位以及镀在侧壁的金属层218的对应部位，以提供背面漏极区域与漏极214之间的电性内连接。 
穿孔211并不限定为圆形样式。比如，图2Q会是一种本发明的可替代实施例，其中穿孔211具有非圆形样式，而是替代的加号(plus-sign)形状。穿孔211的其它样式均在本发明的实施例所保护的范围内。 
图3A～图3I是一种制造半导体装置的功率晶圆级芯片尺寸封装的可替代程序的示意图。如图3A所示，晶圆包含若干半导体装置结构(比如，垂直式功率金属氧化物半导体场效应晶体管(MOSFETs))，半导体装置结构则包含半导体衬底306。钝化层(图中未示)可以沉积在硅衬底306上，且栅极衬垫(G)302与源极衬垫(S)304通过晶圆上表面的钝化层上的开口窗口露出。 
光阻掩膜308沉积在晶圆的上表面，并覆盖住栅极区域(G)302与源极区域(S)304以及位于两个或更多的结构之间的交叉点的孔洞310，如图3B所示。然后，衬底306可以背面研磨至预期的厚度，如图3C所示。 
 透过孔洞310来蚀刻衬底306，以形成穿孔311，如图3D所示。然后，将硅衬底306进行等向性蚀刻，比如，在氧化物蚀刻(湿式操作)之后接着使用硅蚀刻，以在衬底306的背面形成圆形边缘309的穿孔311，如图3E所示。在衬底306的背侧以及穿孔311形成第一金属层312，且该第一金属层312覆盖在穿孔311的侧壁，如3F图所示。根据本发明的实施例，第一金属层312可以为任何适合用来化学镀镍的披覆作业的金属，比如为铝(Al)或铝合金沉积在钛(Ti)层上。第一金属层312的总厚度可以大于1微米(μm)，并以大于3微米(μm)为较佳。在形成第一金属层312之后，光阻掩膜308接着会被移除掉，如图3G所示。第二金属层314，比如为化学镀镍/金(Ni/Au)，化学镀在第一金属层312上，如图3H所示。根据本发明的实施例，镍的厚 度可以在1～10微米(μm)之间，且金的厚度可以小于1微米(μm)，且总厚度小于11微米(μm)。形成第二金属层314的步骤可以仅为一个，将金属成长在栅极衬垫302、源极衬垫304上方并覆盖住金属层312，来形成栅极313、源极315与漏极317。最后，将晶圆分割以形成单独的垂直式功率金属氧化物半导体场效应晶体管(MOSFET)316，如图3I所示。 
对比公知的制程，包含栅极、源极的前面通常与后面分隔开来，因此，在前面金属沉积时，后面需要被保护，且前面与后面使用不同的金属沉积。前面通常使用铝-硅-铜合金，而后面使用铝，导致在固定到电路板上时难以焊接。而上述的实施例，源极、栅极与漏极使用相同金属来连接，使得制程被简化并且降低成本。 
图4A～图4B为本发明将在图1C中的垂直式功率金属氧化物半导体场效应晶体管(MOSFET)的晶圆级芯片尺寸封装安装到印刷电路板上的可替代程序的示意图。 
如图4A所示，在图1C中描绘的晶圆级芯片尺寸封装(WLCSP)400，其前面的栅极402、源极404以及侧壁的漏极406可键合到电路板401上，通过覆晶方式将装置设置在电路板401上后，锡胶408可以沉积在电路板401的电极410上。接着，锡胶408回焊而形成栅极402、源极404、漏极406以及电路板401的相对应电极410之间的电性内连接，如图4B所示。回焊后，锡胶408也可以在修整边缘的侧壁上润湿漏极金属电极406，以形成小的阻抗。 
本发明所提出的上述实施例，避免使用金属接触垫，比如金属帽或是其它结构，或是贴片切割制造程序来提供半导体装置晶圆的前面与后面之间的衬垫。且本发明实施例，在晶圆尚未被切割为单独装置芯片时，允许半导体装置的前面、背面形成电性接点。本发明提供的实施例使得半导体装置的晶圆等级芯片封装更加简化、有效率且成本降低。 
尽管上述实施方式所阐述为垂直功率金属氧化物半导体场效应晶体管(MOSFET)装置，但是本发明同样也可以应用于其它各种的垂直半导体装置，比如为绝缘栅双极晶体管(Insulated Gate Bipolar Transistor，IGBT)、或是底部源极的金属氧化物半导体场效应晶体管(MOSFET)装置、双极功率晶体管等。 
上述说明为本发明的较佳实施例，还可以对这些实施例进行各种变化、修饰或等同替代。因此，本发明的范围应该认为不是限于上述说明，而是参考附上的权利要求及其等同替代方式。任何特征可以组合其他特征。在下面的权利要求中，没有特别指明数量的，均指的是可以一个或者多个。除了在权利要求中使用“指的是”明确指出，权利要求不应被解释为局限于功能或手段限制。 

Claims (24)

1.一种半导体装置，其包含：
半导体衬底，其具有第一衬垫与第二衬垫，该第一衬垫与第二衬垫分别电性连接至位于该半导体衬底前面的第一区域与第二区域；
第一电极，其电性连接至所述的第一衬垫；
第二电极，其电性连接至所述的第二衬垫；以及
第三电极，其包含传导层，该传导层位于半导体衬底的修整边缘的侧壁并延伸到该半导体衬底的背面，其中该传导层电性连接至位于该半导体衬底背面的第三区域。
2.如权利要求1所述的半导体装置，其特征在于，所述的半导体装置包含垂直式功率金属氧化物半导体场效应晶体管。
3.如权利要求2所述的半导体装置，其特征在于，所述的第一区域包含源极区域，所述的第二区域包含栅极区域，且所述的第三区域包含漏极区域。
4.如权利要求3所述的半导体装置，其特征在于，所述的源极区域与栅极区域位于邻近该半导体衬底的前面，该漏极区域位于邻近该半导体衬底的背面。
5.如权利要求1所述的半导体装置，其特征在于，所述的第一电极、第二电极与第三电极是由同一种导电材料所制成。
6.如权利要求1所述的半导体装置，其特征在于，所述的第一电极、第二电极与第三电极是由选自铜或化学镀镍/金层的群组组合的导电材料所制成。
7.如权利要求1所述的半导体装置，其特征在于，所述的第三电极还包含传导层，该传导层延伸至该半导体衬底的前部。 
8.如权利要求7所述的半导体装置，其特征在于，所述的第三电极的设置使得所述的传导层延伸覆盖于该半导体衬底前部的主动区域。
9.如权利要求1所述的半导体装置，其特征在于，所述的半导体装置安装在印刷电路板上，并使得该第一电极、第二电极与该第三电极由于相对及电性接触该印刷电路板上的对应连接处，以形成该印刷电路板至该第一电极、第二电极与该第三电极之间的电性连接。
10.一种制造若干半导体装置的方法，其步骤包含：
a)提供晶圆，该晶圆包含若干半导体晶粒，其中每个半导体晶粒包含第一衬垫与第二衬垫，该第一衬垫电性连接至第一区域，该第二衬垫电性连接至位于该晶圆前表面的第二区域，该每个半导体晶粒还包含位于该晶圆背表面的第三区域；
b)形成若干穿孔，所述穿孔穿过该晶圆并位于所述的半导体晶粒之间的交叉点；以及
c)形成传导层，该传导层位于该晶圆的底表面与所述穿孔的侧壁上并延伸至该晶圆的前表面。
11.如权利要求10所述的制造若干半导体装置的方法，其特征在于，该步骤b)包含：
沉积光阻掩膜，使其覆盖于该晶圆的前表面，其中，该光阻掩膜包含若干孔洞，其中每个孔洞位于所述半导体晶粒之间的交叉点；以及
透过该光阻掩膜上的孔洞去蚀刻该晶圆，以形成若干穿孔穿过该晶圆。
12.如权利要求11所述的制造若干半导体装置的方法，其特征在于，该步骤还包含移除该光阻掩膜。
13.如权利要求10所述的制造若干半导体装置的方法，其特征在于，该步骤还包含研磨该晶圆的背表面至预定厚度。 
14.如权利要求10所述的制造若干半导体装置的方法，其特征在于，该步骤还包含：在步骤b)之后且步骤c)之前，等向性蚀刻该晶圆，以在该晶圆的背表面形成具有圆角的所述穿孔。
15.如权利要求10所述的制造若干半导体装置的方法，其特征在于，该步骤c)还包含在该晶圆的底表面与所述穿孔的侧壁上沉积第一传导层并利用掩膜覆盖该晶圆的上表面。
16.如权利要求15所述的制造若干半导体装置的方法，其特征在于，该步骤还包含化学镀第二传导层于该第一衬垫与该第二衬垫上以及该第一传导层上。
17.如权利要求16所述的制造若干半导体装置的方法，其特征在于，该第二传导层包含若干化学镀镍/金层。
18.如权利要求10所述的制造若干半导体装置的方法，其特征在于，该步骤还包含：在步骤c)之后，切割该晶圆以形成若干独立的半导体装置。
19.如权利要求10所述的制造若干半导体装置的方法，其特征在于，该步骤还包含：
在步骤b)之前且步骤a)之后，在该晶圆的前表面上沉积种子层；以及
在该种子层上形成若干孔洞，其中每一个孔洞位于所述的半导体装置结构之间的交叉点。
20.如权利要求19所述的制造若干半导体装置的方法，其特征在于，该步骤还包含在该种子层上电镀铜。
21.如权利要求20所述的制造若干半导体装置的方法，其特征在于，该步骤 还包含蚀刻该种子层的背面。
22.如权利要求10所述的制造若干半导体装置的方法，其特征在于，所述的传导层包含电镀铜。
23.如权利要求10所述的制造若干半导体装置的方法，其特征在于，该步骤还包含：在步骤b)之后且步骤c)之前，在所述晶圆的背表面及所述穿孔的侧壁上沉积种子层。
24.如权利要求10所述的制造若干半导体装置的方法，其特征在于，步骤c)所述的形成传导层包含：在位于该晶圆的底表面与所述穿孔的侧壁上并延伸至该晶圆的前表面上，沉积钛薄层，然后，沉积铝合金层，最后化学镀镍/金。 
CN200980101261XA 2008-01-31 2009-01-28 晶圆级芯片尺寸封装及制造方法 Active CN101904004B (zh)

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Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7955893B2 (en) * 2008-01-31 2011-06-07 Alpha & Omega Semiconductor, Ltd Wafer level chip scale package and process of manufacture
US8373257B2 (en) * 2008-09-25 2013-02-12 Alpha & Omega Semiconductor Incorporated Top exposed clip with window array
US8222078B2 (en) * 2009-07-22 2012-07-17 Alpha And Omega Semiconductor Incorporated Chip scale surface mounted semiconductor device package and process of manufacture
US20110075392A1 (en) * 2009-09-29 2011-03-31 Astec International Limited Assemblies and Methods for Directly Connecting Integrated Circuits to Electrically Conductive Sheets
WO2011058977A1 (ja) * 2009-11-10 2011-05-19 ローム株式会社 半導体装置および半導体装置の製造方法
US8362515B2 (en) * 2010-04-07 2013-01-29 Chia-Ming Cheng Chip package and method for forming the same
US8987878B2 (en) 2010-10-29 2015-03-24 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
US8362606B2 (en) * 2010-07-29 2013-01-29 Alpha & Omega Semiconductor, Inc. Wafer level chip scale package
CN102403236B (zh) * 2010-09-07 2015-03-04 万国半导体(开曼)股份有限公司 芯片外露的半导体器件及其生产方法
TWI427717B (zh) * 2010-12-28 2014-02-21 Alpha & Omega Semiconductor Cayman Ltd 一種倒裝晶片的封裝方法
JP6024076B2 (ja) * 2011-01-13 2016-11-09 セイコーエプソン株式会社 シリコンデバイスの製造方法
CN102122670B (zh) * 2011-01-31 2012-07-25 江阴长电先进封装有限公司 沟槽互联型圆片级mosfet封装结构及实现方法
CN102122671B (zh) * 2011-01-31 2012-09-19 江阴长电先进封装有限公司 后通孔互联型圆片级mosfet封装结构及实现方法
US8518748B1 (en) 2011-06-29 2013-08-27 Western Digital (Fremont), Llc Method and system for providing a laser submount for an energy assisted magnetic recording head
US8450188B1 (en) * 2011-08-02 2013-05-28 Micro Processing Technology, Inc. Method of removing back metal from an etched semiconductor scribe street
US8288204B1 (en) * 2011-08-30 2012-10-16 Western Digital (Fremont), Llc Methods for fabricating components with precise dimension control
CN103165524B (zh) * 2013-04-03 2015-07-15 株洲南车时代电气股份有限公司 一种igbt芯片及其正面铜金属化结构的制作方法
US20160322342A1 (en) * 2014-01-15 2016-11-03 Panasonic Intellectual Property Management Co. Lt Semiconductor device
US9666498B2 (en) 2014-06-02 2017-05-30 Qorvo Us, Inc. Ring-frame power package
US10199313B2 (en) 2014-06-02 2019-02-05 Qorvo Us, Inc. Ring-frame power package
US10008473B2 (en) 2014-06-02 2018-06-26 Qorvo Us, Inc. Power package lid
GB2534204A (en) * 2015-01-17 2016-07-20 Melexis Technologies Nv Semiconductor device with at least one truncated corner and/or side cut-out
TWI690083B (zh) * 2015-04-15 2020-04-01 杰力科技股份有限公司 功率金氧半導體場效電晶體及其製作方法
FR3040532B1 (fr) * 2015-08-31 2017-10-13 St Microelectronics Tours Sas Puce a montage en surface
US10083888B2 (en) * 2015-11-19 2018-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US10910233B2 (en) * 2018-04-11 2021-02-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN110277321B (zh) * 2019-05-30 2021-04-20 全球能源互联网研究院有限公司 功率芯片预封装、封装方法及其结构、晶圆预封装结构
CN110310931A (zh) * 2019-07-15 2019-10-08 深圳市泛宜微电子技术有限公司 一种芯片及封装元件
CN110349842A (zh) * 2019-07-24 2019-10-18 四川科尔威光电科技有限公司 一种芯片的制作方法
DE102019120886A1 (de) * 2019-08-02 2021-02-04 Infineon Technologies Ag Halbleitergehäuse mit einem Hohlraum in seinem Gehäusekörper
CN111508922A (zh) * 2020-04-26 2020-08-07 深圳市昭矽微电子科技有限公司 Mosfet芯片

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001075961A1 (en) * 2000-04-04 2001-10-11 International Rectifier Corporation Chip scale surface mounted device and process of manufacture

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4729815A (en) * 1986-07-21 1988-03-08 Motorola, Inc. Multiple step trench etching process
JP2800884B2 (ja) 1995-10-27 1998-09-21 日本電気株式会社 横型ｄｓａパワーｍｏｓｆｅｔを備えた半導体装置
US6164523A (en) * 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
JP3614030B2 (ja) * 1999-04-02 2005-01-26 株式会社村田製作所 マザー基板，子基板およびそれを用いた電子部品ならびにその製造方法
KR100608611B1 (ko) * 1999-06-02 2006-08-09 삼성전자주식회사 비아 홀을 이용한 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법
EP1258040A4 (en) * 2000-02-10 2009-07-01 Int Rectifier Corp VERTICAL-CONDUCTING PROTUBERANCE CHIP WITH CONTACT PLOTS ON ONE SURFACE
US6355502B1 (en) * 2000-04-25 2002-03-12 National Science Council Semiconductor package and method for making the same
US6469384B2 (en) * 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6646329B2 (en) * 2001-05-15 2003-11-11 Fairchild Semiconductor, Inc. Power chip scale package
JP3868777B2 (ja) * 2001-09-11 2007-01-17 株式会社東芝 半導体装置
US6784540B2 (en) * 2001-10-10 2004-08-31 International Rectifier Corp. Semiconductor device package with improved cooling
TWI271866B (en) * 2005-05-18 2007-01-21 Au Optronics Corp Thin film transistor and process thereof
US7585750B2 (en) * 2007-05-04 2009-09-08 Stats Chippac, Ltd. Semiconductor package having through-hole via on saw streets formed with partial saw
US7955893B2 (en) * 2008-01-31 2011-06-07 Alpha & Omega Semiconductor, Ltd Wafer level chip scale package and process of manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001075961A1 (en) * 2000-04-04 2001-10-11 International Rectifier Corporation Chip scale surface mounted device and process of manufacture

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TW200937590A (en) 2009-09-01
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US8981464B2 (en) 2015-03-17
WO2009099834A3 (en) 2009-10-01
TWI399836B (zh) 2013-06-21
US20140239383A1 (en) 2014-08-28
US20090194880A1 (en) 2009-08-06
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US7955893B2 (en) 2011-06-07
US8716063B2 (en) 2014-05-06

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