CN213519943U - 半导体器件组件及堆叠晶体管组件 - Google Patents

半导体器件组件及堆叠晶体管组件 Download PDF

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Publication number
CN213519943U
CN213519943U CN202022228941.4U CN202022228941U CN213519943U CN 213519943 U CN213519943 U CN 213519943U CN 202022228941 U CN202022228941 U CN 202022228941U CN 213519943 U CN213519943 U CN 213519943U
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mounting clip
mounting
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semiconductor device
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杰弗里·P·甘比诺
大卫·T·普赖斯
杰弗里·A·尼尔斯
迪安·E·普罗布斯特
桑托什·梅农
P·A·伯克
比基尔迪斯·多斯多斯
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

本实用新型涉及半导体器件组件及堆叠晶体管组件。本实用新型公开了一种半导体器件的堆叠组件，该堆叠组件包括：安装焊盘，该安装焊盘覆盖低侧半导体器件的第一部分；和接触层，该接触层覆盖该低侧半导体器件的第二部分。与该接触层电连接的第一安装夹具有支撑部分，该支撑部分将该第一安装夹连结到第一引线框架部分。与该安装焊盘附接的第二安装夹具有支撑部分，该支撑部分将该第二安装夹连结到第二引线框架部分。高侧半导体器件具有：第一端子，该第一端子电连接到该第一安装夹并由此电连接到该接触层；和第二端子，该第二端子电连接到该第二安装夹。

Description

半导体器件组件及堆叠晶体管组件
技术领域
本说明书涉及用于半导体器件的封装技术，具体涉及半导体器件组件及堆叠晶体管组件。
背景技术
增加半导体器件(诸如晶体管)的封装件内的器件密度使得能够更有效地使用封装件内的可用空间。可例如通过减小单个器件的尺寸或通过将更多数量的器件装配在可用封装件空间内来增加器件密度。
在后一种情况下，例如，可以构造器件的3维(3D)组件。例如，可以将一个晶体管堆叠在另一晶体管上面。具体地，将彼此结合操作的两个晶体管堆叠以在较大电路中提供一个或多个功能可能是有效的。
然而，安装、布线和以另外的方式封装3D器件组件可能是具有挑战性的。例如，此类3D器件组件可能易于受短路和结构组件的影响。在其他示例中，3D器件组件可能需要专门的、昂贵的和/或耗时的制造技术。
实用新型内容
本实用新型旨在提供一种半导体器件组件及堆叠晶体管组件，其具有增加的器件密度且能够提供结构稳定性和完整性。
根据一个一般方面，一种半导体器件组件包括：低侧半导体器件；安装焊盘，该安装焊盘覆盖低侧半导体器件的第一部分；和接触层，该接触层覆盖低侧半导体器件的第二部分。该组件还包括：第一安装夹，该第一安装夹通过其连接部分电连接到接触层，该第一安装夹具有支撑部分，该支撑部分将第一安装夹的连接部分连结到第一引线框架部分；和第二安装夹，该第二安装夹通过其连接部分附接到安装焊盘，该第二安装夹具有支撑部分，该支撑部分将第二安装夹的连接部分连结到第二引线框架部分。该组件还包括高侧半导体器件，该高侧半导体器件具有第一端子，该第一端子电连接到第一安装夹并由此电连接到该接触层，并且具有第二端子，该第二端子电连接到第二安装夹。
根据另一个一般方面，一种堆叠晶体管组件包括：低侧晶体管，该低侧晶体管具有低侧源极触点、低侧栅极触点和低侧漏极触点；和高侧晶体管，该高侧晶体管安装在低侧晶体管上面并且具有高侧源极触点、高侧栅极触点和高侧漏极触点。该堆叠晶体管组件包括：安装焊盘，该安装焊盘覆盖低侧晶体管的第一部分；栅极安装夹，该栅极安装夹固定到安装焊盘并固定到高侧栅极触点；接触层，该接触层覆盖低侧晶体管的第二部分并提供低侧漏极触点；和源极安装夹，该源极安装夹电连接到接触层和高侧源极触点。
根据另一个一般方面，一种半导体器件组件包括：低侧器件组件，所述低侧器件组件包括覆盖所述低侧器件组件的第一部分的安装焊盘和覆盖所述低侧器件组件的第二部分的接触层，所述低侧器件组件被放置于引线框架上；高侧器件组件，所述高侧器件组件具有第一端子和第二端子；第一安装夹，所述第一安装夹附接在所述引线框架与所述安装焊盘之间；和第二安装夹，所述第二安装夹附接在所述引线框架与所述接触层之间；其中所述高侧器件组件被定位成所述第一端子连接到所述第一安装夹并且所述第二端子连接到所述第二安装夹。
本实用新型提供的半导体器件组件及堆叠晶体管组件，实现了增加的器件密度且能够提供结构稳定性和完整性。
一个或多个具体实施的细节在附图和以下描述中阐明。其他特征将从说明书和附图中以及从权利要求书中显而易见。
附图说明
图1A示出了根据一些示例性实施方式的具有双中间安装夹的堆叠晶体管组件的简化横截面。
图1B示出了具有图1A的双中间安装夹的堆叠晶体管组件的更详细横截面。
图2示出了图1B的堆叠晶体管组件的顶视图。
图3是图1B和图2的堆叠晶体管组件的第二横截面。
图4示出了根据一些示例性实施方式的具有双中间安装夹的堆叠晶体管组件的第二实施方式的第一横截面。
图5示出了图4的堆叠晶体管组件的顶视图。
图6是图4和图5的堆叠晶体管组件的第二横截面。
图7是示出用于构造图1至图6的堆叠晶体管组件的示例性操作的流程图。
图8示出了用于图7的对应操作的实施方式的第一示例性工艺步骤。
图9示出了用于图7的对应操作的实施方式的第二示例性工艺步骤。
图10示出了用于图7的对应操作的实施方式的第三示例性工艺步骤。
图11示出了用于图7的对应操作的实施方式的第四示例性工艺步骤。
图12示出了用于图7的对应操作的实施方式的第五示例性工艺步骤。
图13是具有双中间安装夹的堆叠晶体管组件的第三示例性实施方式的横截面。
图14示出了用于制造图13的示例的实施方式的第一示例性工艺步骤。
图15示出了用于制造图13的示例的实施方式的第二示例性工艺步骤。
具体实施方式
如下文所详述，实施方案包括使用多个安装夹竖直安装并电连接的堆叠器件，诸如晶体管。例如，可提供至少两个安装夹，该至少两个安装夹至少部分地介于至少两个堆叠晶体管之间或在该至少两个堆叠晶体管的中间。安装夹实现晶体管和其他器件的快速、廉价的3D封装，在一些示例中包括标准焊料连接的用途。
使用本文所述的技术，使用为晶体管的3D堆叠组件提供结构稳定性和完整性的至少一个安装焊盘来附接多个安装夹。该至少一个安装焊盘还可确保防止多个安装夹彼此接触，使得避免封装件内的短路。该至少一个安装焊盘本身可与该组件内的电连接件隔离。
图1A示出了根据一些示例性实施方式的具有双中间安装夹的堆叠晶体管组件的简化横截面。图1B示出了具有图1A的双中间安装夹的堆叠晶体管组件的更详细的示例性横截面。如下文所详述，图1B提供了图2所示的顶视图的横截面A-A'，而图3提供了图2的横截面B-B'。
因此，图1A示出了低侧晶体管102，高侧晶体管104堆叠在该低侧晶体管上面。低侧晶体管102和高侧晶体管104的操作可由控制器(例如，控制芯片或控制电路)106(如图1B所示)控制。
在图1A中，低侧晶体管102安装在第一引线框架部分110上。可包括如下所述和所示的多个层的安装焊盘135覆盖低侧晶体管102的第一部分。接触层126覆盖低侧晶体管102的第二部分。
还如图所示，第一安装夹120通过其连接部分120b电连接到接触层126。第一安装夹120具有支撑部分120a，该支撑部分将第一安装夹120的连接部分120b连结到第一引线框架部分108。同时，第二安装夹122通过其连接部分122b附接到安装焊盘135。在图1A和图1B的横截面中不可见，但在图2中示出，第二安装夹122具有支撑部分122a，该支撑部分将第二安装夹122的连接部分122b连结到第二引线框架部分。
高侧晶体管104具有与第一安装夹120耦接的第一端子，诸如源极端子，并且电连接到第一安装夹120并由此电连接到接触层126。高侧晶体管104具有第二端子，诸如栅极端子，该第二端子与第二安装夹122耦接并且电连接到第二安装夹。
在图1A中，如上文所提及的，安装焊盘135为图1A的堆叠晶体管组件的结构提供结构稳定性和完整性。安装焊盘135实现并促进在堆叠晶体管102、104之间或在该堆叠晶体管的中间使用安装夹120、122，使得可以有效且廉价地执行图1A的堆叠组件的制造和组装。此外，安装焊盘135限定并确保间隙152，该间隙提供夹120、122之间的电隔离，并且由此避免晶体管102、104的端子之间的任何非期望的连接或短路。
如已经提及的，图1B提供了与图1A相对应的更详细的示例性横截面，并且对于对应的元件使用图1A的相同的附图标记。在图1B中并且在本文提供的后续示例中，术语“竖直”应被理解为是指与芯片、管芯、电路板或任何合适的安装框架的平坦表面或区域垂直的方向，堆叠晶体管组件可安装在该安装框架上。此外，术语“低”和“高”(和类似术语，诸如上/下或上面/下面)应被理解为是指沿此竖直方向的相对位置或距离。因此，术语“水平”是指与竖直方向垂直的方向或平坦表面或区域，而术语“对角线”可指具有竖直分量和水平分量两者的任何方向。
在图1B中，多个引线框架或引线框架部分108、110、112可提供对控制器106和晶体管102、104以及它们之间的电连接件的物理支撑。例如，此类引线框架通常被实施为用于在芯片封装件内部的管芯与外部电路之间提供电连接的金属结构。在一些实施方式中，对应的焊料层114、116、118可用于将引线框架108、110、112连接到晶体管102、104或控制器106。
金属安装夹120被示出为包括对角线部分120a和至少部分地位于晶体管102、104之间的水平部分120b。第二安装夹122在图1B中被示出为包括至少部分地位于晶体管102、104之间的水平部分122b，其中对角线部分122a在图2中可见。
例如，安装夹120、122可表示铜夹。铜夹可用于提供优于引线键合方法的多个优点，包括特别是对于电力电子器件和高频应用而减小封装件的总电阻和热阻抗。
在图1B的示例中，如图所示并且如使用本文所述的技术构造的，安装夹120和安装夹122两者可各自包括在低侧晶体管102与高侧晶体管104之间或在该低侧晶体管与高侧晶体管的中间的至少一部分(例如，水平部分120b、122b的各部分)。水平部分120b、122b为图1B的堆叠晶体管组件提供结构支撑和完整性，同时保持彼此电隔离。更一般地，图1B的结构实现了晶体管102、104、控制器106和引线框架108、110之间的所有必要的电连接。图1B的结构还确保夹120、122之间的电隔离，并且类似地，避免晶体管102、104之间或者在其他情况下在图1B的堆叠组件内(诸如在夹122与低侧漏极触点126之间，如下所述)的任何短路。
在图1B和以下描述中，晶体管102、104被示出并描述为竖直场效应晶体管，每个效应晶体管具有栅极、源极和漏极。然而，也可使用其他类型的晶体管或半导体器件。此外，在本说明书中未详细描述包括晶体管102、104(例如，沟道或掺杂区域)的任何此类器件的内部结构或操作细节。
尽管如此，但是出于解释图1B的堆叠组件的目的，低侧晶体管102被示出为包括低侧源极触点124和低侧漏极触点126。低侧晶体管102还包括低侧栅极触点，该低侧栅极触点在图1B中不可见，但在图2中被示出为低侧栅极触点214。类似地，高侧晶体管104包括高侧源极触点128、高侧栅极触点130和高侧漏极触点132。
因此，引线框架110可被理解为表示由焊料层116连结到低侧源极触点124的低侧源极引线框架。低侧源极触点支撑低侧晶体管102。在低侧源极触点124位于低侧漏极触点126下面的情况下，低侧晶体管102可被称为朝下晶体管。
此外，在图1B中，示出了低侧漏极触点126与绝缘层136之间的毯覆金属层134。如图1B所示并且如下面详细描述的，毯覆层134可跨低侧晶体管102的整个顶表面延伸，并且可将来自漏极触点126的电流跨整个低侧晶体管(包括绝缘层136下方的一部分)分流，并且由此增加通过低侧晶体管102的可用电流或将该可用电流最大化。
层138表示促进低侧漏极126与焊料层140之间的接触和连接的粘附层和润湿层中的一者或多者。例如，层138可包括被包括用于粘附到低侧漏极触点125的钛和将钛焊接到焊料层140的铜。类似地，层142可提供关于将绝缘层136粘附到焊料层144的类似功能。例如，尽管被示出为单层138/142，但此类层可使用例如大约30nm的钛层和大约150nm的铜层来形成。
通过这种方式，焊料层140可连接到安装夹120，而焊料层144可连接到安装夹122。如可从图1B观察到，并且如本文所述，安装夹122与低侧晶体管102电隔离，并且具体地与低侧漏极126电隔离。安装夹122还牢固且牢靠地与安装夹120隔离。
同时，安装夹120通过焊料层146固定到高侧源极触点，而安装夹122通过焊料层148固定到高侧源极触点。因此，高侧晶体管104整体在结构上由安装夹120、122和邻接层支撑和保持。
对于晶体管102、104的操作，控制器106可通过引线键合(在图1B中由单个引线键合150表示)连接到低侧源极触点124、低侧漏极触点126、低侧栅极触点214、高侧源极触点128、高侧栅极触点130和高侧漏极触点132中的每一者。控制器106可通过接地引线框架112接地。在其他实施方式中，引线框架112可表示与电源轨的连接。因此，可以期望方式(例如通过施加适当的栅极电压并控制行进通过高侧漏极触点132、高侧源极触点128、安装夹120、低侧漏极触点126和低侧源极触点124的电流)控制晶体管102、104的操作。
在图1B的示例中，因此形成间隙或空间152，该间隙或空间确保安装夹120、122之间的电隔离。在示例性实施方式中，间隙152可例如在50微米至100微米的范围内。如所描述的，通过将安装夹122连接到由层136、142、144中的至少一些层的组合形成的安装焊盘来牢固且牢靠地保持间隙152。即，本说明书中的术语安装焊盘应被理解为表示用于支撑安装夹122或至少部分地包括在晶体管102、104之间的类似安装夹的任何一个或多个层(例如，层136、142、144)。如所描述的，此安装焊盘将安装夹122与低侧晶体管102和与安装夹120电隔离(在后一种情况下，通过刚刚提及的间隙152电隔离)。
在图1B中，安装夹120连接到高侧源极触点128，并且可以被称为源极夹或源极侧夹。如果高侧源极触点用作输出节点，则安装夹120可被称为输出夹(OUT clip或outputclip)。类似地，当安装夹122支撑高侧栅极触点130时，安装夹122可被称为栅极夹或栅极侧夹。
在图2的顶视图中，示出了引线框架110和引线框架108，但引线框架108与安装夹120的连接、并由此与高侧源极128的连接在图2中不可见。
在图2中，控制器106被示出为具有六个端子202、204、206、208、210、212，其中的每一个引线键合连接到对应的引线框架211、212、213。具体地，引线框架211对应于例如堆叠晶体管组件的引线框架108、110、220，但为了简洁起见，图2中未示出明确的对应关系。然而，引线框架212被示出为连接到低侧栅极214，而引线框架213被示出为连接到包括对角线部分122a的安装夹122。
此外，在图2中，低侧源极焊盘216(对应于图1中的低侧源极触点124)被透明地描绘，以便还示出高侧源极焊盘218(对应于图1中的高侧源极触点128)。最后，在图2中，引线框架220对应于与高侧漏极132附接的第三安装夹302，如图3所示。
具体地，在图3中，沿线B-B'截取的横截面示出了可使用焊料层304将第三安装夹302焊接到引线框架220。第三安装夹包括对角线部分302a，以及使用焊料层301与高侧漏极132连接的水平部分302b。
图4示出了沿线C-C'截取并且根据一些示例性实施方式的具有双中间安装夹的堆叠晶体管组件的第二实施方式的第一横截面。图5示出了图4的堆叠晶体管组件的顶视图。
在图4中，与在图1B中一样，低侧晶体管402和高侧晶体管404堆叠在引线框架406、408和410上或使用该引线框架堆叠。如图所示，引线框架406通过焊料层412附接到低侧栅极触点414。引线框架408通过焊料层416附接到低侧源极触点418。
跨低侧晶体管402的整个上表面形成毯覆金属层420。如所描述的，毯覆金属层420将电流跨整个低侧晶体管402分流，并且由此优化通过低侧晶体管402的电流。
低侧漏极触点422具有形成于其上的一个或多个粘附层/润湿层424。因此，焊料层426可牢靠地形成在一个或多个粘附层/润湿层424上。类似地，形成为与低侧漏极触点422相邻并覆盖毯覆金属层420的表面的其余部分的绝缘体层具有形成于其上的一个或多个粘附层/润湿层430。因此，焊料层432可形成在一个或多个粘附层/润湿层430上。
如进一步所示，安装夹434可附接到焊料层426和焊料层440，并且由此附接到高侧源极触点442。类似地，安装夹436可在一端通过焊料层438附接到引线框架410，并且在另一端通过焊料层444附接到高侧栅极446。如图所示，安装夹436具有对角线部分436a和水平部分436b。最后，在图4中，高侧晶体管404可具有通过焊料层449与安装夹450连接的高侧漏极触点448。
与图1B的示例一样，图4的示例提供将夹434、436分开的间隙452。同样与图1B一样，安装夹436与低侧晶体管402电隔离和绝缘，同时被完全支撑并为图4的堆叠组件提供结构完整性。
在图5的顶视图中，控制器502以与图1和图2的控制器106大致对应的方式示出，并且在这里不再详细描述。图5示出了晶体管402、404和对应的源极触点418、442可以不同配置形成(例如，与图2的示例相比)。
例如，如图5所示，栅极触点414、446可彼此对准。另外，源极触点418、442可具有与本文所述的双中间安装夹技术兼容的各种配置和图案。
图6是图4和图5的堆叠晶体管组件的沿线D-D’截取的第二横截面。图6示出了顶部漏极安装夹450可通过焊料层602附接到引线框架410。安装夹450被示出为包括对角线部分450a和水平部分450b。
图7是示出用于构造图1至图6的堆叠晶体管组件的示例性操作的流程图。在图7的示例中，可形成包括安装焊盘的低侧器件组件(702)。例如，如所描述的，低侧器件可包括低侧晶体管，诸如朝下的竖直沟槽金属氧化物半导体场效应晶体管(mosfet)。安装焊盘可包括覆盖低侧器件的第一部分的绝缘层，而接触层(例如，竖直MOSFET的漏极触点)覆盖低侧器件的第二部分。
可形成高侧器件组件(704)。例如，可形成另一朝下的竖直沟槽MOSFET。
可例如使用拾取和放置工具将低侧器件组件附接到引线框架(706)。例如，可使用焊料层，诸如图1B的焊料层116或图4的焊料层412、416。如所描述的，低侧器件组件可包括安装焊盘，该安装焊盘包括绝缘层(例如，图1中的136)、粘附层/润湿层(例如，图1中的142)和焊料层(例如，图1中的144)。如上文关于图1至图6所示和所述，安装焊盘覆盖低侧器件的第一部分(例如，低侧晶体管102、402)，而接触层(例如，图1中的低侧漏极触点136)覆盖低侧器件的第二部分。
可使用拾取和放置工具来附接双中间安装夹(708)。例如，源极安装夹120可使用焊料层114和140放置，以便通过该源极安装夹的水平部分120b电连接到接触层，而对角线部分120a将源极安装夹120的水平部分120b连结到第一(源极)引线框架108。
同时，可使用焊料层144来放置栅极安装夹122。具体地，如图所示，可使用包括层136/142/144的上文提及的安装焊盘来放置栅极安装夹122。因此，类似于源极安装夹，栅极安装夹通过其水平部分122b有效地附接到安装焊盘，该第二安装夹具有将第二安装夹的水平部分122b连结到第二(栅极)引线框架213的对角线部分122a。
高侧器件组件可使用拾取和放置工具附接到双中间安装夹(710)。例如，图1B的高侧晶体管104或图4的404可使用焊料层146、148或440、444附接。因此，高侧半导体器件可具有第一端子或触点，该第一端子或触点安装在第一安装夹上并电连接到第一安装夹和接触层。例如，高侧晶体管104具有安装在源极安装夹120上的高侧源极端子或触点并由此连接到低侧漏极触点126。高侧晶体管104还具有安装在第二安装夹上的高侧栅极端子或触点，该高侧栅极端子或触点电连接到第二安装夹。
可使用拾取和放置工具来附接高侧安装夹(712)。例如，图3的高侧漏极夹302可如其中所示的那样附接，或者图4和图6的高侧漏极夹450可如其中所示的那样附接。
图8至图12示出了用于形成低侧器件组件的工艺步骤，诸如可用于图7的操作702的特定示例性实施方式中的工艺步骤。在图8的示例中，低侧器件层802包括在图8中被示出为朝下的竖直晶体管的多个器件。在示例性实施方式中，如图8所示的此低侧器件晶圆可使用合适的粘合剂附接到玻璃载体，并且可经历图8中未详细示出的期望减薄或其他工艺步骤。玻璃载体可在切片之前去除。
在图8中，可沉积钛/铜晶种层804以用作图1B的毯覆金属层134或图4的毯覆金属层420。然后，可将绝缘体层806(诸如SiO2或合适的聚合物)沉积到晶种层804上。
在图9中，绝缘体层806可被图案化以形成图案化绝缘体层902。例如，可使用光敏绝缘体或光致抗蚀剂掩膜执行图案化，之后执行蚀刻。
图10示出了使用电镀来沉积铜(Cu)漏极触点1002。更具体地，可使用镀通氧化物(PTO)方法，其中使用晶种层804的电镀以由现有氧化物结构902决定的图案来进行。例如，可将图9中的晶圆浸入含铜离子溶液中，同时向晶圆施加电势，由此Cu电镀可由于晶种层804中存在Cu而进行。在Cu电镀之后，如果需要或期望改善平坦性，则可进行化学机械抛光(CMP)。
在图11中，类似于毯覆层804的形成，使用Ti和Cu形成粘附层/润湿层1102。因此，同样，电镀可使用层1102中的Cu来进行。具体地，例如，可进行镀通抗蚀剂工艺，其中图案化光致抗蚀剂为电镀焊料层触点1104提供开口，如图11所示。然后可使用抗蚀剂剥离，之后进行金属蚀刻来进行蚀刻工艺，该蚀刻工艺提供堆叠对1102/1104之间的间距1106。然后，可继续去除上文提及的玻璃载体，之后将晶圆切片成单个低侧器件。
图12示出了替代示例性实施方式，其中不包括毯覆金属层。在这种情况下，上述镀通氧化物(PTO)电镀选项是不可用的。相反，在绝缘体(例如，SiO2)的沉积和随后的图案化之后，可使用镶嵌工艺来形成铜漏极触点1204。例如，可使用镶嵌工艺来沉积Cu，随后可经历CMP以进行平坦化。然后，上面已经关于图11描述的工艺(例如，镀通抗蚀剂(PTR))可用于形成分别与图11中的层1102和1104相对应的粘附层/润湿层和焊料层。
图13示出了具有双中间安装夹的堆叠晶体管组件的替代实施方式。在图13中，低侧晶体管1302具有堆叠于其上的高侧晶体管1304，并且安装在引线框架1306上。此外，双中间安装夹1308(在高侧晶体管1304的栅极侧上)和1310(在高侧晶体管1304的源极侧上)安装在引线框架1306上。
图13包括用于栅极侧安装夹1308的安装焊盘，该安装焊盘包括绝缘体层1312、粘附和润湿层1314以及焊料层1316。如上文关于图1至图6所述，安装焊盘1312/1314/1316为堆叠晶体管组件提供结构稳定性，同时确保栅极安装夹1308与源极安装夹1310之间的电隔离。
同样在图13中，粘附和润湿层1318有利于包括焊料层1320。因此，源极侧安装夹1310电连接到低侧晶体管1302的漏极，并且电连接到高侧晶体管1304的源极。
在图13中，安装焊盘1312/1314/1316处于与焊料层1320不同的竖直高度处。如下文关于图14和图15所述和所示，通过这种方式制造图13的组件可能更容易且成本更低。例如，可能需要比图8至图12的示例中更少的处理步骤。
尽管如此，可保持安装夹1308、1310的顶表面的平坦性，如图13所示，使得高侧晶体管1304保持稳定，并且牢固地安装在低侧晶体管1302上面。例如，如图所示，与源极侧安装夹1310相比，可以调整栅极侧安装夹1308的相对厚度。
图14示出了用于形成图13的堆叠晶体管组件的第一示例性工艺步骤。在图14中，类似于图9，低侧晶体管1402具有形成于其上的图案化绝缘体1404。与图9相比，图14在绝缘体1404与低侧晶体管1402之间不包括毯覆金属层，但是在图13的另选实施方式中，可包括此毯覆金属层。
在图15中，金属层沉积在图14的结构上方，由此形成漏极触点1406和安装焊盘部分1408。例如，金属层可包括钛、镍、银，其中银为焊料连接件1410、1412提供润湿层。例如，钛/镍/银层1406、1408可使用湿法蚀刻工艺沉积并图案化，而焊料1410、1412可被丝网印刷。在其他实施方式中，焊料可替代地施加到高侧晶体管组件。
一种半导体器件组件可包括：低侧半导体器件；安装焊盘，该安装焊盘覆盖低侧半导体器件的第一部分；和接触层，该接触层覆盖低侧半导体器件的第二部分。该半导体器件组件可包括：第一安装夹，该第一安装夹通过其连接部分电连接到接触层，第一安装夹具有支撑部分，支撑部分将第一安装夹的连接部分连结到第一引线框架部分；和第二安装夹，该第二安装夹通过其连接部分附接到安装焊盘，该第二安装夹具有支撑部分，支撑部分将第二安装夹的连接部分连结到第二引线框架部分。该半导体器件组件可包括高侧半导体器件，该高侧半导体器件具有第一端子，第一端子电连接到第一安装夹并由此电连接到该接触层，并且具有第二端子，该第二端子电连接到第二安装夹。
在半导体器件组件的示例性实施方式中，该安装焊盘可包括绝缘层和焊料层，焊料层将绝缘层连接到该高侧半导体器件。在该半导体器件组件中，金属层可形成在低侧半导体器件的表面上方，并且设置在低侧半导体器件与接触层和安装焊盘中的每一者之间。
在半导体器件组件的示例性实施方式中，低侧半导体器件可为低侧朝下晶体管，并且高侧半导体器件可为高侧朝下晶体管。接触层可提供与低侧朝下晶体管的漏极的连接，并且第一安装夹可连接在低侧朝下晶体管的漏极与高侧朝下晶体管的源极触点之间。第二安装夹可附接到高侧朝下晶体管的栅极触点。第三安装夹可具有与高侧朝下晶体管的漏极电连接的连接部分和与第三引线框架连接的支撑部分。
一种堆叠晶体管组件可包括：低侧晶体管，该低侧晶体管具有低侧源极触点、低侧栅极触点和低侧漏极触点；以及高侧晶体管，该高侧晶体管安装在低侧晶体管上面并且具有高侧源极触点、高侧栅极触点和高侧漏极触点。安装焊盘可覆盖该低侧晶体管的第一部分，并且栅极安装夹可固定到该安装焊盘和该高侧栅极触点。接触层可覆盖低侧晶体管的第二部分并提供低侧漏极触点，并且源极安装夹可电连接到接触层和高侧源极触点。
安装焊盘可包括绝缘层和焊料层，焊料层将绝缘层连接到高侧栅极触点。安装焊盘可保持栅极安装夹与源极安装夹和低侧漏极触点电隔离。
漏极安装夹可具有与高侧漏极触点连接的连接部分和与引线框架连接的支撑部分。低侧源极触点和低侧栅极触点可连接到至少一个引线框架。
低侧晶体管可为低侧器件组件的一部分，该部分包括金属层和金属层上的绝缘体层，该金属层包括低侧器件(诸如低侧晶体管)上的铜(Cu)，绝缘体层包括氧化物。可在绝缘体层附近执行接触层到金属层上的镀通氧化物电镀。
一种制备半导体器件组件的方法包括形成低侧器件组件，该低侧器件组件包括覆盖低侧器件组件的第一部分的安装焊盘和覆盖低侧器件组件的第二部分的接触层。该方法包括：形成高侧器件组件，该高侧器件组件具有第一端子和第二端子；将低侧器件组件放置于引线框架上；以及将第一安装夹附接在引线框架与安装焊盘之间。该方法还包括：将第二安装夹附接在引线框架与接触层之间；以及将该高侧器件组件放置成第一端子连接到第一安装夹并且第二端子连接到第二安装夹。
应当理解，在前述描述中，当元件诸如层、区域、衬底或部件被提及为在另一个元件上，连接到另一个元件，电连接到另一个元件，耦接到另一个元件，或电耦接到另一个元件时，元件可以直接地在另一个元件上，连接到或耦接到另一个元件上，或者可以存在一个或多个中间元件。相反，当元件被提及直接在另一个元件或层上、直接连接到另一个元件或层、或直接耦接到另一个元件或层时，不存在中间元件或层。虽然在整个具体实施方式中可能不会使用术语直接在…上、直接连接到…、或直接耦接到…，但是被示为直接在元件上、直接连接或直接耦接的元件能以此类方式提及。本申请的权利要求书(如果存在的话)可被修订以叙述在说明书中描述或者在附图中示出的示例性关系。
如在本说明书和权利要求书中所使用的，除非根据上下文明确地指出特定情况，否则单数形式可包括复数形式。除了附图中所示的取向之外，空间相对术语(例如，在…上方、在…上面、在…之上、在…下方、在…下面、在…之下、在…之以下等)旨在涵盖器件在使用或操作中的不同取向。在一些实施方式中，在…上面和在…下面的相对术语可分别包括竖直地在…上面和竖直地在…下面。在一些实施方式中，术语邻近能包括横向邻近或水平邻近。
一些实施方式可使用各种半导体处理和/或封装技术来实现。一些实施方式可使用与半导体衬底相关联的各种类型的半导体处理技术来实现，该半导体衬底包含但不限于，例如硅(Si)、砷化镓(GaAs)、氮化镓(GaN)、碳化硅(SiC)等。
虽然所描述的实施方式的某些特征已经如本文所述进行了说明，但是本领域技术人员现在将想到许多修改形式、替代形式、变化形式和等同形式。因此，应当理解，所附权利要求书旨在涵盖落入具体实施的范围内的所有此类修改形式和变化形式。应当理解，这些修改形式和变化形式仅仅以举例而非限制的方式呈现，并且可以进行形式和细节上的各种变化。除了相互排斥的组合以外，本文所述的装置和/或方法的任何部分可以任意组合进行组合。本文所述的实施方式能包括所描述的不同实施方式的功能、部件和/或特征的各种组合和/或子组合。

Claims (10)

1.一种半导体器件组件，其特征在于，所述半导体器件组件包括：
低侧半导体器件；
安装焊盘，所述安装焊盘覆盖所述低侧半导体器件的第一部分；
接触层，所述接触层覆盖所述低侧半导体器件的第二部分；
第一安装夹，所述第一安装夹通过所述第一安装夹的连接部分电连接到所述接触层，所述第一安装夹具有支撑部分，所述支撑部分将所述第一安装夹的所述连接部分连结到第一引线框架部分；
第二安装夹，所述第二安装夹通过所述第二安装夹的连接部分附接到所述安装焊盘，所述第二安装夹具有支撑部分，所述支撑部分将所述第二安装夹的所述连接部分连结到第二引线框架部分；
高侧半导体器件，所述高侧半导体器件具有第一端子，所述第一端子电连接到所述第一安装夹并由此电连接到所述接触层，并且所述高侧半导体器件具有第二端子，所述第二端子电连接到所述第二安装夹。
2.根据权利要求1所述的半导体器件组件，其中，所述接触层附接到所述第一安装夹以及所述安装焊盘附接到所述第二安装夹保持所述第一安装夹与所述第二安装夹之间的空间间隙。
3.根据权利要求1所述的半导体器件组件，其中，所述低侧半导体器件是低侧朝下晶体管，并且所述高侧半导体器件是高侧朝下晶体管。
4.根据权利要求1所述的半导体器件组件，其中，所述安装焊盘的竖直高度高于所述接触层的竖直高度，并且所述第一安装夹和所述第二安装夹的顶表面在水平方向上是平坦的。
5.一种堆叠晶体管组件，其特征在于，所述堆叠晶体管组件包括：
低侧晶体管，所述低侧晶体管具有低侧源极触点、低侧栅极触点和低侧漏极触点；
高侧晶体管，所述高侧晶体管安装在所述低侧晶体管上面并且具有高侧源极触点、高侧栅极触点和高侧漏极触点；
安装焊盘，所述安装焊盘覆盖所述低侧晶体管的第一部分；
栅极安装夹，所述栅极安装夹固定到所述安装焊盘并固定到所述高侧栅极触点；
接触层，所述接触层覆盖所述低侧晶体管的第二部分并提供所述低侧漏极触点；和
源极安装夹，所述源极安装夹电连接到所述接触层和所述高侧源极触点。
6.根据权利要求5所述的堆叠晶体管组件，其中，所述栅极安装夹具有与所述安装焊盘和所述高侧栅极触点附接的连接部分和与引线框架附接的支撑部分。
7.根据权利要求5所述的堆叠晶体管组件，其中，所述源极安装夹具有与所述接触层和所述高侧源极触点附接的连接部分和与引线框架附接的支撑部分。
8.一种半导体器件组件，其特征在于，所述半导体器件组件包括：
低侧器件组件，所述低侧器件组件包括覆盖所述低侧器件组件的第一部分的安装焊盘和覆盖所述低侧器件组件的第二部分的接触层，所述低侧器件组件被放置于引线框架上；
高侧器件组件，所述高侧器件组件具有第一端子和第二端子；
第一安装夹，所述第一安装夹附接在所述引线框架与所述安装焊盘之间；和
第二安装夹，所述第二安装夹附接在所述引线框架与所述接触层之间；
其中所述高侧器件组件被定位成所述第一端子连接到所述第一安装夹并且所述第二端子连接到所述第二安装夹。
9.根据权利要求8所述的半导体器件组件，其中，所述第一安装夹的连接部分连接到所述安装焊盘，并且所述第一安装夹的支撑部分连接到所述引线框架。
10.根据权利要求8所述的半导体器件组件，其中，所述第二安装夹的连接部分连接到所述接触层，并且所述第二安装夹的支撑部分连接到所述引线框架。
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