TWI467721B - 晶圓級晶片尺寸封裝 - Google Patents

晶圓級晶片尺寸封裝 Download PDF

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Publication number
TWI467721B
TWI467721B TW100121065A TW100121065A TWI467721B TW I467721 B TWI467721 B TW I467721B TW 100121065 A TW100121065 A TW 100121065A TW 100121065 A TW100121065 A TW 100121065A TW I467721 B TWI467721 B TW I467721B
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Taiwan
Prior art keywords
conductive
semiconductor device
conductive pad
insulating layer
sidewall
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TW100121065A
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English (en)
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TW201205762A (en
Inventor
Yueh-Se Ho
Yan Xun Xue
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Alpha & Omega Semiconductor
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Publication of TW201205762A publication Critical patent/TW201205762A/zh
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Publication of TWI467721B publication Critical patent/TWI467721B/zh

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Description

晶圓級晶片尺寸封裝
本發明主要涉及半導體封裝，更確切地說是關於晶圓級晶片尺寸封裝(WLCSP)的低成本工藝。
半導體裝置經常要求具有低封裝阻抗和良好的熱性能。對於金屬氧化物半導體場效應管(MOSFET)裝置更是如此，尤其是垂直導電功率MOSFET裝置，它們的閘極和源極電極在半導體晶片的一個表面上，汲極電極在相對的表面上(與橫向裝置不同之處在於，橫向裝置所有的電極都在頂面上)。這些半導體裝置通常也需要簡便、快捷和高效的封裝方法。因此，原有技術中提出了許多封裝思路和方法。
儘管在過去的幾十年中，矽工藝技術取得了顯著的發展，大多數情況下，同一種幾十年前的封裝技術都繼續作為主要的封裝手段。同鋁或金引線接合一起，將環氧樹脂或焊錫晶片貼裝到引線框上，仍然是主要的半導體封裝方法。然而，半導體處理技術的發展使與傳統封裝技術有關的寄生現象(例如電阻、電容和電感)更多的是一個性能限制因素。此外，需要不斷逐漸減小的封裝尺寸。為了最好地優化空間，整體封裝引腳必須盡可能地接近半導體晶片尺寸。在傳統的倒裝晶片工藝中，除了其他 缺點，要電連接到垂直導電晶片的背面是很難的，不僅佔用大量空間，還需要額外的組裝時間。這些限制條件在功率轉換裝置等高電流應用中變得格外顯著。
美國專利號6,271,060提出了製備一種半導體裝置封裝的工藝，該半導體裝置含有一個纏繞在晶片邊緣的金屬層，以便在晶片正面和背面的導電襯底之間形成電連接。該封裝的尺寸與晶片基本相同。首先，導電襯底連接到晶圓的背面，並與晶圓中每個晶片背面上的端子電接觸；在晶圓正面上製備一個非導電的覆蓋層並形成圖案，為裸露的晶片保留一部分鈍化層以及接觸墊，每個接觸墊都被可焊的金屬層覆蓋。然後，沿晶片之間的劃痕線，在垂直方向上電鋸該組件，但是鋸痕並沒有一直延伸穿過襯底，襯底的背面仍然是完整的。截斷在一個方向上的水準鋸痕，以製備類夾層堆疊式安裝的晶片條，晶片條的一側是裸露的。在該堆疊的一側濺射或蒸發一個金屬層；翻轉該堆疊，在另一側進行同樣的工藝。所製備的金屬層沉積在晶片的正面，並沿晶片的邊緣延伸到襯底的邊緣和背面。金屬並不沉積在覆蓋層的表面上。然後，分離堆疊中的條紋，截斷垂直方向上的鋸痕，以分離單獨的晶片。在濺射或蒸發的層上電鍍一個厚金屬層，以便在每個晶片的正面和背面上的端子之間形成良好的電接觸。在一個可選實施例中，利用非導電襯底，在襯底中形成通孔並用金屬填充，以便與晶片背面上的端子形成電接觸。
美國專利號6,316,287提出了一種製備半導體裝置封裝的方法。該方法包括製備金屬層，與半導體晶片正面上的接觸墊接觸，同時該晶片仍然是晶圓的一部分。金屬層延伸到該晶片與相鄰晶片之間的劃線 中。在晶圓正面連接一個非導電蓋，打磨晶圓的背面，以減小其厚度。最好通過鋸和刻蝕，切割晶圓的背面，使金屬層裸露出來。在晶圓的背面製備一個非導電層，在非導電層上方沉積一個第二金屬層，第二金屬層延伸到第二接觸層與第一接觸層通過非導電層中的開口相接觸的劃線中。最好選用，在第二金屬層上製備一個焊錫杆，使完成後的封裝安裝在印刷電路板上。然後，沿劃線鋸蓋，鋸的切口很小，不足以截斷金屬層之間的接頭。從而，將晶片完全相互分開，構成單獨的半導體裝置封裝。
美國專利號6,562,647提出了一種在晶圓級上製備的半導體封裝，通過它連接到晶片的兩端。晶圓的背面連接到金屬板上。鋸斷分割晶片的劃線，使金屬板裸露出來，但切口並沒有穿過金屬板。含有多個子層的金屬層形成在晶片正面，金屬覆蓋著裸露的那部分金屬板，並延伸晶片的側邊緣。金屬層分開的部分也可以覆蓋晶片正面的接觸墊。第二套切口與第一套切口一致，所用的刀片比第一套切口所使用的刀片還窄。因此，金屬層仍然位於晶片的側邊緣，(通過金屬板)連接晶片的正面和背面。由於不要求引線接合，因此所製成的封裝是高低不平的，並且晶片的背面和正面之間具有低阻抗電接觸。
例如先前的原有技術封裝工藝所述的晶圓級晶片尺寸封裝，在小安裝空間中很受歡迎，對於垂直結構功率MOSFET來說，通常延伸汲極到源極和閘極背面，從而將所有的閘極、源極以及汲極電極都分佈在同一背面上。但是，由於不能從一個側視圖上看到所有的電極，因此這種結構在電路板級安裝和檢驗方面還存在許多困難。而且，所述的原有技術需要使用一個額外的支撐襯底，否則就不是真實的晶圓級工藝。
正是在這一前提下，提出了本發明的各種實施例。
本發明的目的是提供一種晶圓級晶片尺寸封裝及其製備方法，該半導體裝置的晶圓級晶片尺寸封裝尺寸小，優化空間，不需要額外的支撐襯底，更加簡便、高效和成本低。
為了達到上述目的，本發明提供了一種半導體裝置，其包括：一個半導體襯底，具有第一和第二表面以及在第一和第二表面之間的側壁；一個第一導電墊，在裝置的第一表面上，與襯底內的第一半導體裝置結構電接觸；一個第二導電墊，在裝置的第二表面上，與襯底內的第二半導體裝置結構電接觸；一個在側壁上的切口，從第一表面延伸到第二表面，其中所述的切口並沒有延伸穿過晶片的整個長度；一個絕緣層，在第一表面上和切口中的側壁上；一個導電層，在側壁上的部分絕緣層上，其中導電層與第二導電墊電接觸，以便可以從第一表面上接入第二導電墊，其中絕緣層阻止導電層在第二導電墊和半導體襯底的側壁之間接觸。
上述的半導體裝置，其中，所述的絕緣層和導電層覆蓋了第一表面上的一部分第一導電墊，絕緣層使第一導電墊與所述的導電層絕緣。
上述的半導體裝置，其中，側壁上的一部分導電層裸露出來，通過這個裸露的部分，從裝置的邊緣就可以電連接到第二導電墊或檢驗接頭。
上述的半導體裝置，其中，該裝置是一個垂直場效應管。
上述的半導體裝置，其中，第一半導體裝置結構含有一個源極區，其中第二半導體裝置結構含有一個汲極區。
上述的半導體裝置，其中，該半導體裝置還包括：一個在側壁上的第二切口，從第一表面延伸到第二表面；一個第二絕緣層，在第二表面上以及第二切口中的側壁上；一個第二導電層，在側壁上的部分第二絕緣層上，其中第二導電層與第一導電墊電接觸，以便可以從第二表面接入第一導電墊。
上述的半導體裝置，其中，第二絕緣層和第二導電層覆蓋了第二表面上的一部分第二導電墊，第二絕緣層使第二導電墊與所述的第二導電層絕緣。
上述的半導體裝置，其中，該半導體裝置還包括：一個第三導電墊，在第一表面上，與襯底內的第三半導體裝置電接觸，其中第三導電墊與第一導電墊電絕緣；一個在側壁上的第三切口，從第一表面延伸到第二表面；一個第三絕緣層，在第二表面和第三切口上；一個第三導電層，在第三切口上的部分第三絕緣層上以及第二表面上，其中第三導電層與第三導電墊電接觸，以便從第二表面接入第三導電墊，其中第三絕緣層阻止第三導電層在第三導電墊和半導體襯底的側壁之間接觸。
上述的半導體裝置，其中，第一半導體裝置結構含有一個源極區，第二半導體裝置結構含有一個汲極區，並且第三半導體裝置結構含有一個閘極。
上述的半導體裝置，其中，第一和第三導電墊是由同一種導電層製成的。
上述的半導體裝置，其中，第一、第二和第三導電墊均可以從第一和第二表面接入。
上述的半導體裝置，其中，在側壁上的一部分第一、第二和第三導電層裸露出來，通過這些裸露的部分，從裝置邊緣就可以電連接到第一、第二和第三導電墊或檢驗那裏的電接頭。
上述的半導體裝置，其中，該半導體裝置還包括：一個在半導體襯底側壁上的附加的切口，從第一表面延伸到第二表面；一個附加的絕緣層，在附加的切口的側壁上；一個附加的導電層，在側壁上的部分附加的絕緣層上，其中通過附加的絕緣層，附加的導電層與半導體襯底電絕緣，使附加的導電層在第一表面和第二表面之間形成一個外部電連接。
本發明還提供了一種製備多個半導體裝置的晶圓級方法，該方法包括：a)製備多個半導體裝置晶片，在一個由半導體襯底構成的半導體晶圓上被標出的劃線分開，其中每個半導體晶片都含有一個在第一表面上的第一導電墊和一個在第二表面上的第二導電墊，其中第二表面在襯底邊上與第一表面相對，並被側壁分開，其中第一導電墊與襯底中的第一半導體裝置結構電接觸，第二導電墊與第二表面上的第二半導體裝置結構電接觸；b)製備一個或多個通孔，穿過襯底，在相鄰的晶片之間的劃線處，其中所述的通孔並沒有延伸穿過半導體晶片的整個長度；c)在一個或多個通孔的側壁上製備一個絕緣層；並且d)在第一表面和側壁上的絕緣層上方，製備一個導電層，其中導電層與第二導電墊電接觸，以便從第一表面接入第二導電墊，其中絕緣層阻止導電層在第二導電墊和半導體襯底的側壁之間接觸。
上述的方法，其中，該方法還包括在步驟b)之後：c’)在一個不同的一個或多個通孔的一部分側壁上，製備第二絕緣層；並且d’)在 第二表面上以及不同的一個或多個通孔的側壁上的第二絕緣層上方，製備一個第二導電層，其中第二導電層與第一導電墊電接觸，以便從第二表面接入第一導電墊，其中第二絕緣層阻止第二導電層在第一導電墊和半導體襯底的側壁之間接觸。
上述的方法，其中，該方法還包括：在步驟d)之後，切割晶圓，以形成單獨的半導體裝置，其中所述的切割包括將通孔分成切口。
上述的方法，其中，該方法包括：a)製備多個半導體裝置晶片還包括，製備多個半導體裝置晶片，使每個裝置晶片還包括在第一表面上的第三導電墊，與襯底內的第三半導體裝置結構電接觸，其中第三導電墊與第一導電墊電絕緣；其中該方法還包括在步驟b)之後：c’’)在另一個不同的一個或多個通孔的一部分側壁上，製備一個第三絕緣層；並且d’’)在第二表面和另一個不同的一個或多個通孔的側壁上，製備一個第三導電層，其中第三導電層與第三導電墊電接觸，以便從第二表面接入第三導電墊，其中第三絕緣層阻止第三導電層在第三導電墊和半導體襯底的側壁之間接觸。
本發明還提供了一種電路封裝元件，該元件包括：一個第一垂直金屬氧化物半導體場效應管(MOSFET)，具有頂部源極和閘極以及一個底部汲極，其中第一垂直MOSFET包括至少源極、閘極和汲極電極中的兩個，源極、閘極和汲極電極可以在第一MOSFET的正面和背面連接；以及一個第二垂直金屬氧化物半導體場效應管(MOSFET)，具有頂部源極和閘極以及一個底部汲極，其中第二垂直MOSFET包括至少源極、閘極和汲極電極中的兩個，源極、閘極和汲極電極可以在第二MOSFET的正面和背面連接， 其中，第一和第二MOSFET堆疊在一起。
上述的電路封裝元件，其中，第一和第二MOSFET的至少源極、閘極和汲極電極中的兩個包括沿MOSFET側壁的切口中所含的附加導電層，通過一個絕緣層，所述的附加導電層與半導體襯底的側壁絕緣。
上述的電路封裝元件，其中，第一MOSFET的源極電連接到第二MOSFET的汲極。
上述的電路封裝元件，其中，MOSFET的電極是並聯的。
本發明的實施例無需使用外來襯底，例如蓋或其他結構，或分開製備工藝後，為半導體裝置晶片的正面和背面之間提供接觸。本發明的實施例允許在半導體裝置的正面和背面上電接觸，同時該裝置仍然是晶圓的一部分，並且在將晶圓分成單獨的裝置晶片之前。本發明的實施例也可以提供具有裸露的金屬接頭的裝置結構，這些金屬接頭可以從裝置結構的邊緣得到。這使得連接可以從晶片的邊緣看到並檢驗，如果有必要，也可以連接到晶片的邊緣。由於晶片的頂面和底面上都連接到電極，因此附加的結構，例如並聯或串聯堆疊晶片，都是可以的。
本發明的技術方案在功率MOSFET應用中尤其有優勢。本發明的實施例在裝置的兩側都有閘極、源極和汲極電極，並且可以從裝置的邊緣接觸，使得高端(HS)和低端(LS)MOSFET的堆疊式共同封裝，構成一個直流-直流功率轉換器半橋式，或者堆疊多個MOSFET晶片並聯，以提高導通電阻(Ron)，並且在直流-直流功率轉換器上堆疊一個電容器，以提高模式和電路板級性能。
除了MOSFET以外，還可以利用上述技術製備其他類型的裝 置。本發明的實施例也可以用於任何類型的在裝置的兩側帶有電極的垂直裝置，包括絕緣柵雙極電晶體(IGBT)、垂直雙極結型電晶體(BJT)、功率二極體等。
100、200‧‧‧半導體裝置
201‧‧‧襯底
202‧‧‧閘極正面墊
204‧‧‧源極正面墊
206‧‧‧正面汲極接頭
208‧‧‧側面汲極接頭
210‧‧‧絕緣材料
102‧‧‧鈍化層
104‧‧‧導電層
105‧‧‧側壁
106‧‧‧切角
107、207、D‧‧‧汲極電極
108、S‧‧‧源極電極
110、G‧‧‧閘極電極
112‧‧‧襯底
114‧‧‧有源裝置區
203、205‧‧‧背面接頭
219‧‧‧再路由電極
300‧‧‧矩形部分
301‧‧‧正面
302‧‧‧半導體晶片
303‧‧‧背面
304‧‧‧劃線區
306、702‧‧‧閘極墊
308、704‧‧‧源極墊
310、707‧‧‧汲極墊
311‧‧‧半導體襯底
312‧‧‧通孔
314‧‧‧沉積絕緣層
316‧‧‧絕緣層
700‧‧‧裝置
703‧‧‧閘極接頭
705‧‧‧源極接頭
706‧‧‧汲極接頭
710‧‧‧切口
DPC‧‧‧公共晶片墊
HS‧‧‧高端
LS‧‧‧低端
SP‧‧‧焊錫膏
SH‧‧‧源極
DL‧‧‧汲極
SL‧‧‧源極
LF‧‧‧引線框
BW‧‧‧接合引線
第1A圖表示一種原有技術的半導體裝置正面(源極和閘極表面)的透視圖。
第1B圖表示第1A圖所示的半導體裝置背面(汲極背面)的透視圖。
第2A圖表示依據本發明的一個實施例，一種半導體裝置正面(源極和汲極背面)的透視圖。
第2B圖表示第2A圖所示的半導體裝置背面(汲極背面)的透視圖。
第2C圖和第2D圖分別表示第2A-2B圖所示的半導體裝置的一個可選實施例的正面和背面的透視圖。
第3A圖至第6A圖和第7A圖為一種半導體裝置的正面(源極和閘極表面)透視圖，分別表示依據本發明的一個實施例，第2A-2B圖所示類型的半導體裝置的晶圓級晶片尺寸封裝工藝。
第3B圖至第6B圖和第7B圖表示第3A圖至第6A圖所示的製備工藝的特定步驟中的半導體裝置的背面透視圖。
第6C-6D圖為半導體裝置的正面和背面透視圖，表示第6A-6B圖所述的製備工藝的特定步驟的一個可選實施例。
第8A圖表示高端和低端MOSFET共同封裝的一個原有技術示例的側視圖。
第8B圖表示依據本發明的一個實施例，堆疊式高端和低端MOSFET的側視圖。
儘管為了解釋說明，以下詳細說明包含了許多具體細節，但是本領域的任何技術人員都應理解基於以下細節的多種變化和修正都屬本發明的範圍。因此，本發明的典型實施例的提出，對於請求保護的發明沒有任何一般性的損失，而且不附加任何限制。
相同委託人的美國公開號2009/0194880的專利提出了一種垂直功率MOSFET的功率晶圓級晶片尺寸封裝，該MOSFET中所有的源極、閘極和汲極電極都位於裝置的一個表面上，可以通過焊膏等方式方便地安裝到印刷電路板(PCB)上。第1A-1B圖分別表示半導體裝置100的正面和背面的透視圖。如第1A圖所示，源極電極(S)108和閘極電極(G)110位於裝置100的正面上，通過鈍化層102中的打開視窗，連接到下方的源極墊和閘極墊，鈍化層102沉積在半導體材料(例如矽)製成的襯底112上。源極墊和閘極墊連接到垂直功率MOSFET的正面的源極區和閘極區，汲極區通常位於裝置100的背面。如第1A圖所示，汲極電極(D)107可以位於裝置100正面上切角106處。通過切角106處的襯底112的側壁105背面和上方的導電層104，如第1A-1B圖所示，將汲極電極(D)107電連接到裝置100背面附近的汲極區上。可以配置汲極電極107，使它們延伸到正面上被鈍化物102覆蓋的那部分有源裝置區114上方。通過穿過含有多個半導體晶片的晶圓製備通孔，在半導體晶片之間的角交叉處，形成汲極電極(D)107，然後，在晶圓的底面上以及通孔的側壁上製備一個導電層，觸及晶圓的正面。然而，半導體 裝置100在裝置的一個表面上僅具有閘極、源極和汲極電極，並不能從側面看到所有的電極，這使得電路板級安裝和檢驗比較困難。
實施例
在本發明的實施例中，可以通過具有半導體襯底的半導體裝置克服這些缺點，半導體襯底帶有第一和第二表面以及在它們之間的側壁。在第一和第二表面上的第一和第二導電墊，與襯底中相應的第一和第二半導體裝置結構電接觸。在側壁上，形成一個從第一表面到第二表面的切口。在第一表面和切口側壁上的絕緣層，覆蓋第一表面上的那部分第一導電墊，以及半導體襯底的側壁。在第一導電墊上的那部分絕緣層上以及側壁上的導電層，與第二導電墊電接觸。絕緣層阻止導電層在第一和第二導電墊之間以及電極和半導體襯底側壁之間電接觸。
在一些實施例中，側壁上的那部分導電層可以裸露出來，從而與第二導電墊電接觸或通過裸露部分的裝置側壁檢驗該電接觸。
本發明的實施例包括垂直場效應管裝置的裝置，其中在裝置的第一和第二表面上具有閘極、源極和汲極電極。可以通過在閘極、源極和汲極區附近的晶圓劃線中的通孔製備這種裝置。
第2A-2B圖分別表示依據本發明的一個實施例，半導體裝置200的正面(源極和閘極表面)和背面(汲極背面)的透視圖。閘極正面墊202和源極正面墊204形成在襯底201的正面。汲極墊207可以形成在襯底201的背面。
閘極、源極和汲極電極可以與襯底201中相應的裝置結構電接觸。更確切地說，閘極正面墊204可以與在襯底201中所形成的閘極結構電 接觸。閘極結構含有形成在襯底內的一個或多個導電閘極，並與襯底材料電絕緣。閘極可以電連接到閘極滑道，閘極滑道水準穿過襯底，並與襯底材料電絕緣。閘極滑道可以通過導電接頭電連接到閘極電極，導電接頭垂直穿過襯底，並與襯底材料電絕緣。源極正面墊204可以通過垂直接頭，電連接到形成在襯底201內的一個或多個源極區。例如通過每個閘極附近選擇性的襯底摻雜區域，形成每個源極區。閘極正面墊202和源極正面墊204位於裝置的正面或頂面上。汲極電極207可以與襯底底部直接電接觸，摻雜襯底底部用作汲極區。半導體裝置可以是一個垂直裝置，意味著主電流從第一(例如頂部)表面上的源極開始，垂直流至襯底201的汲極和第二(例如底部)表面。
一個或多個閘極、源極和汲極電極通過形成在襯底201的一部分側壁上的導電層，電連接到位於襯底201對面的相應的導電墊。更確切地說，通過由裝置200的側壁上的那部分導電層所形成的側面汲極接頭208，背面上的汲極墊207可以電連接到正面上相應的正面汲極接頭206。通過裝置左側側壁上類似的導電源極和閘極側面接頭(圖中沒有表示出)，正面上的正面閘極墊202和正面源極墊204可以分別電連接到背面上相應的背面接頭203、205上。
正面閘極墊202、側面閘極接頭以及背面閘極接頭203的組合有時稱為閘極電極。正面源極墊204、側面源極接頭以及背面源極接頭205的組合有時稱為源極電極。與之類似，汲極墊207、側面汲極接頭208以及背面汲極接頭206的組合有時稱為汲極電極。墊、對面接頭以及每個電極的側面接頭都可以視為該電極的不同部分。
形成在一部分頂部源極墊204和裝置的側壁右邊，側面汲極接頭208和汲極墊206下方的絕緣材料210，防止側面汲極接頭208不必要的短路電流流經源極電極和汲極電極，同時使構成源極墊204的源極金屬完全覆蓋晶片的大型有源區，以便更加高效地利用晶片區域。與之類似，形成在一部分底部汲極墊207上方，底部源極閘極墊203和底部表面源極墊205電極下方，並在裝置200的左側側壁上的絕緣材料210，防止不必要的短路電流流經汲極電極和閘極電極或源極電極之間。絕緣材料還防止不必要的短路電流流經閘極電極和源極電極以及半導體襯底201的側壁之間。側壁上的絕緣材料210和導電材料可以形成在切口中。切口沿側壁從半導體襯底201的頂面一直到底面，但並沒有穿過半導體襯底201的整個長度。如圖汲極電極207所示，對於一個電極可以形成不止一個切口。因此，襯底201中形成的到源極、閘極和汲極結構的接頭可以從裝置200的頂面和底面開始。儘管，第2A-2B圖僅表示出了含有連接導電層的切口沿裝置的兩個(左邊和右邊)側壁形成，但是應明確它們也可以沿其他側壁形成。
如第2A-2B圖所示，構成側面汲極接頭208以及側面源極和閘極接頭的導電層的側壁部分可以裸露出來，從而使可以從裝置200的側面到閘極、源極和汲極電極進行電接頭或視覺檢驗。
第2C圖和第2D圖分別表示本發明的一個可選實施例，從正面和背面的頂部和底部透視圖。除了含有再路由電極219之外，它們大部分都與第2A圖和第2B圖相同。對於源極、閘極和汲極，再路由電極219具有與電極、墊、側面接頭以及上述導電層類似的結構，但是通過絕緣層210，與半導體襯底以及源極、閘極和汲極電極絕緣。這可以用於從晶片頂部到底 部的再路由電連接。例如，電連接可以從堆疊在裝置200上方的另一個裝置(例如第二MOSFET、電容器、IC晶片等)開始。如上所述，再路由電極219的側壁部分也可以位於切口中。
第3A-7A圖和第3B-7B圖為依據本發明的一個實施例，從半導體裝置的正面和背面的透視圖，分別表示製備第2A-2B圖所示的垂直功率MOSFET的晶片級封裝晶圓級製備工藝。
第3A圖和第3B圖分別表示半導體襯底311的矩形部分300的正面和背面視圖，其中半導體襯底311含有多個形成在它上面的裝置結構302。作為示例，該襯底可以是一個半導體晶圓，例如矽晶圓，由多個半導體晶片構成。該晶圓可以在一個連續的柵格中容納多個類似於矩形部分300那樣的部分。半導體晶片302被劃線區304分開(儘管晶片還沒有被分開)，每個劃線區304的寬度w1約為60至80微米。每個半導體晶片302都含有一個閘極墊306和源極墊308在正面301上，以及一個汲極墊310在背面303上。
如第4A圖和第4B圖所示，通孔312可以穿過襯底311形成，在閘極、源極、汲極墊306、308、310附近的劃線區304中的間隔處。通孔可以有不同的形狀，包括橢圓形、矩形、圓形等。而且，一個電極可以有多個通孔，例如第4A-4B圖中的汲極的通孔。可以通過濕刻蝕或幹咳嗽製備通孔312。選取通孔312的間距，使它足夠大(例如約為30至50微米)，以便在分割半導體晶片時防止裝置短路。選取通孔的尺寸，為後續工藝在通孔中製備絕緣層和金屬化，留出充足的空間。通孔312並沒有延伸穿過晶片的整個長度，因此在這種情況下，通孔312並沒有將襯底311分成單獨的晶片或部分。所以，無需將襯底311貼裝到支撐襯底上，就可以將它作為一個完整的 晶圓，進一步處理。
如第5A圖和第5B圖所示，在通孔312的側壁上，以及側壁附近晶片的正面301和背面303的那部分上，沉積絕緣層314，使通孔312的側壁與源極墊306、閘極墊308以及汲極墊310的部分電絕緣。在一個典型的垂直FET中，半導體襯底311的側壁(通過通孔裸露出來)處於汲極電勢，因此，它對於使源極和閘極與半導體襯底側壁絕緣尤其重要。絕緣層314也可以為最終的頂部汲極接頭位於一部分源極金屬308上方留出空間，並為最終的閘極和源極底部接頭位於一部分汲極金屬310上方留出空間，因此不需要犧牲有源區，就可以從裝置的頂面和底面連接到電極上。絕緣層314可以含有氧化物(例如含有硼酸的矽玻璃(PSG))、氮化物或其他適宜的材料。絕緣層314的厚度約為3-4微米。可以利用一個帶圖案的掩膜(例如光致抗蝕劑掩膜)形成絕緣層314的圖案。
然後，如第6A-6B圖所示，可以在裝置302的正面301和背面303上所選的那部分絕緣層314上方，以及通孔312內，形成一個第二金屬(例如鋁-銅合金(Al-Cu))層，以便通過覆蓋通孔312的側邊，使閘極、源極和汲極墊電連接到它們對面接頭上。可以利用一個帶圖案的掩膜(例如光致抗蝕劑掩膜)形成絕緣層316的圖案。作為示例，不作為局限，可以通過帶圖案的掩膜(例如先進的光致抗蝕劑)中的開口，進行物理氣相沉積(PVD)沉積金屬，從而將導電層316沉積在所選的那部分絕緣層314上方。作為示例，導電層316的金屬可以完全覆蓋閘極、源極和汲極墊306、308、310的第一金屬層的裸露部分(對於第5A-5B圖裸露)。如第6C-6D圖所示，在一個可選實施例中，導電層316的金屬可以僅僅覆蓋閘極、源極和汲極墊306、308、 310的第一金屬層部分，同時留出源極和汲極墊308、310的其他部分用絕緣層314覆蓋。
如第7A-7B圖所示，將晶圓切成塊，形成單獨的裝置700。切割工藝沿劃線區304穿過通孔312的中心。在每個半導體晶片的側壁中，晶圓分割(例如切割)將通孔312變成切口710。切口含有絕緣材料和導電材料，用於將墊連接到對面對應的接頭上。如果孔312沿劃線的間距足夠大，那麼就可以在切割過程中避免不必要的短路，例如晶圓切割工藝中金屬污染。另外，可以進行短暫的刻蝕，避免從金屬到半導體襯底側壁或電極之間的短路。如第7A圖所示，裝置700的正面含有一個閘極墊702、一個源極墊704和一個汲極接頭706。如第7B圖所示，裝置700的背面也含有一個閘極接頭703、一個源極接頭705和一個汲極墊707。
本發明的實施例無需使用外來襯底，例如蓋或其他結構，或分開製備工藝後，為半導體裝置晶片的正面和背面之間提供接觸。本發明的實施例允許在半導體裝置的正面和背面上電接觸，同時該裝置仍然是晶圓的一部分，並且在將晶圓分成單獨的裝置晶片之前。本發明的實施例也可以提供具有裸露的金屬接頭的裝置結構，這些金屬接頭可以從裝置結構的邊緣得到。這使得連接可以從晶片的邊緣看到並檢驗，如果有必要，也可以連接到晶片的邊緣。由於晶片的頂面和底面上都連接到電極，因此附加的結構，例如並聯或串聯堆疊晶片，都是可以的。
本發明的實施例在功率MOSFET應用中尤其有優勢。例如，傳統的利用MOSFET功率裝置的直流-直流功率轉換器通常需要一個高端NMOSFET和一個低端NMOSFET。傳統的垂直MOSFET裝置是底部汲極。在 功率轉換器封裝中，高端源極和低端汲極通常通過額外的接合引線相互連接，並且低端源極可以電耦合到引線框上。本發明的實施例在裝置的兩側都有閘極、源極和汲極電極，並且可以從裝置的邊緣接觸，使得高端(HS)和低端(LS)MOSFET的堆疊式共同封裝，構成一個直流-直流功率轉換器半橋式，或者堆疊多個MOSFET晶片並聯，以提高導通電阻(Ron)，並且在直流-直流功率轉換器上堆疊一個電容器，以提高模式和電路板級性能。
除了MOSFET以外，還可以利用上述技術製備其他類型的裝置。本發明的實施例也可以用於任何類型的在裝置的兩側帶有電極的垂直裝置，包括絕緣柵雙極電晶體(IGBT)、垂直雙極結型電晶體(BJT)、功率二極體等。
參見第8A圖和第8B圖可以理解本發明實施例的優勢。第8A圖的剖面圖表示一個高端NMOSFET HS和一個低端NMOSFET LS的原有技術的共同封裝結構。如第8A圖所示，高端NMOSFET HS和低端NMOSFET LS位於一個公共晶片墊DPC上，高端NMOSFET HS的源極SH和低端NMOSFET LS汲極DL面對著公共晶片墊DPC。低端NMOSFET LS源極SL可以通過接合引線BW電耦合到引線框LF上。然而，這不如堆疊式結構更能有效地利用空間，並且對於高端NMOSFET HS而言，還需要設計一個底部源極MOSFET裝置。
第8B圖的剖面圖表示一個高端NMOSFET HS和一個低端NMOSFET LS的堆疊式共同封裝元件的優勢，其中在裝置的兩側都有閘極、源極和汲極電極。如第8B圖所示，高端NMOSFET HS可以堆疊在低端NMOSFET LS上方。通過焊錫膏SP，利用上述包纏式側壁接頭，高端 NMOSFET HS的源極可以電連接到低端NMOSFET的汲極上。低端MOSFET可以通過焊錫膏SP，安裝在一個印刷電路板(PCB)(圖中沒有表示出)上方。堆疊MOSFET可以更加高效地利用電路板上的空間。作為示例，通過利用上述的再路由電極(圖中沒有表示出)，頂部晶片的閘極可以連接到堆疊的底部。還可選擇，為了提高導通電阻，第8B圖所示的剖面圖可以表示兩個並聯的堆疊式MOSFET。
由上可知，本發明的實施例可以使半導體裝置的晶圓級晶片尺寸封裝更加簡便、高效和成本低。
儘管說明書所述的是垂直功率MOSFET，但是本發明也可以用於任何類型的垂直半導體裝置，例如絕緣柵雙極電晶體(IGBT)、底部源極MOSFET或雙極功率電晶體，或垂直二極體。
儘管本發明關於某些較佳的版本已經做了詳細的敍述，但是仍可能存在各種等效的其他方案和修正。因此，本發明的範圍不應由上述說明決定，與之相反，本發明的範圍應參照所附的申請專利範圍及其全部等效內容。任何可選件(無論首選與否)，都可與其他任何可選件(無論首選與否)組合。在以下申請專利範圍中，除非特別聲明，否則不定冠詞“一個”或“一種”都指下文內容中的一個或多個專案的數量。除非用“意思是”明確指出限定功能，否則所附的申請專利範圍並不應認為是意義和功能的侷限。
200‧‧‧半導體裝置
201‧‧‧襯底
202‧‧‧閘極正面墊
204‧‧‧源極正面墊
206‧‧‧正面汲極接頭
208‧‧‧側面汲極接頭
210‧‧‧絕緣材料

Claims (19)

  1. 一種半導體裝置，其包括：一個半導體襯底，具有第一和第二表面以及在第一和第二表面之間的側壁；一個第一導電墊，在裝置的第一表面上，與襯底內的第一半導體裝置結構電接觸；一個第二導電墊，在裝置的第二表面上，與襯底內的第二半導體裝置結構電接觸；一個在側壁上的切口，從第一表面延伸到第二表面，其中所述的切口並沒有延伸穿過晶片的整個長度；一個絕緣層，在第一表面上和切口中的側壁上；一個導電層，在側壁上的部分絕緣層上，其中導電層與第二導電墊電接觸，以便可以從第一表面上接入第二導電墊，其中絕緣層阻止導電層在第二導電墊和半導體襯底的側壁之間接觸，所述的絕緣層和導電層覆蓋了第一表面上的一部分第一導電墊，絕緣層使第一導電墊與所述的導電層絕緣。
  2. 如申請專利範圍第1項所述的半導體裝置，其特徵在於，側壁上的一部分導電層裸露出來，通過這個裸露的部分，從裝置的邊緣就可以電連接到第二導電墊或檢驗接頭。
  3. 如申請專利範圍第1項所述的半導體裝置，其特徵在於，該裝置是一個垂直場效應管。
  4. 如申請專利範圍第3項所述的半導體裝置，其特徵在於，第一半導體裝置 結構含有一個源極區，其中第二半導體裝置結構含有一個汲極區。
  5. 如申請專利範圍第1項所述的半導體裝置，其特徵在於，該半導體裝置還包括：一個在側壁上的第二切口，從第一表面延伸到第二表面；一個第二絕緣層，在第二表面上以及第二切口中的側壁上；一個第二導電層，在側壁上的部分第二絕緣層上，其中第二導電層與第一導電墊電接觸，以便可以從第二表面接入第一導電墊。
  6. 如申請專利範圍第5項所述的半導體裝置，其特徵在於，第二絕緣層和第二導電層覆蓋了第二表面上的一部分第二導電墊，第二絕緣層使第二導電墊與所述的第二導電層絕緣。
  7. 如申請專利範圍第5項所述的半導體裝置，其特徵在於，該半導體裝置還包括：一個第三導電墊，在第一表面上，與襯底內的第三半導體裝置電接觸，其中第三導電墊與第一導電墊電絕緣；一個在側壁上的第三切口，從第一表面延伸到第二表面；一個第三絕緣層，在第二表面和第三切口上；一個第三導電層，在第三切口上的部分第三絕緣層上以及第二表面上，其中第三導電層與第三導電墊電接觸，以便從第二表面接入第三導電墊，其中第三絕緣層阻止第三導電層在第三導電墊和半導體襯底的側壁之間接觸。
  8. 如申請專利範圍第7項所述的半導體裝置，其特徵在於，其中第一半導體裝置結構含有一個源極區，第二半導體裝置結構含有一個汲極區，並且第三半導體裝置結構含有一個閘極區。
  9. 如申請專利範圍第7項所述的半導體裝置，其特徵在於，第一和第三導電墊是由同一種導電層製成的。
  10. 如申請專利範圍第7項所述的半導體裝置，其特徵在於，第一、第二和第三導電墊均可以從第一和第二表面接入。
  11. 如申請專利範圍第7項所述的半導體裝置，其特徵在於，其中在側壁上的一部分第一、第二和第三導電層裸露出來，通過這些裸露的部分，從裝置邊緣就可以電連接到第一、第二和第三導電墊或檢驗那裏的電接頭。
  12. 如申請專利範圍第1項所述的半導體裝置，其特徵在於，該半導體裝置還包括：一個在半導體襯底側壁上的附加的切口，從第一表面延伸到第二表面；一個附加的絕緣層，在附加的切口的側壁上；一個附加的導電層，在側壁上的部分附加的絕緣層上，其中通過附加的絕緣層，附加的導電層與半導體襯底電絕緣，使附加的導電層在第一表面和第二表面之間形成一個外部電連接。
  13. 一種製備多個半導體裝置的晶圓級方法，其特徵在於，該方法包括：a)製備多個半導體裝置晶片，在一個由半導體襯底構成的半導體晶圓上被標出的劃線分開，其中每個半導體晶片都含有一個在第一表面上的第一導電墊和一個在第二表面上的第二導電墊，其中第二表面在襯底邊上與第一表面相對，並被側壁分開，其中第一導電墊與襯底中的第一半導體裝置結構電接觸，第二導電墊與第二表面上的第二半導體裝置結構電接觸；b)製備一個或多個通孔，穿過襯底，在相鄰的晶片之間的劃線處，其中所述的通孔並沒有延伸穿過半導體晶片的整個長度； c)在一個或多個通孔的側壁上製備一個絕緣層；並且d)在第一表面和側壁上的絕緣層上方，製備一個導電層，其中導電層與第二導電墊電接觸，以便從第一表面接入第二導電墊，其中絕緣層阻止導電層在第二導電墊和半導體襯底的側壁之間接觸，所述的絕緣層和導電層覆蓋了第一表面上的一部分第一導電墊，絕緣層使第一導電墊與所述的導電層絕緣。
  14. 如申請專利範圍第13項所述的方法，其特徵在於，該方法還包括在步驟b)之後：c’)在一個不同的一個或多個通孔的一部分側壁上，製備第二絕緣層；並且d’)在第二表面上以及不同的一個或多個通孔的側壁上的第二絕緣層上方，製備一個第二導電層，其中第二導電層與第一導電墊電接觸，以便從第二表面接入第一導電墊，其中第二絕緣層阻止第二導電層在第一導電墊和半導體襯底的側壁之間接觸。
  15. 如申請專利範圍第14項所述的方法，其特徵在於，該方法還包括：在步驟d)之後，切割晶圓，以形成單獨的半導體裝置，其中所述的切割包括將通孔分成切口。
  16. 如申請專利範圍第14項所述的方法，其特徵在於，該方法包括：a)製備多個半導體裝置晶片還包括，製備多個半導體裝置晶片，使每個裝置晶片還包括在第一表面上的第三導電墊，與襯底內的第三半導體裝置結構電接觸，其中第三導電墊與第一導電墊電絕緣；其中該方法還包括在步驟b)之後：c’’)在另一個不同的一個或多個通孔的一部分側壁上，製備一個第三絕緣 層；並且d’’)在第二表面和另一個不同的一個或多個通孔的側壁上，製備一個第三導電層，其中第三導電層與第三導電墊電接觸，以便從第二表面接入第三導電墊，其中第三絕緣層阻止第三導電層在第三導電墊和半導體襯底的側壁之間接觸。
  17. 一種電路封裝元件，其特徵在於，該元件包括：一個第一垂直金屬氧化物半導體場效應管(MOSFET)，具有頂部源極和閘極以及一個底部汲極，其中第一垂直MOSFET包括至少源極、閘極和汲極電極中的兩個，源極、閘極和汲極電極可以在第一MOSFET的正面和背面連接；以及一個第二垂直金屬氧化物半導體場效應管(MOSFET)，具有頂部源極和閘極以及一個底部汲極，其中第二垂直MOSFET包括至少源極、閘極和汲極電極中的兩個，源極、閘極和汲極電極可以在第二MOSFET的正面和背面連接，其中，第一和第二MOSFET堆疊在一起；第一及第二MOSFET的電極是並聯的。
  18. 如申請專利範圍第17項所述的電路封裝元件，其特徵在於，其中第一和第二MOSFET的至少源極、閘極和汲極電極中的兩個包括沿MOSFET側壁的切口中所含的附加導電層，通過一個絕緣層，所述的附加導電層與半導體襯底的側壁絕緣。
  19. 如申請專利範圍第17項所述的電路封裝元件，其特徵在於，其中：第一MOSFET的源極電連接到第二MOSFET的汲極。
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