TW200814884A - Process for attaching an electronic component on a circuit board and system cimprised of a circuit board and at least one electronic component - Google Patents

Process for attaching an electronic component on a circuit board and system cimprised of a circuit board and at least one electronic component Download PDF

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Publication number
TW200814884A
TW200814884A TW096117171A TW96117171A TW200814884A TW 200814884 A TW200814884 A TW 200814884A TW 096117171 A TW096117171 A TW 096117171A TW 96117171 A TW96117171 A TW 96117171A TW 200814884 A TW200814884 A TW 200814884A
Authority
TW
Taiwan
Prior art keywords
contact
circuit board
electronic component
connection
intermediate layer
Prior art date
Application number
TW096117171A
Other languages
English (en)
Inventor
Hannes Voraberger
Gerhard Schmid
Markus Riester
Johannes Stahr
Original Assignee
Austria Tech & System Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Austria Tech & System Tech filed Critical Austria Tech & System Tech
Publication of TW200814884A publication Critical patent/TW200814884A/zh

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
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    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113Via provided in pad; Pad over filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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    • H05K13/00Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04Mounting of components, e.g. of leadless components
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    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
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    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01ELECTRIC ELEMENTS
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    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • HELECTRICITY
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2201/09436Pads or lands on permanent coating which covers the other conductors
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    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
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    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
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    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
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    • H05K3/465Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
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    • H05K3/4652Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

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200814884 九、發明說明: - 【發明所屬之技術領域】 本發明係關於一種將電子元件附著至電路板上及/或 將該電子元件接觸於該電路板之方法,以及一種用來產生 用於從電路板之接觸或連接表面拆解電子元件之接觸或連 接位置之中間層之方法。本發明復關於—種包括電路板和 至少一個電子元件之系統。 【先前技術】 ♦ θ制於電路板上之電子元件⑽得愈來愈複雜,尤其 疋電子兀件已造成需要更多數量的連接至電路板,如此 轉而導致減少個別或相鄰連接(譬如像是具有未改變電子 元件尺寸之導電接腳(pin))之間的距離。於此連接 刷電路板製造者開始藉由穿過稱之為高密度互連接 (Ingh-denshy interconnect)或Hm板之幾個電路板層之 導電通道(passage)或微小穿孔(mien>via)而施行料 ⑩元件、或個別元件之拆解。 +隨著電子元件之複雜性的進一步增加及因此涉及 至電路板之連接的數量之增加、及/或進一步減少此 二之尺寸’其將同樣導致相鄰連接之間的距離之減; 大里增加%路板層數期望能符合所需的拆解。然而,声 此種電子元件之複雜性連同減少用強化曰 互間距離將使得個別連接之、^^ 二或導電結構變得最小, 為u不如此將立即要求進—步增加所需電路板: 93969 6 200814884 /層數。然而,此種電路板之額外的層將造成增加電路板之 '厚度’而且,增加產品成本。 . -種減少電路板的數量之方法為使用非常細或者 =導電結構’然而其中目前即使有可能取得生產此種: 或者超細的導電結構,亦可預期包括此種超構 產品在譬如像是一之高密度冗 式’不能使得充分精確地製造電路板層,以便 =如1供在設有此種超細的導電㈣或導電 層之間的導電連接。 丨口⑺敬 根據該最初定義種類之方法 、… ± ^ , m Vl· ^ ^ 及該取初疋義種類之 目標是要避免上述關於使用增加複雜 連接門之/… 7°件而因此減少連接到電路板之 =間之小的相互距離之問題’藉由實質上未改變電路板 泛又计’以及尤其使之能拆解此 種回腹雜的元件(特別是小 尺寸),同%避免需要額外的電路板層。 【發明内容】 ^ 欲達成上述目的,一種用來帝 — 上及/或將該電子元件接觸於^2子 著於電路板 徵為下列步驟·· 該电路板之方法,其實質上特 _提供該電路板有複數個接觸或連接表面; -提供該電子元件有對靡私兮 t鱼妓本u h 電路板之該複數個接觸 或連接表面之多個接觸或連接位 罟夕妞方π咕# 4 置該多個接觸或連接位 置之相互距離係相對於該電路 而減少;以及接觸或連接表面之距離 93969 7 200814884 , 在該電路板之接觸或連桩矣;# + .或連接位置之間安排:成至:=r:L之接觸 ,電子元件之接觸或連接位置。们中間層,用來拆解該 連接♦面=、^明’於已提供該電路板有複數個接觸或 =表面:二供該電子元件有對應數目之接觸或連接位置 接位置之^少一個用來拆解該電子元件之該接觸或連 面盘係安排或形成於該電路板之接觸或連接表 子元::之相關接觸或連接位置之間 拆解今雷f附者至、或將接觸於該電路板’而不增加用來 :用電路板層之數目,已成為可行,其中,該電子元= (1用=高複雜性並因而包括較大量之對該電路板之連接 (在㈣個別連接之間的同時減少距離)、及/或具有減少尺 依照本發明所提供之該中間層可具有相對 而板層之厚度而減少之厚度’尤其是介電層或薄膜, 而使钎可忽略該整個電路板所增加之厚度,尤其是考 =員型之電路板通常會包括複數個(例如多於4個,:其 =多於6個)電路板層’而同時仍能夠安全拆解中間芦= =之單層或夾層_。若使用了包含極大數目之接二戈 連接位置之高度複雜之元件,則可提供超過一個包含個別 通孔(feedthr〇Ugh)之中間層,然而,其中即使提供了超 過:個中間層,如此將可獲得相關於提供增加數目之額外 的電路板層之不變之大優點,相較於習知的電路板、 幅減少之厚度和簡化建構之電路板。 93969 8 200814884 口此心、藉現有用來形成具有複數個電路板層之♦ 板之技術為可行的,特別是當考慮到對齊此等電路板^之 個別次區域之精確要求時,同時適當的非常細或者超二的 導電線雜aek)或結構可設於詩拆解之該中間層之 中而α此大的部分區域或接觸區域可設於用於該電^ 件之接觸或連接位置以及該電路板之連接或接觸表面之個 別接觸或連接的該中間層上。 ㈣如ί述已經表示之’將使用較通常電路板層而有簡化 、、口構之中間層來拆解,在此方面較佳提出,中間層係带 =於接觸區之間之導電線跡或結構,該等 庫 該電子元件之接觸或連接位置和對應於該電路板之 接Γ:中間層僅形成有位於接觸區(對應於㈣ 表面)之間之導電線跡或結構,故可提供 -連接 或者超細的導電線跡或導電結構,且:二1吊細 =形成於中間層上或中間層内,使得此等元件間之連接 的相互距離(其當使用複雜㈣時會減少)不1對可= 中間層中實施或提供導電線跡構成任何的_此、 土為了確保該電子元件與用於拆解之該中間層之 ::Γ二t照較佳實施例兹提出該電子元件之接觸或連 接位置與该中間層之間之接觸係透 (contact)而實現。 、°亥包子兀件之接點 依照修改之實施例,本發明較佳地提出兮+ 接觸或連接位置係直接與該中間層之接點區二,:二 93969 9 200814884 丫i如知接或接合之連接,而亦改進 认h 連接或固定。電子兀件於電路板上之 成於:=發明之另一較佳實施例,提出該中間層係僅形 減少之材料耗用,因為後】;=r間層時將涉及 ,件或該電子元件於該電路板;=需=:著電:元 到該龟路板之個別接觸或連揍表面、心 件之接觸或連接位置之㈣增加。S /㈣於電子元 是二:::降:成本及/或形成小型的整體結構,尤其 較:,:Γ:Γ電路板時’依照本發明之另-個 接觸或連接表面而附著於該電==向朝離開該電路板之 r m 书路板上,亚且該電子元件择 會:並==、厚度之該中間層提供拆 行,使得用於該電子元件之电額外2之支撐功能也將會實 以便不僅使得能夠減少包括該路得以免除, M ^ ^ 发包路扳和該至少一個雷+开 正個系統的尺寸,而且亦減少整體之成本。 欲達成開始時提及之g # 子元件之接觸或連接位置與兩路一種用來產生用於拆解 間層之方法,且盘所 厂、包板之接觸或連接表面之中 4八只貝上特徵為下列步驟: 93969 10 200814884 -V. , -提供該電路板有複數個接觸或連接表面; 、 -至少於該電路板之接觸或連接表面之FA/ .中間層之基礎材料; 妾表面之£域内形成該 -建構該中間層以形成導電線跡或結構,以用來盘該 t板之接觸或連接表面接觸及與將要附著於該電路^之 龟子元件之接觸或連接位置接觸。 或、車^上述已^才曰出的’於已提供該電路板有複數個接觸 • ίϊ 之後,以簡單的方式使用於拆解之至少-個中 響間層可用於將要隨後附著之電子元件為可行的。 跡或可祕成包括尤其是非常細或者超細的導電線 知:消:广中間層,兹再提出藉由就其本身而言為已 ^減(subt⑽ve )技術、半加成(semi_addi㈣技術、 而口施ri中及/或嵌入(emb〇SSing)技術或雷射建構技術 用於^ Γ層之建構’如對應於依照本發明之用來產生 ;斥解之中間層之較佳實施例。 為了接收或實現支稽後續將附著㈣電路板之電子 (在插入用於拆解之中間層後)之功能,依照本發明之 ^較ί實施例提出W建構該中間層後,祕該電子元 ❹Γ者或接觸之額外較撐層健設於用於拆解之該中 曰j ,該額外的支撐層並設有用於該電子元件之接點。 1如上述已經提及的,依照本發明可較佳地提供,尤其 =綠f到用於拆解之該中間層僅包含# ^或者超細的導 ^心或導電結構(除了將提供用於與該電子元件與該電 觸之接觸區外),該中間層係形成有相對於電路板層 93969 11 200814884 ,的厚度而減少之厚度。 " 關於此點,佑日S 士政an •間層之厚度传選擇;; 特定較佳實施例提出,該中 少於三分之二2〉、於電路板層的厚度的一半,尤其是 例如35至4〇㈣施’例如具有介電薄膜厚度低於 画電路板之血二:低至1〇/Zm或更少)之中間層,而 80㈣。、型"電缚膜厚度為至少6一,例如超過 ^了拆解該電子元件之接合接連 鲁因此在該中,中餘〇 、 ϋ安觸$運接位置’ 在此方而分非吊細或者超細的導電結構,其中 在方面依照本發明之另一較佳奋絲彻担山 有寬度選擇為少於5心3 該中間層設 或導電結構。心(尤其疋少於、啦導電線跡 施二述Γ經提及的’依照本發明之另-實施例可實 尤π為了進-步減少成本和簡、 個4欠達:開始時提及之目的’一種包括電路板和至少-=子-件之糸統,實質上特徵在於:至少一個中間声, H足該電路板之接觸或連接表面拆解該電子元件之躺 ==位置,該中間層係安排或形成於該電子元件之接觸 或連接位置與該電路板之接觸或連接表面之間/以帝 ^件之接觸或連接位置包括相對於該電路板之接觸或^ f立置而減少之相互距離。因此,僅藉由提供至少-個且 有比較小厚度之中間層而確保拆解為可行的,_ 93969 12 200814884 s較佳地設於或可僅部分設於該電路板之接觸或連接表面以 ‘及將連接至該電路板之該電子元件之接觸鱗接位置之區 ' 域中,如上述已經表示者。 依照較佳實施例’在此方面提出該中間層係形成有 接觸區之間的導電線跡或結構,該等接觸區對應於該電子 凡件之接觸或連接位置和該電路板之接觸或連接表面。 ^欲簡化該電子元件之附著和接觸,再提出用於該電子 兀件之附著和接觸之額外的支撐犀 、,一丨J文塚層係敷设於用於拆解之該 中間層上’亚设有用於該電子元件 士於旭—口 几仟之接點,如對應於依胛 本叙明之另一較佳實施例。、 >已經表讀:欠的,較佳地可提供該右 對於雷跋;θ &戚有相 ::::: 減少之厚度’其中,依照特定較佳 :該中間層之厚度係少於電路板層之厚度之一 丰,尤其是少於三分之一。 此外,較佳地提出該中間凡 構,该導帝 9 "又有^电線跡或導電結 冓4,線跡或導電結構之寬度係少於 少於30#m。 尤其是 為了使用未封裝之電子元件以及為了方便 路板和接觸於該電路板,依照 蔣者;电 層係用作為用㈣^ + 只知例&出該中間 用於该电子几件之支撐或封閉。 如已經表示數次的,依昭 層較佳地可使用尤A β ^ " 用於拆解之該中間 板,其中,再提出以太& & 口包路扳層之電路 捉出Μ本身為已知方式使 士 個疊置之電路板層,兮望a定电路板形成有複數 -專电路板層至少部分係藉由連接個 93969 13 200814884 別電路㈣之導電通道(⑶nduetive passage)或 :=:r互連接’如對應於依照本發明之系統之另- 【實施方式】 3且心地减不系统1、系統1包括電路板、尤其 :者個:層之HDI板2,以及將連接並 刖者之電子7L件3,雷;;从1 Μ 件3係以用於拆解之配置在電 :::。3與電路板2之間之中間… 夕厂1圖中可看出’中間層4包括對應於電子元件3 之夕個接觸或連揍位置5 數 之數目的I數個接點或連接區 2上^觸直触合於對應於設在電路板 二二表面8之接點或連接區7。從第1圖中可 >:疋看出電子元件3之相鄰接觸或連接位置5 = 係小於電路層2之相鄰接觸或連接表面8之間之 = 此一炎,盔7 士人山_ 〜间心此離,如 此不為了於中間層4之拆解,非堂知十& Λ 跡戋導電社i盖筏L 卜吊、、、田或赵細的導電線 外地包括,以提供與中間層4 接點或連接區7之連接,透過中間層實 乂 路板2之連接或接觸表面8接觸/係只貝有效地與電 相對於已知之習知技術,藉由選擇性地 於含 複雜之電子元件 ^ U於间度 或微小穿f之用於拆解之通道 路拓 $ 70件3之連接或接觸位置或諸連接鱼電 :板2之相關連接或接觸表面8之間之中間連接得二 見’依照第」圖之配置確保經由中間層4之完全拆解, 93969 14 200814884 在雷:依:!Γ圖之配置中,用於拆解之中間層4僅僅設 在電子兀件3之接觸或連接位置$以及電路板2之連接或 接觸表面7之區域,使得完成部分形成中間層4。 再者,,亥中間層之厚度不表示相對於各圖式中之電路 板2和電子元件3之大小或尺寸而比例縮放。考慮到非常 細或者超細的導電線跡或導電結構 : M Q θ 線跡或導電結 構9可例如具有小於5〇/^、例如大約25心之寬度,用 =間層4之該介電質膜之厚度係大約為…W等級, 此係少於電路板2之板層之介電質膜之通常厚度的一半。 此外氣中間層4之該介電質膜之厚度達…m或低於10 A 111為可使用和應用的。 +於昂1圖中所表示之實施例中,用於拆解之中間層4 子元件3之連接或接觸位置5之間的接觸係透過^電 而A現’導電接點10係接收或提供於由11所示意 曰不之载件層(carrierlayer)或支撐結構中。 取代對應於電路層2之接觸或連接表面8以及電子元 接觸或連接位置5之用於拆解之中間層4之僅僅部 二置,中間層4以及尤其是中間層4之基礎材料,可實 :被塗佈或提供於電路層2之整個表面、具有接觸 2上\之個別結構、以及被僅僅被設在或形成在電路層 之该(或-個)電子元件3之附著或接觸區之導電線 93969 15 200814884 , 第2圖示意地描繪用於產生系統i之方法#引 / :=〜子元件’一形成 於步驟(a)中,提供電路板’尤其是職板2, 適當的連接或接觸表面8係已經形成和表示。一中 於步驟(b )中,施加用於中間層上 中,分別執行建構接點或連接匚=二 •之導電線跡9。用來結構中間層4 來 ,舨弟3圖而於後文中討論。 ^ 接續於建構或形成用於拆解之中間層4後,於 … 中有效的應用額外的堆疊⑽e)或支撐層μ工产此 依照步驟⑴,藉由例如提供接點10 構康^ 支撐層或堆疊11和12。 只見建構和元成 最後,於步驟(f)中,電子元件 耦 =解之中,,並接續著經由連接或::置連= 置接點10時而與電路板2連接。 田才 第3圖示意地顯示使用例如本身為已知之嵌 夾 建構或形成中間層4之部分步驟再 ^何末 成或建構用於拆解之中門芦4 應再庄思的疋,對於形 由, 轉之中間層4,相對於大致表示於第3圖 中之極細導電體結構,中間層4之建構僅僅施行於—側。 ::第3圖於步驟⑴巾,使用㈣入工具…將 、、友和結構(relief structure)嵌入於刼输柳+ 層4之喪入。 )甘入入於熱塑膠膜上以實現中間 於步驟⑴中,可能的剩餘留存材料係藉由例如反 93969 16 200814884 =性=_而去除,以便使能夠產生穿透孔或微小穿孔 .俜與二於敕依恥步驟(C),薄導電材料製成之晶種層薄膜 H 此種只鈿方式例如可用濺鍍或熱蒸 /li "L積而有效達成。 j成此步驟後’依照步驟(d)緩和結構被鑛銅,而 赤據♦式而建立之犬起銅於步驟(e)中係藉由例如化學 理絲,以便使能夠如t間層4所希望之結構功 月b ’依照電子元件3之接觸戋遠接 觸或連接〆 接觸次連接位置5和電路板2之接 =連接表面8以及所希望之超細導電線跡9之位置而形 成接觸區ό和7 〇 為了產生中間層4,可使用像是例如聚醚亞胺 ΤΓΡρ/1ί1ΐ6Γ1Ιηΐά6) ' (^quid crystal polymer ; LCP)熱塑材料。 者不使用熱塑材料,建構中間層4可以使用, 外線可固化(uv_curable)材料。 、=者’說明於㈣⑷和(d)之導電層之應用可用 將¥电材料填充於凹入或凹陷部而予以替代。 代之使用喪入技術,可藉由例如雷射光來達成去除 於中間層4之聚合物材料。 、為了分別建構該電路板或配置導電連接或接觸區6和 7、以及導電線跡9,可使用已知的消減技術、半加成技術、 加成技術。 一^第4至7圖中所示之範例實施例中,前面圖式中之 凡件们虎’尤其是第i圖中之元件符號維持使用於相同的 93969 17 200814884 元件。 依照第4圖之例不,電子元件3之附著係再經由中間 層4上之接點10而實現,而與電路板2接觸,其中第4 圖額外詳細繪示了電子元件3,由該圖中尤其顯然看出電 子元件3被配置於板形支撐結構15上並由護套(sheathing) 16所環繞。 從依照第5圖之修正例示中,很清楚看出再由3表示 之電子元件被插入而沒有第4圖中所示之各自之支撐結構 和護套結構15和16’而是經由再由5所表示之連接或接 觸位置而直接與用於拆解之中間層4之個別接觸區6連 或耦接,經由此情形連接或接合到再由2表示之電路板經 由連接或接觸表面8而被後續實施。 依照第5圖之配置中,用於拆解之中間層*再直接用 作為支撐結構,而因此實現用於電子元件3之支撐或 ^ ’使得額外的接點可免除。此結果減少成本,同時加 強電子元件3到中間層4、並因此到電路板2之連接。 :了適當地固定和保護未封裝之電子元件」 子疋件3並被支擇於用於拆解之中間層4上 於依照第5圖之實施例中。录不 於依照第6圖之實施例中,使用未封裝之電子丰 Π元件:係直接與用於拆解之中間㈣接。在二元 之上表不另外的層18和19,且 ^ ^ =中’表示有額外的多個接點或遠接二該 接-係用來附著其他的元件,該其他的元件未顯示二連6 93969 18 200814884 圖中。弟6圖所不之實施例中此等其他 由 ’點之接觸再依於插入之用於拆解之-由^或接 . 於第7圖所表示之實施射,電子元件^知。 被配置在電子%件3之上,刻電路板2之^曰 面8再有效於後續的接觸。於依照第6和7圖之每/表 因此能釣立即使電子元件3整合,如此造成谁^例中, 式元件之整合,拎ή哆—ώ k成進一步之嵌入 11二人 密度同時減少系統的整個尺寸。 亦^ 於電子元件3之該多個連接或接觸位置5 亦4路板2之該複數個接觸或連接表面 之具有減少厚度之中間層4(尤其關間=拆解 扳層之;度比幸父時)將因此足夠使得於主要 :發生可忽略之增加整個電路板之厚度。 再者,於大多數之情況將實施用於拆解之單一 接,用於拆解之中間層4相對於通常的電路板層,僅^ 1區6和7以及非f細或者超細的導電線跡或導電結構 蠢接觸區6和7以及非常細或者超細的導電線跡或導電姓 ,9可調適於高度複雜之電子元们之連接或接觸… t的距離,而不需要複數個層以及尤其用於拆解此等高 度裣_之電子元件3之額外的電路板層。 士當使用包括極大數目之連接或接觸位置之電子元件3 蚪,筹數目可以從數百至數千之範圍,而且,可提供另一 =間層施用或沉積於中間層4上,例如依照第3圖中所示 -例不之方法’其中設有適當的通孔或微小穿孔用來與配 93969 19 200814884 置於下方之電路板2、或形成電路板2之該 應該銘記於心的是此種選用所需額外的心 外的電路板層及尤其是其介電層之厚度^ 拆:m外應該銘記於心的是,由於此種用於 έ ^ 4之簡化結構,該後者實質上係包括僅非常
由者超細的導電線跡結構9,而致可③、略電路板2連同 2層4之整體厚度之增加,較超過多於-個中間層4 ϋΓ用?拆解高度複雜之電子元件3之區域。反之,必 .思令疋用經由額外的電路板層而隨意地試圖拆解, 帝I於中間層4之簡單結構,電路板結構更複雜時, 恭板層之數目將必須相當地增加,而使得因此高度增加 屯路板2之整體厚度,以及涉及產品之成本增加。
位^ ^卜’、配置薄的中間層4使得可實行提供較大的連接 去置或區域’以便符合個別層之記錄正確性之要求,甚至 萨吏用大尺寸之印刷電路板(尤其是,板)產品格式 $。於考慮到厚度減少時,錐形的或圓錐形的孔設在通道 的區域將需要小的空間,因此降低記錄或方向精確性的要 求。 【圖式簡單說明】 以上係藉由範例實施例配合附圖式而做更詳細之說 明。各圖中·· 第1圖為依照本發明之系統之部分剖示圖,該系統包 括包路板和附著於該電路板之電子元件,該系統使用依照 本务明用於拆解之中間層; 20 93969 200814884 第2 (a)至2(f)圖為示意地顯示用於施行依照本發 , 明之用來將電子元件附著於電路板並同時形成或安排用於 4 拆解之中間層的方法之個別步驟; 第3 (a)至3 (e)圖為示意地顯示將被分另U使用於依 照本發明之方法和依照本發明之系統中用於形成用於拆解 之中間層之個別方法步驟; 第4圖相似於第1圖之顯示,詳細描繪依照本發明之 系統之電子元件,相較於第1圖為尺寸縮小關係; ⑩ 第5圖相似於第4圖之顯示,描繪依照本發明之系統 之另一修正實施例,具有整合之未封裝之電子元件; 第6圖相似於第4和5圖之顯示,描繪依照本發明之 系統之另一修正實施例,該電子元件係直接應用在用於拆 解之中間層上;以及 第7圖再相似於第4至6圖之顯示,描繪依照本發明 之系統之另一修正實施例,用於拆解之中間層係應用在整 φ合於電路板中之電子元件上。 【主要元件符號說明】 1 系統 2 電路板(HDI板) 3 電子元件 4 中間層 5 接觸或連接位置(連接或接觸位置) 6 接點或連接區(連接或接觸區) 7 接點或連接區(連接或接觸表面)(連接或接觸區) 21 93969 200814884 8 接觸或連接表面(連接或接觸表面) 9 導電線跡 4 10 導電接點 11 載件層(堆疊或支撐層) 12 堆疊或支樓層 13 嵌入工具 14 穿透孔或微小穿孔(microvias ) 15 板形支撐結構 • 16 、 17 護套(sheathing ) 18、19 層 20 接點或連接 22 93969

Claims (1)

  1. 200814884 十 1. 、申睛專利範圍: -種用來將電子元件⑴附著至電路板⑺上 將該電子㈣⑴接觸於該電路板⑴之方法,勺或 括下列步驟·· 匕 々供該電路板⑺有複㈣接㈣連接表面(8); 供該電子元件⑴有對應於該電路板之該複數 蜀或連接表面(8)的多個接觸或連接位置(5), S子元件(3 )之邊多個接觸或連接位置(5 ) 互距離係相對於該電路板(2)之该箄接鈣$& ⑴之距離而減少;以及 亥4接觸或連接表面 在該電路板⑺之該等接觸或連接表面⑴* 排或形成至少一個用於批㈣币^位置(5)之間安 H連子元件(3)之該等接 觸足連接位置(5)的中間層(4)。 2·如申請專利範圍第!項之方法,其中,該中 、 係形成有位於接觸區之M 咕' 间7 ¥電線跡或結構(9),竑 倾觸區對應於該電子元件⑶之接 2 面(8)。 该4接觸或連接表 ;·如申請專利之方法,其中, =⑴之該等接觸或連接位置(5)與該中間層⑷ ::接觸係透過該電子元件(3)之接點而達成。 ::請專利範園第1或2項之方法,其中,該電子元 ⑴之接觸或連接位置⑸與該中間層⑷之接 93969 23 4· 200814884 觸區係直接接觸。 5. 如申請專利範圍第1至4項中任一項之古 該中間声f 4# 員之方法’其中, 或連接/ 成於該電路板(2)之該等接觸 次連接表面(8)以及該電子 予得觸 6. 連接位置(5)之區域中。)之該等接觸或 如申請專利範圍第】至5項中任方立 該電子元件(3)孫围—a* 、之方法’其中, 連接位置“ 朝離開該電路板(2)之接觸或 it而附著至該電路板⑺上,並且該電 ,等接由用於拆解和連接到該電路板⑴之 二等接觸或連接表面⑴的該中間層(4)覆蓋。 ,種用來產生用於從電路板(2)之接% + & ^ _子元件⑺之接觸或Ht(5=i(8) ⑷的方法’包括下列步驟置(5)的中間層 _提供該f路板(2)錢數個接料連接表面⑴; 之電路板⑺之該等接觸或連接表面⑴ 之區域中形成該中間層⑷之基礎材料,· -建構該中間層(4)以形成導電線跡或結構⑼ =接觸位置(6,7),以用來與該電路板⑵之接觸 或連接表面⑴接觸及與將要附著至該電路板⑺ 上之電子元件⑶之接觸或連接位置⑸接觸。 ,申請專利範圍第7項之方法,其中,建構該中間層 ⑷係猎由就其本身而言為已知之消減技術、半加成 技術、加成技術、及/或嵌入技術或雷射建構技術而施 行0 93969 24 8. 200814884 9·如申請專利範圍第7或8項之方, :μ層⑷之後’用於該電子元件(^ ’在建構該 •⑽物)係敷— 日1曰(4)上亚设有用於該電子元件( 10·如申請專利範圍第7、8或9項之方法妾點(上10)。 層(4)係形成有相對於電路板 ”、中省中間 11 ^ ^ 之7子度而減少之厚彦。 H·如申睛專利範圍第10項之方 置 之知度 之該厚戶 /、中,該中間層(4) &巧y予度係选擇為少於電路板 ,是少於三分之一。層之居度之—半,尤其 如申請專利範圍第7至u項中任一頊 該中間層(4)設有導電線 、法,其中’ 導電線跡或導^導電結構(9),該等 尤其是少於=、:()之見度係選擇為少於—, 丨細第項中任一項之方法,其中, 及/或二⑷係用作為用於該電子元件⑶之支樓 14· 一種包含電路板( 續,勺虹 )和至少一個電子元件〇)之系 、,死 包括:至少一個中 之接觸或連接表面(8):斥:二於:該電路板⑺ 凡件(3)之接觸 雷早- /中間層(4)係安排或形成於該 柘/ < 之5亥等接觸或連接位置(5)與該電路 子之。亥等接觸或連接表面(8)之間,以及該電 位置(5)包括相對於 X寻接觸或連接位置(8)而誠少之 93969 25 200814884 相互距離。 曹 .. .I5.如申請專利範圍第14項之糸 , 俜形忐古办产拉總 、糸、、先’其中,該中間層(4 ) (9) , 之間的導電線跡或結構 等接觸或連接位置(;)=該電子元件⑴之該 等接觸或連接表面(8)。…於該電路板(2)之該 16.如申請專利範圍第14或15項 雷早分氹^ 貝之糸統,其中,用於該 冤子兀件(3)之該附著和接 係接觸頜外的支撐層(11) 你敷, 又於用於拆解之該中 -fir ^ ^ ^ ] 3 (4)上並設有用於該電 于凡件(3)之接點(1〇)。 17·如申請專利範圍第14、】 中η展m产 或項之系統,其中,該 中間層(4 )係形成有相對 厚度。 了於电路板層之厚度而減少之 18. 如申請專利範圍第 夕# m ^ , 之系統,其中,該中間層(4) 該;度係少於電路板層之厚 三分之一。 予度之—+,尤其是少於 其中, 該等 ,尤其 其中, 19. 如申請專利範圍第14至18項中任_ 該中間層(4)設有導電缓 、之系統 、 電線跡或導電結構( 導電線跡或導電結構(9 )之嘗译 是少於。 見度係少於5一 μ.如申請專利範圍第14至19 / 該中n爲“、γ Τ任項之系統,其中 曰1 ()係用作為用於該電子元件 及/或封閉。 I )之支梡 21·如申請專利範圍第14至 貝甲任一項之系統,其中, 93969 26 200814884 以本身為已知方式使該電路板(2)形成有複數個疊置 . 之電路板層,該複數個電路板層係至少部分藉由連接 j 個別電路板層之導電通道或微小穿孔而相互連接。 27 93969
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