TW200707586A - Semiconductor apparatus and manufacturing method therefor - Google Patents

Semiconductor apparatus and manufacturing method therefor

Info

Publication number
TW200707586A
TW200707586A TW095113213A TW95113213A TW200707586A TW 200707586 A TW200707586 A TW 200707586A TW 095113213 A TW095113213 A TW 095113213A TW 95113213 A TW95113213 A TW 95113213A TW 200707586 A TW200707586 A TW 200707586A
Authority
TW
Taiwan
Prior art keywords
gate electrode
insulating layer
upper face
formed over
side wall
Prior art date
Application number
TW095113213A
Other languages
English (en)
Chinese (zh)
Other versions
TWI308779B (enExample
Inventor
Tsuyoshi Serata
Shuji Enomoto
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW200707586A publication Critical patent/TW200707586A/zh
Application granted granted Critical
Publication of TWI308779B publication Critical patent/TWI308779B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/50—Alloying conductive materials with semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0137—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
TW095113213A 2005-04-14 2006-04-13 Semiconductor apparatus and manufacturing method therefor TW200707586A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005116618A JP2006295025A (ja) 2005-04-14 2005-04-14 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
TW200707586A true TW200707586A (en) 2007-02-16
TWI308779B TWI308779B (enExample) 2009-04-11

Family

ID=37077886

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095113213A TW200707586A (en) 2005-04-14 2006-04-13 Semiconductor apparatus and manufacturing method therefor

Country Status (5)

Country Link
US (1) US20060252196A1 (enExample)
JP (1) JP2006295025A (enExample)
KR (2) KR100748906B1 (enExample)
CN (2) CN101425540A (enExample)
TW (1) TW200707586A (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100755671B1 (ko) * 2006-07-14 2007-09-05 삼성전자주식회사 균일한 두께의 니켈 합금 실리사이드층을 가진 반도체 소자및 그 제조 방법
JP5315779B2 (ja) * 2008-05-09 2013-10-16 富士通セミコンダクター株式会社 半導体装置の製造方法
KR101080200B1 (ko) * 2009-04-14 2011-11-07 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 리프레쉬 제어 방법
KR102301249B1 (ko) * 2015-11-16 2021-09-10 삼성전자주식회사 반도체 장치
JP7034834B2 (ja) * 2018-05-30 2022-03-14 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR102675935B1 (ko) * 2019-12-16 2024-06-18 삼성전자주식회사 반도체 소자

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW232751B (en) * 1992-10-09 1994-10-21 Semiconductor Energy Res Co Ltd Semiconductor device and method for forming the same
JP3382743B2 (ja) * 1995-01-27 2003-03-04 株式会社リコー 半導体装置の製造方法
US6060387A (en) * 1995-11-20 2000-05-09 Compaq Computer Corporation Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions
US5731239A (en) * 1997-01-22 1998-03-24 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance
JPH11233770A (ja) * 1997-09-02 1999-08-27 Sony Corp 半導体装置の製造方法
US6306712B1 (en) * 1997-12-05 2001-10-23 Texas Instruments Incorporated Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing
JP3168992B2 (ja) * 1998-09-08 2001-05-21 日本電気株式会社 半導体装置の製造方法
US20010053572A1 (en) * 2000-02-23 2001-12-20 Yoshinari Ichihashi Semiconductor device having opening and method of fabricating the same
US6803318B1 (en) * 2000-09-14 2004-10-12 Cypress Semiconductor Corp. Method of forming self aligned contacts
US6376320B1 (en) * 2000-11-15 2002-04-23 Advanced Micro Devices, Inc. Method for forming field effect transistor with silicides of different thickness and of different materials for the source/drain and the gate
KR100396469B1 (ko) * 2001-06-29 2003-09-02 삼성전자주식회사 반도체 장치의 게이트 전극 형성 방법 및 이를 이용한불휘발성 메모리 장치의 제조방법
JP3657915B2 (ja) * 2002-01-31 2005-06-08 株式会社東芝 半導体装置および半導体装置の製造方法
US6657244B1 (en) * 2002-06-28 2003-12-02 International Business Machines Corporation Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation
CN1270362C (zh) * 2002-09-18 2006-08-16 上海宏力半导体制造有限公司 形成自行对准金属硅化物的方法
JP4057985B2 (ja) * 2003-09-19 2008-03-05 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
KR20070062957A (ko) 2007-06-18
KR100748906B1 (ko) 2007-08-13
CN100501948C (zh) 2009-06-17
US20060252196A1 (en) 2006-11-09
KR20060108537A (ko) 2006-10-18
JP2006295025A (ja) 2006-10-26
CN101425540A (zh) 2009-05-06
CN1848392A (zh) 2006-10-18
TWI308779B (enExample) 2009-04-11
KR100754262B1 (ko) 2007-09-03

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees