TW200705594A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
TW200705594A
TW200705594A TW095121404A TW95121404A TW200705594A TW 200705594 A TW200705594 A TW 200705594A TW 095121404 A TW095121404 A TW 095121404A TW 95121404 A TW95121404 A TW 95121404A TW 200705594 A TW200705594 A TW 200705594A
Authority
TW
Taiwan
Prior art keywords
metal wiring
electrode
inspection
manufacturing
semiconductor device
Prior art date
Application number
TW095121404A
Other languages
English (en)
Inventor
Kazumi Watase
Akio Nakamura
Katsumi Ootani
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of TW200705594A publication Critical patent/TW200705594A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2853Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228Resistive arrangements or effects of, or between, wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW095121404A 2005-06-17 2006-06-15 Semiconductor device and its manufacturing method TW200705594A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005177067 2005-06-17
JP2006102611A JP4592634B2 (ja) 2005-06-17 2006-04-04 半導体装置

Publications (1)

Publication Number Publication Date
TW200705594A true TW200705594A (en) 2007-02-01

Family

ID=37573889

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095121404A TW200705594A (en) 2005-06-17 2006-06-15 Semiconductor device and its manufacturing method

Country Status (3)

Country Link
US (1) US7595557B2 (zh)
JP (1) JP4592634B2 (zh)
TW (1) TW200705594A (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011014434A2 (en) * 2009-07-31 2011-02-03 Altera Corporation Bond and probe pad distribution and package architecture
US9267985B2 (en) * 2009-07-31 2016-02-23 Altera Corporation Bond and probe pad distribution
JP2011249366A (ja) 2010-05-21 2011-12-08 Panasonic Corp 半導体装置及びその製造方法
JP2014139985A (ja) * 2013-01-21 2014-07-31 Renesas Electronics Corp 半導体装置
US9704809B2 (en) * 2013-03-05 2017-07-11 Maxim Integrated Products, Inc. Fan-out and heterogeneous packaging of electronic components
US9082765B2 (en) * 2013-03-08 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace (BOT) structures and methods for forming the same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6148927A (ja) 1984-08-16 1986-03-10 Matsushita Electronics Corp 半導体装置
JPH03278552A (ja) * 1990-03-28 1991-12-10 Nec Corp 半導体集積回路装置
JPH05144901A (ja) 1991-11-21 1993-06-11 Oki Electric Ind Co Ltd 微細パターンを有するデバイスの不良箇所検出方法
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
JPH06120307A (ja) 1992-10-08 1994-04-28 Matsushita Electron Corp 半導体装置
JPH09330934A (ja) * 1996-06-12 1997-12-22 Toshiba Corp 半導体装置及びその製造方法
JPH11274252A (ja) * 1998-03-19 1999-10-08 Mitsubishi Electric Corp 半導体装置の検査装置及びその検査方法
US6233184B1 (en) * 1998-11-13 2001-05-15 International Business Machines Corporation Structures for wafer level test and burn-in
JP2000294730A (ja) * 1999-04-09 2000-10-20 Mitsubishi Electric Corp システムlsiチップ及びその製造方法
JP2002039801A (ja) 2000-06-08 2002-02-06 Internatl Business Mach Corp <Ibm> 特性値表示方法および特性値表示装置
US6590225B2 (en) * 2001-01-19 2003-07-08 Texas Instruments Incorporated Die testing using top surface test pads
JP2002296314A (ja) * 2001-03-29 2002-10-09 Hitachi Ltd 半導体デバイスのコンタクト不良検査方法及びその装置
TW558772B (en) * 2001-08-08 2003-10-21 Matsushita Electric Ind Co Ltd Semiconductor wafer, semiconductor device and fabrication method thereof
JP3940591B2 (ja) 2001-11-28 2007-07-04 沖電気工業株式会社 半導体装置の電気特性のシミュレーション方法
JP2004253445A (ja) * 2003-02-18 2004-09-09 Renesas Technology Corp 半導体装置およびその製造方法
JP2004296464A (ja) * 2003-03-25 2004-10-21 Denso Corp 半導体装置
JP4409348B2 (ja) * 2004-04-26 2010-02-03 三菱電機株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JP2007027685A (ja) 2007-02-01
US20060286689A1 (en) 2006-12-21
US7595557B2 (en) 2009-09-29
JP4592634B2 (ja) 2010-12-01

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