TW200643724A - System for improving bandwidth among a plurality of memory controllers and method thereof - Google Patents

System for improving bandwidth among a plurality of memory controllers and method thereof

Info

Publication number
TW200643724A
TW200643724A TW095112623A TW95112623A TW200643724A TW 200643724 A TW200643724 A TW 200643724A TW 095112623 A TW095112623 A TW 095112623A TW 95112623 A TW95112623 A TW 95112623A TW 200643724 A TW200643724 A TW 200643724A
Authority
TW
Taiwan
Prior art keywords
memory controller
output signal
busy
data bus
write
Prior art date
Application number
TW095112623A
Other languages
English (en)
Inventor
Eric Matulik
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of TW200643724A publication Critical patent/TW200643724A/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
TW095112623A 2005-04-15 2006-04-10 System for improving bandwidth among a plurality of memory controllers and method thereof TW200643724A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0503811A FR2884629B1 (fr) 2005-04-15 2005-04-15 Dispositif d'amelioration de la bande passante pour des circuits munis de controleurs memoires multiples
US11/183,052 US20060236007A1 (en) 2005-04-15 2005-07-15 Apparatus to improve bandwidth for circuits having multiple memory controllers

Publications (1)

Publication Number Publication Date
TW200643724A true TW200643724A (en) 2006-12-16

Family

ID=35005757

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095112623A TW200643724A (en) 2005-04-15 2006-04-10 System for improving bandwidth among a plurality of memory controllers and method thereof

Country Status (4)

Country Link
US (2) US20060236007A1 (zh)
CN (1) CN101160569A (zh)
FR (1) FR2884629B1 (zh)
TW (1) TW200643724A (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2884629B1 (fr) * 2005-04-15 2007-06-22 Atmel Corp Dispositif d'amelioration de la bande passante pour des circuits munis de controleurs memoires multiples
US7433262B2 (en) * 2006-08-22 2008-10-07 Atmel Corporation Circuits to delay a signal from DDR-SDRAM memory device including an automatic phase error correction
US7539078B2 (en) * 2006-08-22 2009-05-26 Atmel Corporation Circuits to delay a signal from a memory device
US7941594B2 (en) * 2007-09-21 2011-05-10 Freescale Semiconductor, Inc. SDRAM sharing using a control surrogate
US8312299B2 (en) * 2008-03-28 2012-11-13 Packet Digital Method and apparatus for dynamic power management control using serial bus management protocols
JP4674614B2 (ja) * 2008-04-18 2011-04-20 ソニー株式会社 信号処理装置および制御方法、信号処理方法、プログラム、並びに信号処理システム
JP2017097633A (ja) * 2015-11-25 2017-06-01 日立オートモティブシステムズ株式会社 車両制御装置
US10216454B1 (en) * 2017-08-24 2019-02-26 Advanced Micro Devices, Inc. Method and apparatus of performing a memory operation in a hierarchical memory assembly
US10789015B2 (en) * 2019-03-01 2020-09-29 Micron Technology, Inc. Background operations in memory
CN113971143B (zh) * 2021-10-22 2023-12-05 展讯半导体(成都)有限公司 一种内存控制器、物联网芯片及电子设备

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0338725A (ja) * 1989-07-05 1991-02-19 Mitsubishi Electric Corp データ処理装置及びマイクロプロセッサ
JPH0711793B2 (ja) * 1989-07-13 1995-02-08 株式会社東芝 マイクロプロセッサ
JP3144794B2 (ja) * 1990-11-09 2001-03-12 株式会社日立製作所 マルチプロセッサシステム
JPH087715B2 (ja) * 1990-11-15 1996-01-29 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理装置及びアクセス制御方法
US5191649A (en) * 1990-12-21 1993-03-02 Intel Corporation Multiprocessor computer system with data bus and ordered and out-of-order split data transactions
DE69320508T2 (de) * 1992-03-04 1999-03-04 Motorola Inc Verfahren und Gerät zur Busarbitrierungsdurchführung mit einem Arbiter in einem Datenverarbeitungssystem
JPH06231074A (ja) * 1993-01-29 1994-08-19 Nec Corp システムバスの多重アクセス方式
GB2285524B (en) * 1994-01-11 1998-02-04 Advanced Risc Mach Ltd Data memory and processor bus
JPH09306162A (ja) * 1996-05-09 1997-11-28 Minoru Furuta Dramの制御システム
JPH1097496A (ja) * 1996-09-20 1998-04-14 Sanyo Electric Co Ltd バス制御方法およびその方法を用いた装置
GB2334415A (en) * 1998-02-13 1999-08-18 Motorola Ltd Interfacing multiplexed and non- multiplexed busses
JPH11328102A (ja) * 1998-05-12 1999-11-30 Fujitsu Ltd バス制御システムおよびバス制御方法
JP2000047994A (ja) * 1998-07-27 2000-02-18 Fujitsu Ltd 情報処理装置
US6763448B1 (en) * 1999-02-16 2004-07-13 Renesas Technology Corp. Microcomputer and microcomputer system
US6708257B2 (en) * 1999-07-12 2004-03-16 Koninklijke Philips Electronics N.V. Buffering system bus for external-memory access
US6513094B1 (en) * 1999-08-23 2003-01-28 Advanced Micro Devices, Inc. ROM/DRAM data bus sharing with write buffer and read prefetch activity
KR100709888B1 (ko) * 2000-08-04 2007-04-20 엘지노텔 주식회사 웜 스탠바이 이중화 장치의 구현방법
US6684268B1 (en) * 2000-09-27 2004-01-27 Emc Corporation Data storage system having separate data transfer section and message network having CPU bus selector
US7209989B2 (en) * 2004-09-29 2007-04-24 Intel Corporation Transfer acknowledgement mechanism for an MSL architecture
FR2884629B1 (fr) * 2005-04-15 2007-06-22 Atmel Corp Dispositif d'amelioration de la bande passante pour des circuits munis de controleurs memoires multiples
US7444472B2 (en) * 2005-07-19 2008-10-28 Via Technologies, Inc. Apparatus and method for writing a sparsely populated cache line to memory

Also Published As

Publication number Publication date
CN101160569A (zh) 2008-04-09
FR2884629A1 (fr) 2006-10-20
FR2884629B1 (fr) 2007-06-22
US20090216926A1 (en) 2009-08-27
US20060236007A1 (en) 2006-10-19
US8468281B2 (en) 2013-06-18

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