US20060236007A1 - Apparatus to improve bandwidth for circuits having multiple memory controllers - Google Patents
Apparatus to improve bandwidth for circuits having multiple memory controllers Download PDFInfo
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- US20060236007A1 US20060236007A1 US11/183,052 US18305205A US2006236007A1 US 20060236007 A1 US20060236007 A1 US 20060236007A1 US 18305205 A US18305205 A US 18305205A US 2006236007 A1 US2006236007 A1 US 2006236007A1
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
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Abstract
An apparatus for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller, a second memory controller, a first busy read output signal circuit, a first busy write output signal circuit, a second busy read output signal circuit, and a second busy write output signal circuit. The first busy read output signal indicates when the first memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the first memory controller. The first busy write output signal indicates when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller. The second busy read output signal indicates when the second memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the second memory controller. The second busy write output signal indicates when the second memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the second memory controller.
Description
- The present invention relates to memory controllers. More specifically, the present invention relates to control circuits for multiple memory controllers.
- An integrated micro-controller device includes a microprocessor, on-chip memories, an interface with external memories including an external bus interface (EBI) used to run application software, a number of standard peripheral modules configured to communicate with the external devices such as an universal asynchronous receiver/transmitter (UART), a serial peripheral interface (SPI), a parallel I/O chip (PIO), or a universal serial bus (USB), and modules to generate interruptions like an interrupt controller, or a timer.
- The EBI generates signals required to drive external memories such as a static RAM (SRAM) memory controller; a flash memory controller; a burst flash memory controller; a synchronous dynamic RAM (SD-SDRAM) memory controller; a double date rate synchronous memory controller (DDR-SDRAM); a reduced latency dynamic RAM memory controller, an EEPROM, or a read only memory (ROM). Typically, these signals, like chip select signals, and/or control signals (read/write, enable, strobe) are transmitted using a control bus, an address bus, and/or a data bus. In some types of applications, a micro-controller utilizes an external bus interface (EBI). If this is the case, an EBI may drive several memory devices of different types, like SDRAM, SRAM, and flash, at the same time by generating the corresponding signals for each memory it targets.
- The EBI module is often connected on the internal system bus as a slave executing the actions required by the microprocessor which acts as a master in a simplified architecture. The master is able to read/write data from/into the internal memory (RAM) or external memories. Internal memories are often faster than external memory but smaller. Usually, a set of data that requires fast access time (such as interrupt handler software, or any set of data which size is small enough) resides at on-chip memories. When a master sets the internal address bus to a value targeting an on-chip memory (for example, a SRAM), the address decoder asserts the internal selection signal. The EBI is not selected in this case. On the other hand, a large set of data that can be processed at a slower access time, resides at the external memory. When the master starts an access to/from an external memory, the address decoder asserts the internal selection signal. The EBI modules translate the system bus waveforms protocol into the targeted memory waveform protocol.
- In this type of prior art architecture, when an external memory requires more than one system bus clock cycle to be accessed, the EBI asserts the “wait” signal to indicate the master that no other access is possible. As a result, the master postpones its next access whatever the destination of the new access is. For example, if the next access target is the external memory, it will postponed because of the wait state which has been asserted to prevent an access to the external bus.
- This architecture becomes especially burdensome when several masters are connected on a single system bus to a plurality of slave devices because all of the masters will be put in wait states. In another multiple system bus architecture, where there is a single master per system bus, the master, having initiated the transfer of data, will not be allowed to process any transfer of data to or from other slaves.
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FIG. 1 depicts a priorart system architecture 10 with a micro-controller 12 connected to different types of external memories, such as a static RAM (SRAM)memory 14 and a synchronous dynamic RAM (SDRAM) memory by utilizing an external bus interface (EBI) (not shown). If this is the case, the EBI may drive several memory devices of different types, likeSRAM 14 and SDRAM 16 by generating the corresponding signals for each memory it targets. - A common port mapping for the EBI includes a
single address bus 18, a bi-directional data bus and different control signals. The “chip selects” signals are unique for each memory device. For instance, thechipsel_sram signal 22 is used to select theSRAM memory device 14, whereas thechipsel_sdram signal 24 is utilized to select theSDRAM memory device 16. Each type of memory device requires other specific control signals, like a byte enable signal (not shown) forSRAM 14, and a bank addressing signal (not shown) forSDRAM 16. As it is well known to those skillful in the art, the data transfer cannot occur at the same time on more than one external memory device. Therefore, each control signal output of the micro-controller should have multiple functions to accommodate the needs of different memory devices. -
FIG. 2 illustrates a basic prior artmicro-controller architecture 40 in more details. The EBImodule 42 is often connected on the internal system bus (including aninternal address bus 46, aninternal data bus 50, an internalread data bus 48, and an internal write data bus 44) as a slave, that is EBI executes the actions required by themicroprocessor 52 which acts as a master in a simplified architecture. - In this master-slave model, the master (microprocessor 52) is able to read/write data from/into the internal memory, like ROM, or SRAM on-
chip memories 54, or to read/write data from/to the External memories (not shown). An internal memory is in most cases faster than an external memory, but has a lesser data capacity. Therefore, the data that requires a fast access time, such as an interrupt handler software, or any data which size is small enough, is targeted into on-chip memories. - When the master (microprocessor 52) sets the
internal address bus 46 to a value targeting an on-chip memory 54 (for example, the SRAM memory), theaddress decoder 56 asserts the internal “sel_intram”internal selection signal 58. The EBI 42 is not selected in this case. - On the other hand, a large set of data that accepts a slower access time can be stored in the external memory. If this is the case, when the master (microprocessor 52) starts an access to/from an external memory, the
address decoder 56 asserts the internal “sel_ebi”selection signal 60 via theEBI module 42 that translates the system bus waveforms protocol into the targeted external memory waveform protocol. When an external memory (not shown) requires more than one system bus clock cycle to be accessed, the EBI 42 asserts the “wait” signal (not shown) to indicate the master (microprocessor 52) that no other access to any kind of destination device is possible. If this is the case, the master (microprocessor 52) postpones its next access to any other device. - Thus, in this prior art system bus architecture where a single system bus is allocated for the master, the master that initiated the transfer to any type of device that requires more than one system bus clock cycle to be accessed will not be allowed to process any transfer to any other device until the first transfer is completed.
- This situation is exacerbated in the prior art multiple system bus architecture where several masters are connected via a single system bus to several slaves because all the masters will be put in wait states even if a single master has initiated the transfer to any type of device that requires more than one system bus clock cycle to be accessed.
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FIG. 3 illustrates aprior art architecture 70 wherein the EBI has several sub-modules, including aSRAM memory controller 72, and aSDRAM memory controller 74. The “Sel_ebi”signal 60 ofFIG. 2 includes a plurality of selection signals, whereas each memory controller is assigned its own selection signal. For instance, theSDRAM memory controller 74 is assigned the selection signal “sel_extsdram” 78, and theSRAM memory controller 72 is assigned the selection signal “sel_extsram” 76. Themultiplexers MUX1 80 andMUX2 82 are required to share theexternal address bus 84 and theexternal data bus 86. If the SRAM memory (not shown) is selected, the “external address bus” 84 is driven by theSRAM controller 72. Themultiplexer MUX3 88 allows theSRAM memory controller 72 and theSDRAM memory controller 74 to share the internalread data bus 90. - The generation of “wait”
signal 92 is performed at each memory controller level, taking into account the specific characteristics of the memory being driven and at the EBI level where it is necessary to collect all the memory controllers wait information and report a single signal. This is the function of 2_input ORgate 94. -
FIG. 4 depicts prior art waveforms for a system including a read access to an external memory requiring one wait state and requiring roughly one clock cycle to release the data bus after the external memory has been de-selected. - The time required to completely release the data bus after the external memory de-selection is called “time data float” (TDF). The EBI asserts the
wait signal 116 for threewait cycles 122, thoughD1 Data value 120 on the EBIdata bus 112 is available after only one wait cycle. This is done to prevent any other transfer on EBI until the EBIdata bus 112 is released, i.e. untiltime T2 126 on thesystem bus clock 102. The wait signal is asserted for thewait period 122 equal to the time data float period TDF. Therefore the next access to external memory cannot start beforeT2 126. According to the EBIaddress bus waveform 110 ofFIG. 4 , the next access starts at thetime T3 128, whereas T3=T1+4. - Thus, it takes a long time in the prior art to start the next access to the external memory following the initial read access.
- To address the shortcomings of the art, the present invention provides an apparatus for improving a bandwidth for circuits having multiple memory controllers by generating a plurality of busy signals that are configured to indicate when the next external access to the data bus is allowed, thus improving the data throughput.
- One aspect of the present invention is directed to an apparatus featuring a data bus, a memory controller, a first output signal circuit, and a second output signal circuit. The first output signal is configured to indicate when the memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the memory controller, whereas the second output signal is configured to indicate when the memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the memory controller.
- In one embodiment, the apparatus of the present invention employs a first input signal circuit and a second input signal circuit. The first input signal is configured to indicate when the data bus is released by an external memory controller for a read access by the memory controller, whereas the second input signal is configured to indicate when the external bus is released by the external memory controller for a write access by the memory controller. The memory controller delays all external accesses to the data bus subsequent to an initial write access to the data bus. The memory controller anticipates a next external access to the address bus subsequent to an initial read access to the data bus by performing a next access command using the address bus.
- Another aspect of the present invention is directed to an apparatus for improving bandwidth for circuits having a plurality of memory controllers. This architecture includes a first memory controller, a second memory controller, a first first_memory_controller _output signal circuit, a second first_memory_controller _output signal circuit, a first second_memory_controller _output signal circuit, and a second second_memory _controller_output signal circuit. In this embodiment, the first first_memory_controller_output signal is configured to indicate when the first memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the first memory controller.
- The second_first_memory_controller_output signal is configured to indicate when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller. The first second_memory _controller_output signal is configured to indicate when the second memory controller releases the address bus for an external access subsequent to a read access to the data bus by the second memory controller. The second second_memory_controller_output signal is configured to indicate when the second memory controller releases the data bus for an external access subsequent to a write access to the data bus by the second memory controller.
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FIG. 1 depicts a prior art system architecture with a micro-controller connected to external memories, like a Static RAM (SRAM) memory and a synchronized dynamic RAM (SDRAM) memory. -
FIG. 2 illustrates a basic prior art micro-controller architecture. -
FIG. 3 shows the prior art architecture of the external bus interface (EBI) having several sub-modules, including a SRAM memory controller, and a SDRAM memory controller. -
FIG. 4 illustrates prior art waveforms for a system including a read access to an external memory requiring one wait state and requiring roughly one clock cycle to release the data bus after the external memory has been de-selected. -
FIG. 5 depicts the apparatus of the present invention for improving bandwidth for circuits having a plurality of memory controllers and a plurality of busy signal circuits. -
FIG. 6 illustrates timing diagrams for the apparatus ofFIG. 5 having two clocks gain in throughput. -
FIG. 7 illustrates timing diagrams with a gain in throughput for the apparatus ofFIG. 5 when an external read access is followed by an external access. -
FIG. 8 illustrates timing diagrams with a gain in the throughput of the apparatus ofFIG. 5 when an external write access is followed by an external access. - With reference to
FIG. 5 , theEBI apparatus 140 of the present invention for improving bandwidth forcircuits 140 has a first (SRAM)memory controller 142 in parallel to a second (SDRAM )memory controller 144. A firstfirst_memory_controller_output signal circuit 146 asserts a busy_read_out sramcontroller output signal 8. A secondfirst_memory_controller_output signal circuit 148 asserts a busy_write_out sramcontroller output signal 7. A firstsecond_memory_controller_output signal circuit 156 asserts a busy_read_out sdramcontroller output signal 2. A second second_memory_controller _outputsignal circuit 154 asserts a busy_write_out sdramcontroller output signal 1. - A first
first_memory_controller_input signal circuit 150 receives abusy_read_in_sram signal 6. A secondfirst_memory_controller_input signal circuit 152 receives abusy_write_in_sram signal 5. A firstsecond_memory_controller_input signal circuit 160 receives abusy_read_in_sdram signal 4, and a secondsecond_memory_controller_input signal circuit 158 receives abusy_write_in_sdram signal 3. - The
first memory controller 142, as well as thesecond memory controller 144, can be selected from various memory controllers including a static RAM (SRAM) memory controller; a flash memory controller; a burst flash memory controller; a synchronous dynamic RAM (SDRAM) memory controller; a double date rate synchronous dynamic RAM controller; and a reduced latency dynamic RAM memory controller. - The
busy_read_in_sram signal 6 to indicates when theexternal data bus 162 is released for a read access by theSRAM memory controller 142. Thebusy_write_in_sram signal 5 indicates when theexternal data bus 162 is released for a write access by theSRAM memory controller 142. Thebusy_read_in_sdram signal 4 indicates when theexternal address bus 166 is released for a read access by theSDRAM memory controller 144. Thebusy_write_in_sdram signal 3 indicates when theexternal data bus 162 is released for a write access by theSDRAM memory controller 144. - Referring still to
FIG. 5 , the busy_read_in _sramsignal 6 and thebusy_write_in_sram signal 5 are internally combined with theselection signal sel_extsram 168 to allow theSRAM controller 142 access to theexternal bus 162. Similarly, thebusy_read_in_sdram signal 4 and thebusy_write_in_sdram signal 3 are internally combined with theselection signal sel_extsdram 170 to allow theSDRAM controller 144 access to theexternal bus 162. - Referring still to
FIG. 5 , the busy_read_out sramcontroller output signal 8 indicates when theSRAM memory controller 142 releases theexternal address bus 166 for a next external access subsequent to a read access to the data bus by theSRAM memory controller 142. The busy_write_out sramcontroller output signal 7 indicates when theSRAM memory controller 142 releases theexternal data bus 162 for a next external access subsequent to a write access to the data bus by the SRAM memory controller. The busy_read_out sdramcontroller output signal 2 indicates when theSDRAM memory controller 144 releases theexternal address bus 166 for an external access subsequent to a read access to the data bus by the SDRAM memory controller. The busy_write_out sdramcontroller output signal 1 is configured to indicate when theSDRAM memory controller 144 releases theexternal data bus 162 for an external access subsequent to a write access to the data bus by the SDRAM memory controller. - The “busy_read_out/busy_write_out” signals are asserted when some conditions are met. The timing condition to assert a “busy_read_out” signal is the time where a read access on an external memory ends (time data float also known as TDF). During this period the “busy_read_out” signal is asserted to indicate the memory controller 142 (or 144) which drives the next access to the
address bus 166 that certain command (active or precharge command) can be performed because theexternal address bus 166 is not busy. The memory controller 142 (or 144) anticipates the next access to the address bus, but it will not perform the read command as long as “busy_read_out” signal is asserted because the residual data can be present on the EBI data bus. During a read access (whatever the next access is), thewait signal 172 is asserted to indicate the master (microprocessor, or direct memory access controller) (not shown) that the data is not ready. No other access can be anticipated in this situation. - On the other hand, the condition to assert the “busy_write_out” signal is a write access to the
data bus 162 by the memory controller 142 (or 144) where thedata bus 162 is driven by the microcontroller (not shown). The memory (for instance, SRAM, or SDRAM) may require several clock cycles so that the data could be correctly written. - Memory controller 142 (or 144) includes a store element (not shown) to hold the data until the write transfer is completed. If this is the case, there is no need to assert the “wait” signal. Instead, the master (microcontroller) should be informed that the current write access to the data bus needs several clock cycles to be completed. This is done by asserting the “busy_write_out” signal to prevent any other access on EBI. In this case it's not possible to anticipate a next access to the data bus 162 (whatever the next access is) because the
external address bus 166 is busy by the write access. Therefore, theapparatus 140 of the present invention optimizes the EBI architecture efficiency for multiple memory type. Indeed, for a given clock frequency, an application software will run faster with the invention rather than without invention. The efficiency of the EBI architecture for multiple memory type of the present invention is illustrated in the discussion below. - Referring still to
FIG. 5 , the output circuits including the firstfirst_memory_controller_output signal circuit 146, the secondfirst_memory_controller_output signal circuit 148, the first second_memory_controller _outputsignal circuit 156, and the second second_memory _controller_outputsignal circuit 154 are all electrically communicating with the input circuits including the firstfirst_memory_controller_input signal circuit 150, the secondfirst_memory_controller_input signal circuit 152, the first second_memory_controller _inputsignal circuit 160, and the second second_memory _controller_inputsignal circuit 158. - The “busy_write_out”
signal 7 ofmemory controller 142 drives the “busy_write_in”signal 3 ofmemory controller 144. In another embodiment of the present invention, the “busy_write_out”output signal 1 ofmemory controller 144 drives the “busy_write_in”signal 5 ofmemory controller 142. In one more embodiment of the present invention, the “busy_read_out”signal 8 ofmemory controller 142 drives the “busy_read_in”signal 4 ofmemory controller 144. In one additional embodiment of the present invention, the “busy_read_out”output signal 2 ofmemory controller 144 drives the “busy_read_in”signal 6 ofmemory controller 142. -
FIG. 6 illustrates a signal output drawing for the apparatus ofFIG. 5 that has dual clock gain in throughput as compared with the throughput of the prior art apparatus ofFIG. 4 , when an external read access is followed by an external access, whereas the memory requires only one clock cycle of TDF. More specifically, the readtransfer command 220 sent by the master on theinternal system bus 205 starts the read transfer to an external memory followed by the external memory transfer to an another device access to the external bus. A read access is required on EBI (theread value D1 228 at the address location A1 224). The wait signal 226 from memory controller is asserted during the first clock period T1 228 (on a system bus clock 202), and de-asserted afterwards. Indeed, the master starts the newwrite access D2 230 ataddress location A2 232 which corresponds to the external memory without wait signals. Instead, the memory controller samples the internal address bus value A2 229 into internal storage elements and holds this value on the external address bus until the memory has completed the read of data bus (value D1 228) attime T3 240. This time is exactly the same as the time T3 ofFIG. 4 . What is different is the time when the next access can start, for instance thewrite access D2 230 ataddress location A2 232. Due to the absence of a wait signal and presence ofbusy read signal 216, the master can initiate the next transfer command using the control bus and the address bus then can perform the next transfer command to an external device attime T3 240 which is equal to (T1+2) clock cycles. On the other hand, in the prior art embodiment as depicted inFIG. 4 , the time to start the new transfer command is T3=(T1+4) clock cycles. The gain is 2 clock cycles. The gain is higher if the wait signal used in the prior art apparatus to complete a single read is longer than 3 clock cycles. -
FIG. 7 illustrates further signal output drawings for the apparatus ofFIG. 5 . In this example, the memory requires more than 2 clock cycles ofTDF 252, whereas in the example shown inFIG. 6 the memory requires only one clock cycle ofTDF 242. The time of data floating (TDF) is not part of thewait time 254. The gain is 2 clock cycle for the given example The gain is higher if the external memory requires more cycles to release the data bus after being de-selected. More specifically, on the first access the “wait”signal 254 is asserted to prevent the master from reading the data prematurely atcycle T2 256 after thefirst cycle T1 258. On thesecond cycle T2 256 the “wait”signal 254 is released to inform master that the data is ready on the internal bus. There is a direct throughput from external data bus to internal data bus. On the same T2 cycle the “busy_read”signal 260 is asserted to prevent a new access on the EBI to avoid data contention on the external data bus. If the next cycle is an external cycle, several commands can be sent during the time period when thebusy_read signal 260 is asserted. This allows to use bus address. TheA2 address 264 is processed and corresponding data (D2) 266 is set on the external data bus when busy_read is de-asserted to avoid contention on the bus, and when all additional conditions are met (for example, the asynchronous timing of SDRAM). If the next cycles are the internal accesses, like the internal accesses toA3 268, toA4 270, and toA5 272 addresses which do not use the external data bus, the risk of data contention is low and the transfer is not blocked. -
FIG. 8 illustrates further signal output drawings of the apparatus ofFIG. 5 . The memory may require several clock cycles to be correctly written, for instance two clock periods. If the memory controller includes a store element to hold the data until the write transfer is completed, there is no need to assert thewait signal 284. Instead, there is a need to inform the system (master) that the current write access needs several clock cycles to be completed. This is done by asserting abusy_write signal 282 to prevent any other access on EBI. If this is the case, it is not possible to anticipate the next access, no matter what the next access is, because the external address bus is busy by the write access. In this embodiment, the gain is dependent on the number of clock cycles required for a write command to be completed. - Referring still to
FIG. 5 , the following output circuits: the firstfirst_memory_controller_output signal circuit 146, the secondfirst_memory_controller_output signal circuit 148, the first second_memory_controller _outputsignal circuit 156, and the secondsecond_memory_controller_output signal circuit 154 are all electrically disconnected from the following input circuits: the firstfirst_memory_controller_input signal circuit 150, the secondfirst_memory_controller_input signal circuit 152, the first second_memory_controller _inputsignal circuit 160, and the second second_memory _controller_inputsignal circuit 158. In this embodiment, the simplified architecture features adata bus 162, asingle memory controller 142, a firstoutput signal circuit 146, a secondoutput signal circuit 148, a firstinput signal circuit 150, and a secondinput signal circuit 152. Thefirst output signal 8 indicates when thememory controller 142 releases theaddress bus 166 for a next external access subsequent to a read access to the data bus by thememory controller 142, whereas thesecond output signal 7 indicates when thememory controller 142 releases thedata bus 162 for a next external access subsequent to a write access to thedata bus 162 by thememory controller 142. Thefirst input signal 6 indicates when theaddress bus 166 is released by an external memory controller for a read access by thememory controller 142, whereas thesecond input signal 5 indicates when the external bus is released by the external memory controller for a write access by thememory controller 142. - The method for improving bandwidth for circuits having a plurality of memory controllers employs the following steps: (A) asserting a first first_memory _controller_output signal to indicate when a first memory controller releases an address bus for a next external access subsequent to a read access to the data bus by the first memory controller; (B) asserting a second first_memory_controller_output signal to indicate when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller; (C) asserting a first second_memory_controller_output signal to indicate when a second memory controller releases the address bus for an external access subsequent to a read access to the data bus by the second memory controller; and
- (D) asserting a second second_memory_controller_output signal to indicate when the second memory controller releases the data bus for an external access subsequent to a write access to the data bus by the second memory controller.
- In one embodiment of the present invention, the step (A) of asserting the first first_memory_controller _output signal further includes the step of: (A1) asserting a first_busy_read_out signal by using the address bus to anticipate a next external access to the data bus subsequent to an initial read access to the external data bus by the first memory controller.
- The step (B) of asserting the second first_memory_controller_output signal further includes the step of: (B1) asserting a first_busy_write_out signal to delay all external accesses to the external data bus subsequent to an initial write access to the external data bus by the first memory controller. The step (C) of asserting the first second_memory_controller_output signal further includes the step of: (C1) asserting a second_busy_read_out signal by using the address bus to anticipate a next external access to the data bus subsequent to an initial read access to the external data bus by the second memory controller. The step (D) of asserting the second second_memory_controller_output signal further includes the step of: (D1) asserting a second_busy_write_out signal to delay all external accesses to the external data bus subsequent to an initial write access to the external data bus by the second memory controller.
- Further steps can include the following: (E) asserting a first first_memory_controller_input signal to indicate when the external address bus is released for a read access by the first memory controller; (F) asserting a second first_memory_controller_input signal to indicate when the external data bus is released for a write access by the first memory controller; (G) asserting a first second_memory_controller_input signal to indicate when the external address bus is released for a read access by the second memory controller; and (H) asserting a second second_memory_controller_input signal to indicate when the external data bus is released for a write access by the second memory controller.
Claims (26)
1. A system comprising:
an address bus and a data bus, a memory controller electrically communicating with said address bus and said data bus;
a first output signal circuit electronically communication with the memory controller wherein said first output circuit has means for signaling when the memory controller releases the address bus; and
a second output signal circuit electrically communicating with the memory controller wherein said second output signal circuit has means for signaling when the memory controller releases the data bus.
2. The apparatus of claim 1 further comprising:
a first input signal circuit electrically communicating with said memory controller, wherein said first input signal circuit has means for signaling when said address bus is released by an external memory controller for an access by said memory controller; and
a second input circuit electrically communicating with the said memory controller, wherein said second input signal circuit has mean for signaling when said data bus is released by said external memory controller for a access by said memory controller.
3. The apparatus of claim 2 wherein said memory controller has means for delaying all external accesses to said data bus subsequent to an initial access to said data bus by using the second input signal.
4. The apparatus of claim 2 wherein said memory controller further comprising means for anticipating a next external access by using to said address bus subsequent to an initial access to said data bus by using the first input signal.
5. A system for improving bandwidth among a plurality of memory controllers, said system comprising:
a first memory controller electrically communicating with an external data and address bus for controlling a first memory circuit;
a second memory controller electrically communicating with an external data and address bus for controlling a second memory circuit;
a first output signal circuit electrically communicating with the first memory controller, wherein said first output signal has means for signaling when the said first memory controller releases said address bus for a next external access subsequent to an access to said data bus by said first memory controller;
a second output signal circuit electrically communicating with the first memory controller, wherein said second output has mean for signaling when the said first memory controller releases said data bus for a next external subsequent to an access to said data bus by said first memory controller;
a first output signal circuit electrically communicating with the second memory controller, wherein said first output signal has means for signaling when the said second memory controller releases said address bus for a next external access subsequent to an access to said data bus by said second memory controller; and
a second output signal circuit electrically communicating with the second memory controller, wherein said second output has means for signaling when the said second memory controller releases said data bus for a next external access subsequent to an access to said data bus by said second memory controller.
6. The apparatus of claim 5 further comprising:
a first input signal circuit electrically communicating with the said first memory controller, wherein said first input signal has means for signaling when said external address bus is released for a next access by said first memory controller;
a second input signal circuit electrically communicating with the said first memory controller, wherein said second input signal has means for signaling when said external data bus is released for a next access by said first memory controller;
a first input signal circuit electrically communicating with the said second memory controller, wherein said first input signal has means for signaling when said external address bus is released for a next access by said second memory controller; and
a second input signal circuit electrically communicating with the said second memory controller, wherein said second input signal has means for signaling when said external data bus is released for a next access by said second memory controller.
7. The apparatus of claim 5 wherein said first memory controller further comprising:
a memory controller selected from the group consisting of: a static ram memory controller, a flash memory controller, a burst flash memory controller, a single data rate synchronous dynamic random access memory (SDR SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a pseudo-static random access memory (PSRAM), a CellularRam, and a reduced latency dynamic random access memory (RLDRAM).
8. The apparatus of claim 5 wherein said second memory controller further comprising:
a memory controller selected from the group consisting of: a static ram memory controller, a flash memory controller, a burst flash memory controller, a single data rate synchronous dynamic random access memory (SDR SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a pseudo-static random access memory (PSRAM), a CellularRam, and a reduced latency dynamic random access memory (RLDRAM).
9. The apparatus of claim 5 wherein said first memory controller has means for signaling that the external data bus is released for external access to said external bus subsequent to an initial write by asserting a busy_write_out signal.
10. The apparatus of claim 9 wherein said first memory controller further includes a store element means for holding a set of data including a first integer number of clock cycles, wherein a write transfer from said external data bus is completed within said busy_write_out signal is asserted to indicate that said current write access to said external data bus needs said first integer number of clock cycles to be completed.
11. The apparatus of claim 5 wherein said second memory controller has means for signaling that the external data bus is released for external access to said external bus subsequent to an initial write by asserting a busy_write_out signal.
12. The apparatus of claim 9 wherein said second memory controller further includes a store element means for holding a set of data including a first integer number of clock cycles, wherein a write transfer from said external data bus is completed within said busy_write_out signal is asserted to indicate that said current write access to said external data bus needs said first integer number of clock cycles to be completed.
13. The apparatus of claim 5 wherein said first memory controller has means for signaling that the address bus is released to anticipate a next external access to said data bus subsequent to an initial read access to said external data by said first memory controller by asserting a busy_read_out signal.
14. The apparatus of claim 13 wherein said first memory controller has mean for asserting said busy_read_out signal during the time period when a set of data floats (TDF) at said data bus.
15. The apparatus of claim 5 wherein said second memory controller has means for signaling that the address bus is released to anticipate a next external access to said data bus subsequent to an initial read access to said external data bus by said second memory controller by asserting a busy_read_out signal.
16. The apparatus of claim 15 wherein said second memory controller has means for asserting said busy_read_out signal during the time period when a set of data floats (TDF) at said data bus.
17. The apparatus of claim 6 wherein said first memory controller is electrically communicating with said second memory controller, and wherein said first memory controller's busy_write_out signal drives second memory controller's busy_write_in signal.
18. The apparatus of claim 6 wherein said first memory controller is electrically communicating with said second memory controller, and wherein said second memory controller's busy_write_out signal drives first memory controller's busy_write_in signal.
19. The apparatus of claim 6 wherein said first memory controller is electrically communicating with said second memory controller, and wherein said first memory controller's busy_read_out signal drives second memory controller's busy_read_in signal.
20. The apparatus of claim 6 wherein said first memory controller is electrically communicating with said second memory controller, and wherein said second memory controller's busy_read_out signal drives first memory controller's busy_read_in signal.
21. The method of improving bandwidth for circuits having a plurality of memory controllers, said method comprising the steps of:
a) asserting a first output signal to indicate when a first memory controller releases an address bus for a next external access subsequent to an access to said data bus by said first memory controller;
b) asserting a second output signal to indicate when said first memory controller releases an said data bus for a next external access subsequent to an access to said data bus by said first memory controller;
c) asserting a first output signal to indicate when a second memory controller releases said address bus for a next external access subsequent to an access to said data bus by said second memory controller; and
d) asserting a second output signal to indicate when said second memory controller releases an said data bus for a next external access subsequent to an access to said data bus by said second memory controller.
22. The method of claim 21 further comprising the steps of:
e) asserting a first input signal to indicate when said external address bus is released for an access by said first memory controller;
f) asserting a second input signal to indicate when said external data bus is released for an access by said controller;
g) asserting a first input signal to indicate when said external address bus is released for an access by said second memory controller; and
h) asserting a second input signal to indicate when said external data bus is released for an access by said first memory controller.
23. The method of claim 21 wherein said step a) of asserting said first output signal further includes the step of:
a) asserting a signal indicating said address bus is released to anticipate a next external access to said data bus subsequent an initial access to said external data bus by said first memory controller.
24. The method of claim 21 wherein said step b) of asserting said second output signal further includes the step of:
b) asserting a signal to indicate delay all external accesses to said external data bus subsequent to an initial access to said external data bus said first memory controller are not allowed.
25. The method of claim 21 wherein said step c) of asserting said first output signal further includes the step of:
c) asserting a signal indicating said address bus is released to anticipate a next external access to said data bus subsequent an initial access to said external data bus by said second memory controller.
26. The method of claim 21 wherein said step d) of asserting said second output signal further includes the step of:
d) asserting a signal to indicate delay all external accesses to said external data bus subsequent to an initial access to said external data bus said second memory controller are not allowed.
Priority Applications (5)
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PCT/US2006/008447 WO2006112968A1 (en) | 2005-04-15 | 2006-03-08 | Apparatus to improve bandwidth for circuits having multiple memory controllers |
DE112006000758T DE112006000758T5 (en) | 2005-04-15 | 2006-03-08 | Device for improving the bandwidth for circuits with a plurality of memory control units |
GB0721911A GB2441668A (en) | 2005-04-15 | 2006-03-08 | Apparatus to improve bandwidth for circuits having multiple memory controllers |
TW095112623A TW200643724A (en) | 2005-04-15 | 2006-04-10 | System for improving bandwidth among a plurality of memory controllers and method thereof |
US12/433,859 US8468281B2 (en) | 2005-04-15 | 2009-04-30 | Apparatus to improve bandwidth for circuits having multiple memory controllers |
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FR05/03811 | 2005-04-15 | ||
FR0503811A FR2884629B1 (en) | 2005-04-15 | 2005-04-15 | DEVICE FOR ENHANCING BANDWIDTH FOR CIRCUITS WITH MULTIPLE MEMORY CONTROLLERS |
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Also Published As
Publication number | Publication date |
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FR2884629B1 (en) | 2007-06-22 |
US20090216926A1 (en) | 2009-08-27 |
CN101160569A (en) | 2008-04-09 |
TW200643724A (en) | 2006-12-16 |
US8468281B2 (en) | 2013-06-18 |
FR2884629A1 (en) | 2006-10-20 |
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