GB2441668A - Apparatus to improve bandwidth for circuits having multiple memory controllers - Google Patents
Apparatus to improve bandwidth for circuits having multiple memory controllers Download PDFInfo
- Publication number
- GB2441668A GB2441668A GB0721911A GB0721911A GB2441668A GB 2441668 A GB2441668 A GB 2441668A GB 0721911 A GB0721911 A GB 0721911A GB 0721911 A GB0721911 A GB 0721911A GB 2441668 A GB2441668 A GB 2441668A
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory controller
- output signal
- busy
- data bus
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
Abstract
An apparatus (140) for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller (142), a second memory controller (144), a first busy read output signal circuit (146), a first busy write output signal circuit (148), a second busy read output signal circuit (156), and a second busy write output signal circuit (154). The first busy read output signal (8) indicates when the first memory controller (142) releases the address bus (166) for a next external access subsequent to a read access to the data bus by the first memory controller (142). The first busy write output signal (7) indicates when the first memory controller (142) releases the data bus (162) for a next external access subsequent to a write access to the data bus by the first memory controller (142). The second busy read output signal indicates when the second memory controller (144) releases the address bus (166) for a next external access subsequent to a read access to the data bus by the second memory controller (144). The second busy write output signal (1) indicates when the second memory controller (144) releases the data bus (162) for a next external access subsequent to a write access to the data bus by the second memory controller (144).
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0503811A FR2884629B1 (en) | 2005-04-15 | 2005-04-15 | DEVICE FOR ENHANCING BANDWIDTH FOR CIRCUITS WITH MULTIPLE MEMORY CONTROLLERS |
| US11/183,052 US20060236007A1 (en) | 2005-04-15 | 2005-07-15 | Apparatus to improve bandwidth for circuits having multiple memory controllers |
| PCT/US2006/008447 WO2006112968A1 (en) | 2005-04-15 | 2006-03-08 | Apparatus to improve bandwidth for circuits having multiple memory controllers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB0721911D0 GB0721911D0 (en) | 2007-12-19 |
| GB2441668A true GB2441668A (en) | 2008-03-12 |
Family
ID=37115454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0721911A Withdrawn GB2441668A (en) | 2005-04-15 | 2006-03-08 | Apparatus to improve bandwidth for circuits having multiple memory controllers |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE112006000758T5 (en) |
| GB (1) | GB2441668A (en) |
| WO (1) | WO2006112968A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114667509B (en) * | 2020-02-13 | 2024-08-09 | 华为技术有限公司 | Memory, network equipment and data access method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5893158A (en) * | 1996-05-09 | 1999-04-06 | Furuta; Minoru | Multibank dram system controlled by multiple dram controllers with an active bank detector |
| US20010052060A1 (en) * | 1999-07-12 | 2001-12-13 | Liewei Bao | Buffering system bus for external-memory access |
-
2006
- 2006-03-08 DE DE112006000758T patent/DE112006000758T5/en not_active Withdrawn
- 2006-03-08 GB GB0721911A patent/GB2441668A/en not_active Withdrawn
- 2006-03-08 WO PCT/US2006/008447 patent/WO2006112968A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5893158A (en) * | 1996-05-09 | 1999-04-06 | Furuta; Minoru | Multibank dram system controlled by multiple dram controllers with an active bank detector |
| US20010052060A1 (en) * | 1999-07-12 | 2001-12-13 | Liewei Bao | Buffering system bus for external-memory access |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0721911D0 (en) | 2007-12-19 |
| WO2006112968A1 (en) | 2006-10-26 |
| DE112006000758T5 (en) | 2008-02-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |