TW200627651A - IC chip package structure and underfill process - Google Patents
IC chip package structure and underfill processInfo
- Publication number
- TW200627651A TW200627651A TW094120646A TW94120646A TW200627651A TW 200627651 A TW200627651 A TW 200627651A TW 094120646 A TW094120646 A TW 094120646A TW 94120646 A TW94120646 A TW 94120646A TW 200627651 A TW200627651 A TW 200627651A
- Authority
- TW
- Taiwan
- Prior art keywords
- flip chip
- package structure
- carrier substrate
- adhesive material
- underfill process
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 4
- 239000000853 adhesive Substances 0.000 abstract 4
- 230000001070 adhesive effect Effects 0.000 abstract 4
- 239000000463 material Substances 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 239000012812 sealant material Substances 0.000 abstract 2
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01006—Carbon [C]
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- H01L2924/01019—Potassium [K]
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- H01L2924/01033—Arsenic [As]
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- H01L2924/0105—Tin [Sn]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/043,602 US7148560B2 (en) | 2005-01-25 | 2005-01-25 | IC chip package structure and underfill process |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200627651A true TW200627651A (en) | 2006-08-01 |
TWI283076B TWI283076B (en) | 2007-06-21 |
Family
ID=36695941
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094120646A TWI283076B (en) | 2005-01-25 | 2005-06-21 | IC chip package structure and underfill process |
Country Status (3)
Country | Link |
---|---|
US (1) | US7148560B2 (zh) |
CN (1) | CN100373597C (zh) |
TW (1) | TWI283076B (zh) |
Cited By (1)
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TWI703648B (zh) * | 2019-06-25 | 2020-09-01 | 力成科技股份有限公司 | 半導體封裝結構之底膠填充方法及其底膠填充設備 |
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TWI301657B (en) * | 2006-01-27 | 2008-10-01 | Siliconware Precision Industries Co Ltd | Flip-chip semiconductor device and method for fabricating the same |
US7256503B2 (en) * | 2006-02-27 | 2007-08-14 | International Business Machines Corporation | Chip underfill in flip-chip technologies |
TW200741959A (en) * | 2006-04-20 | 2007-11-01 | Min-Chang Dong | A die and method fabricating the same |
JP5085081B2 (ja) * | 2006-09-22 | 2012-11-28 | パナソニック株式会社 | 電子部品実装構造体 |
US8110933B2 (en) * | 2006-12-26 | 2012-02-07 | Panasonic Corporation | Semiconductor device mounted structure and semiconductor device mounted method |
JP4438006B2 (ja) * | 2007-03-30 | 2010-03-24 | Okiセミコンダクタ株式会社 | 半導体装置及び半導体装置の製造方法 |
FR2919426B1 (fr) * | 2007-07-23 | 2009-12-11 | Commissariat Energie Atomique | Procede d'enrobage de deux elements hybrides entre eux au moyen d'un materiau de brasure |
US7834442B2 (en) * | 2007-12-12 | 2010-11-16 | International Business Machines Corporation | Electronic package method and structure with cure-melt hierarchy |
US8633586B2 (en) * | 2008-03-26 | 2014-01-21 | Stats Chippac Ltd. | Mock bump system for flip chip integrated circuits |
US8624402B2 (en) * | 2008-03-26 | 2014-01-07 | Stats Chippac Ltd | Mock bump system for flip chip integrated circuits |
JP5388673B2 (ja) * | 2008-05-07 | 2014-01-15 | パナソニック株式会社 | 電子部品 |
JP4533951B2 (ja) * | 2008-11-28 | 2010-09-01 | 株式会社東芝 | 電子機器、プリント回路基板および電子部品 |
US8039938B2 (en) * | 2009-05-22 | 2011-10-18 | Palo Alto Research Center Incorporated | Airgap micro-spring interconnect with bonded underfill seal |
JP5418367B2 (ja) * | 2010-03-30 | 2014-02-19 | 富士通株式会社 | プリント配線板ユニットおよび電子機器 |
US9064881B2 (en) * | 2010-11-11 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protecting flip-chip package using pre-applied fillet |
US8877567B2 (en) * | 2010-11-18 | 2014-11-04 | Stats Chippac, Ltd. | Semiconductor device and method of forming uniform height insulating layer over interposer frame as standoff for semiconductor die |
US8546957B2 (en) | 2010-12-09 | 2013-10-01 | Stats Chippac Ltd. | Integrated circuit packaging system with dielectric support and method of manufacture thereof |
TWI424552B (zh) | 2010-12-31 | 2014-01-21 | Ind Tech Res Inst | 三維立體堆疊晶片封裝結構 |
US8810025B2 (en) | 2011-03-17 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reinforcement structure for flip-chip packaging |
KR101237668B1 (ko) * | 2011-08-10 | 2013-02-26 | 삼성전기주식회사 | 반도체 패키지 기판 |
KR101333398B1 (ko) * | 2012-02-14 | 2013-11-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
TWI480989B (zh) | 2012-10-02 | 2015-04-11 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US9312193B2 (en) * | 2012-11-09 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress relief structures in package assemblies |
KR102065648B1 (ko) | 2013-08-14 | 2020-01-13 | 삼성전자주식회사 | 반도체 패키지 |
US9596756B2 (en) | 2013-09-06 | 2017-03-14 | Apple Inc. | Electronic device with printed circuit board noise reduction using elastomeric damming and damping structures |
US9373559B2 (en) | 2014-03-05 | 2016-06-21 | International Business Machines Corporation | Low-stress dual underfill packaging |
KR20150136393A (ko) | 2014-05-27 | 2015-12-07 | 에스케이하이닉스 주식회사 | 칩 고정 구조물을 갖는 플립칩 패키지 |
US10823355B2 (en) * | 2016-01-27 | 2020-11-03 | Lite-On Electronics (Guangzhou) Limited | Light-emitting module for vehicle lamp |
US9809446B1 (en) * | 2016-05-09 | 2017-11-07 | Amkor Technology, Inc. | Semiconductor package and manufacturing method thereof |
US10249573B2 (en) | 2017-03-16 | 2019-04-02 | Powertech Technology Inc. | Semiconductor device package with a stress relax pattern |
US10957672B2 (en) * | 2017-11-13 | 2021-03-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of manufacturing the same |
JP7236807B2 (ja) * | 2018-01-25 | 2023-03-10 | 浜松ホトニクス株式会社 | 半導体装置、及び半導体装置の製造方法 |
US11217460B2 (en) | 2018-05-09 | 2022-01-04 | Texas Instruments Incorporated | Multiple underfills for flip chip packages |
US10867955B2 (en) * | 2018-09-27 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure having adhesive layer surrounded dam structure |
US11062968B2 (en) | 2019-08-22 | 2021-07-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method for forming the same |
FR3109466B1 (fr) * | 2020-04-16 | 2024-05-17 | St Microelectronics Grenoble 2 | Dispositif de support d’une puce électronique et procédé de fabrication correspondant |
CN111800718A (zh) * | 2020-06-30 | 2020-10-20 | 荣成歌尔电子科技有限公司 | 车用麦克风及其制作工艺 |
US11404379B2 (en) | 2020-11-17 | 2022-08-02 | International Business Machines Corporation | Structure and method for bridge chip assembly with capillary underfill |
US11688657B2 (en) | 2021-02-10 | 2023-06-27 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
CN113130331B (zh) * | 2021-03-23 | 2024-07-30 | 浙江臻镭科技股份有限公司 | 贴装芯片结构及其制备方法 |
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US6459144B1 (en) * | 2001-03-02 | 2002-10-01 | Siliconware Precision Industries Co., Ltd. | Flip chip semiconductor package |
TW540123B (en) * | 2002-06-14 | 2003-07-01 | Siliconware Precision Industries Co Ltd | Flip-chip semiconductor package with lead frame as chip carrier |
US6774497B1 (en) * | 2003-03-28 | 2004-08-10 | Freescale Semiconductor, Inc. | Flip-chip assembly with thin underfill and thick solder mask |
US6933173B2 (en) * | 2003-05-30 | 2005-08-23 | Texas Instruments Incorporated | Method and system for flip chip packaging |
-
2005
- 2005-01-25 US US11/043,602 patent/US7148560B2/en active Active
- 2005-06-21 TW TW094120646A patent/TWI283076B/zh active
- 2005-07-12 CN CNB2005100830056A patent/CN100373597C/zh active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI703648B (zh) * | 2019-06-25 | 2020-09-01 | 力成科技股份有限公司 | 半導體封裝結構之底膠填充方法及其底膠填充設備 |
Also Published As
Publication number | Publication date |
---|---|
CN1812077A (zh) | 2006-08-02 |
CN100373597C (zh) | 2008-03-05 |
US20060163749A1 (en) | 2006-07-27 |
TWI283076B (en) | 2007-06-21 |
US7148560B2 (en) | 2006-12-12 |
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