TW200709373A - Flip-chip-on-film package structure capable of preventing sealing material from overflowing - Google Patents
Flip-chip-on-film package structure capable of preventing sealing material from overflowingInfo
- Publication number
- TW200709373A TW200709373A TW094128291A TW94128291A TW200709373A TW 200709373 A TW200709373 A TW 200709373A TW 094128291 A TW094128291 A TW 094128291A TW 94128291 A TW94128291 A TW 94128291A TW 200709373 A TW200709373 A TW 200709373A
- Authority
- TW
- Taiwan
- Prior art keywords
- sealing material
- flip
- chip
- overflowing
- package structure
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
The invention discloses a flip-chip-on-film package structure including a substrate, a flip chip, a plurality of bumps, a first sealing material, and a barricade. The substrate has an upper surface and a plurality of leads formed on the upper surface. The flip chip has an active surface and a plurality of pads formed on the active surface, wherein each of the pads is corresponding to one of the leads, respectively. Each of the bumps is used for connecting one of the pads and the corresponding lead. The first sealing material is coated to cover around the flip chip. The barricade is formed on the upper surface of the substrate and surrounds the flip chip. The barricade is used for preventing the first sealing material from overflowing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW094128291A TW200709373A (en) | 2005-08-19 | 2005-08-19 | Flip-chip-on-film package structure capable of preventing sealing material from overflowing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW094128291A TW200709373A (en) | 2005-08-19 | 2005-08-19 | Flip-chip-on-film package structure capable of preventing sealing material from overflowing |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200709373A true TW200709373A (en) | 2007-03-01 |
Family
ID=57911049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094128291A TW200709373A (en) | 2005-08-19 | 2005-08-19 | Flip-chip-on-film package structure capable of preventing sealing material from overflowing |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW200709373A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8003442B2 (en) | 2007-03-19 | 2011-08-23 | Yu-Lin Yen | Integrated cirucit package and method for fabrication thereof |
CN104795363A (en) * | 2014-01-17 | 2015-07-22 | 菱生精密工业股份有限公司 | Copper-clad substrate with barrier structure and manufacturing method thereof |
-
2005
- 2005-08-19 TW TW094128291A patent/TW200709373A/en unknown
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8003442B2 (en) | 2007-03-19 | 2011-08-23 | Yu-Lin Yen | Integrated cirucit package and method for fabrication thereof |
US8624383B2 (en) | 2007-03-19 | 2014-01-07 | Yu-Lin Yen | Integrated circuit package and method for fabrication thereof |
CN104795363A (en) * | 2014-01-17 | 2015-07-22 | 菱生精密工业股份有限公司 | Copper-clad substrate with barrier structure and manufacturing method thereof |
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