TW200624842A - Structure and method for failure analysis in a semiconductor device - Google Patents
Structure and method for failure analysis in a semiconductor deviceInfo
- Publication number
- TW200624842A TW200624842A TW094142743A TW94142743A TW200624842A TW 200624842 A TW200624842 A TW 200624842A TW 094142743 A TW094142743 A TW 094142743A TW 94142743 A TW94142743 A TW 94142743A TW 200624842 A TW200624842 A TW 200624842A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- failure analysis
- semiconductor
- analytic fields
- semiconductor transistors
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040102543A KR100748552B1 (ko) | 2004-12-07 | 2004-12-07 | 반도체 장치의 불량 분석을 위한 분석 구조체 및 이를이용한 불량 분석 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200624842A true TW200624842A (en) | 2006-07-16 |
TWI275815B TWI275815B (en) | 2007-03-11 |
Family
ID=36573173
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094142743A TWI275815B (en) | 2004-12-07 | 2005-12-05 | Structure and method for failure analysis in a semiconductor device |
Country Status (5)
Country | Link |
---|---|
US (1) | US7468530B2 (zh) |
JP (1) | JP5258161B2 (zh) |
KR (1) | KR100748552B1 (zh) |
CN (1) | CN100557797C (zh) |
TW (1) | TWI275815B (zh) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7160741B2 (en) * | 2003-11-06 | 2007-01-09 | Chartered Semiconductor Manufacturing Ltd. | Planar voltage contrast test structure and method |
KR100591771B1 (ko) * | 2005-02-07 | 2006-06-26 | 삼성전자주식회사 | 반도체 장치의 불량 분석을 위한 분석 구조체 |
KR100684892B1 (ko) * | 2005-03-14 | 2007-02-20 | 삼성전자주식회사 | 반도체 불량 분석을 위한 분석 구조체 |
KR100741858B1 (ko) * | 2006-05-18 | 2007-07-24 | 삼성전자주식회사 | 반도체 회로의 결함 검사용 모니터링 패턴 및 이를 이용한결함 검사 방법. |
KR100827440B1 (ko) * | 2006-09-29 | 2008-05-06 | 삼성전자주식회사 | 반도체 집적 회로 장치의 불량 분석 방법 및 시스템 |
KR100935581B1 (ko) * | 2007-06-28 | 2010-01-07 | 주식회사 하이닉스반도체 | 반도체 장치 및 이를 포함하는 워드라인 드라이버 |
KR100869746B1 (ko) * | 2007-07-13 | 2008-11-21 | 주식회사 동부하이텍 | 반도체 소자의 누설전류 모니터링 테그 및 그 제조방법 |
CN102053169B (zh) * | 2009-11-10 | 2014-02-05 | 中芯国际集成电路制造(上海)有限公司 | 互连结构失效分析样品的制作方法 |
CN102253328B (zh) * | 2010-05-21 | 2013-07-10 | 武汉新芯集成电路制造有限公司 | 存储芯片位线失效分析方法 |
CN102384867B (zh) * | 2010-09-02 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | 制备失效分析样品的方法 |
CN102176441B (zh) * | 2010-12-29 | 2012-10-03 | 杭州广立微电子有限公司 | 用于物理失效分析的改进型可寻址测试芯片及制作方法 |
CN102832201B (zh) * | 2011-06-15 | 2015-03-11 | 中芯国际集成电路制造(上海)有限公司 | 测试结构及测试方法 |
CN103035617B (zh) * | 2011-09-28 | 2016-08-17 | 无锡华润上华科技有限公司 | 芯片中模块的失效原因判定方法及晶圆结构 |
JP2014078290A (ja) | 2012-10-09 | 2014-05-01 | Toshiba Corp | 不揮発性半導体記憶装置 |
KR101482683B1 (ko) * | 2013-06-05 | 2015-01-16 | 한국과학기술원 | 단선 및 단락 테스트 구조를 갖는 3차원 집적 회로 및 이의 테스트 방법 |
CN103366055A (zh) * | 2013-06-28 | 2013-10-23 | 杭州广立微电子有限公司 | 一种可寻址测试芯片版图的生成方法 |
KR102066925B1 (ko) * | 2013-08-30 | 2020-01-16 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN103811468A (zh) * | 2013-12-10 | 2014-05-21 | 杭州广立微电子有限公司 | 一种可寻址测试芯片及其测试方法 |
CN104020408B (zh) * | 2014-05-26 | 2016-07-06 | 武汉新芯集成电路制造有限公司 | 存储芯片位线失效分析方法 |
US9831139B2 (en) * | 2016-01-18 | 2017-11-28 | Samsung Electronics Co., Ltd. | Test structure and method of manufacturing structure including the same |
CN106531724B (zh) * | 2016-11-30 | 2019-01-25 | 上海华力微电子有限公司 | 测试结构及测试方法 |
CN111092024B (zh) * | 2019-12-25 | 2023-02-07 | 上海华力微电子有限公司 | 检测闪存位线之间漏电结构的制造方法及漏电检测方法 |
KR102479995B1 (ko) * | 2020-11-16 | 2022-12-21 | 충남대학교 산학협력단 | 신소자 테스트 시스템 및 신소자 테스트 방법 |
US20220214398A1 (en) * | 2021-01-04 | 2022-07-07 | Changxin Memory Technologies, Inc. | Evaluation method for hot carrier effect degraded performance |
TWI750074B (zh) * | 2021-03-30 | 2021-12-11 | 力晶積成電子製造股份有限公司 | 半導體裝置的缺陷分析方法與電子裝置 |
CN114399508A (zh) * | 2022-03-25 | 2022-04-26 | 杭州广立微电子股份有限公司 | 晶圆数据的处理方法、装置、电子装置和存储介质 |
CN116936568A (zh) * | 2022-04-12 | 2023-10-24 | 长鑫存储技术有限公司 | 半导体版图结构及半导体测试结构 |
JP2024516754A (ja) * | 2022-04-12 | 2024-04-17 | チャンシン メモリー テクノロジーズ インコーポレイテッド | 半導体レイアウト構造及び半導体テスト構造 |
Family Cites Families (11)
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US5262719A (en) * | 1991-09-19 | 1993-11-16 | International Business Machines Corporation | Test structure for multi-layer, thin-film modules |
JPH0737988A (ja) * | 1993-07-20 | 1995-02-07 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP3501880B2 (ja) * | 1995-08-02 | 2004-03-02 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法および半導体ウエハ |
JPH0964122A (ja) * | 1995-08-21 | 1997-03-07 | Matsushita Electric Ind Co Ltd | プローブカード、プローブカードの製造方法及びプローブカードを用いた半導体装置の製造方法 |
JPH09321245A (ja) * | 1996-05-30 | 1997-12-12 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP3592318B2 (ja) | 2001-08-14 | 2004-11-24 | 沖電気工業株式会社 | 半導体装置の検査方法及び半導体装置の検査システム |
KR20030050651A (ko) | 2001-12-19 | 2003-06-25 | 주식회사 하이닉스반도체 | 일렉트로마이그레이션 측정용 테스트패턴 |
US6768144B2 (en) * | 2001-12-31 | 2004-07-27 | Texas Instruments Incorporated | Method and apparatus for reducing leakage current in an SRAM array |
JP2003332449A (ja) * | 2002-05-15 | 2003-11-21 | Nec Electronics Corp | 半導体装置の製造方法 |
JP4184036B2 (ja) * | 2002-10-25 | 2008-11-19 | 株式会社ルネサステクノロジ | 半導体記憶装置およびそのテスト方法 |
JP4088143B2 (ja) * | 2002-11-28 | 2008-05-21 | シャープ株式会社 | 不揮発性半導体記憶装置及び行線短絡不良検出方法 |
-
2004
- 2004-12-07 KR KR1020040102543A patent/KR100748552B1/ko active IP Right Grant
-
2005
- 2005-11-30 US US11/291,242 patent/US7468530B2/en active Active
- 2005-12-05 TW TW094142743A patent/TWI275815B/zh active
- 2005-12-06 JP JP2005352535A patent/JP5258161B2/ja active Active
- 2005-12-07 CN CNB200510128845XA patent/CN100557797C/zh active Active
Also Published As
Publication number | Publication date |
---|---|
KR100748552B1 (ko) | 2007-08-10 |
US20060118784A1 (en) | 2006-06-08 |
JP2006165569A (ja) | 2006-06-22 |
US7468530B2 (en) | 2008-12-23 |
TWI275815B (en) | 2007-03-11 |
KR20060063380A (ko) | 2006-06-12 |
CN1805139A (zh) | 2006-07-19 |
JP5258161B2 (ja) | 2013-08-07 |
CN100557797C (zh) | 2009-11-04 |
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