TW200604093A - Silicon nitride film with stress control - Google Patents

Silicon nitride film with stress control

Info

Publication number
TW200604093A
TW200604093A TW094122624A TW94122624A TW200604093A TW 200604093 A TW200604093 A TW 200604093A TW 094122624 A TW094122624 A TW 094122624A TW 94122624 A TW94122624 A TW 94122624A TW 200604093 A TW200604093 A TW 200604093A
Authority
TW
Taiwan
Prior art keywords
etch stop
nitride
nitride etch
substrate
silicon nitride
Prior art date
Application number
TW094122624A
Other languages
English (en)
Other versions
TWI345553B (en
Inventor
R Suryanarayanan Iyer
Andrew M Lam
Yuji Maeda
Thomas Mele
Jacob W Smith
Sean M Seutter
Sanjeev Tandon
Randhir P Singh Thakur
Sunderraj Thirupapuliyur
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of TW200604093A publication Critical patent/TW200604093A/zh
Application granted granted Critical
Publication of TWI345553B publication Critical patent/TWI345553B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
TW094122624A 2004-07-06 2005-07-04 Silicon nitride film with stress control TWI345553B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/885,969 US7488690B2 (en) 2004-07-06 2004-07-06 Silicon nitride film with stress control

Publications (2)

Publication Number Publication Date
TW200604093A true TW200604093A (en) 2006-02-01
TWI345553B TWI345553B (en) 2011-07-21

Family

ID=35124326

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094122624A TWI345553B (en) 2004-07-06 2005-07-04 Silicon nitride film with stress control

Country Status (6)

Country Link
US (1) US7488690B2 (zh)
JP (1) JP2008506262A (zh)
KR (2) KR100903891B1 (zh)
CN (1) CN100536161C (zh)
TW (1) TWI345553B (zh)
WO (1) WO2006014471A1 (zh)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7122222B2 (en) * 2003-01-23 2006-10-17 Air Products And Chemicals, Inc. Precursors for depositing silicon containing films and processes thereof
JP4444027B2 (ja) * 2004-07-08 2010-03-31 富士通マイクロエレクトロニクス株式会社 ｎチャネルＭＯＳトランジスタおよびＣＭＯＳ集積回路装置
DE102004047631B4 (de) * 2004-09-30 2010-02-04 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden einer Halbleiterstruktur in Form eines Feldeffekttransistors mit einem verspannten Kanalgebiet und Halbleiterstruktur
US7429775B1 (en) 2005-03-31 2008-09-30 Xilinx, Inc. Method of fabricating strain-silicon CMOS
US7423283B1 (en) 2005-06-07 2008-09-09 Xilinx, Inc. Strain-silicon CMOS using etch-stop layer and method of manufacture
US7655991B1 (en) * 2005-09-08 2010-02-02 Xilinx, Inc. CMOS device with stressed sidewall spacers
US7456058B1 (en) * 2005-09-21 2008-11-25 Advanced Micro Devices, Inc. Stressed MOS device and methods for its fabrication
US7936006B1 (en) 2005-10-06 2011-05-03 Xilinx, Inc. Semiconductor device with backfilled isolation
US8729635B2 (en) * 2006-01-18 2014-05-20 Macronix International Co., Ltd. Semiconductor device having a high stress material layer
US9048180B2 (en) * 2006-05-16 2015-06-02 Texas Instruments Incorporated Low stress sacrificial cap layer
US7824968B2 (en) * 2006-07-17 2010-11-02 Chartered Semiconductor Manufacturing Ltd LDMOS using a combination of enhanced dielectric stress layer and dummy gates
US7790635B2 (en) * 2006-12-14 2010-09-07 Applied Materials, Inc. Method to increase the compressive stress of PECVD dielectric films
US7968949B2 (en) * 2007-01-30 2011-06-28 International Business Machines Corporation Contact forming method and related semiconductor device
US7678698B2 (en) * 2007-05-04 2010-03-16 Freescale Semiconductor, Inc. Method of forming a semiconductor device with multiple tensile stressor layers
US20090014807A1 (en) * 2007-07-13 2009-01-15 Chartered Semiconductor Manufacturing, Ltd. Dual stress liners for integrated circuits
CN101399186B (zh) * 2007-09-24 2010-06-02 联华电子股份有限公司 氮化硅间隙填充层及其形成方法
DE102007052050B4 (de) * 2007-10-31 2010-04-08 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement und Verfahren zum Erhöhen der Ätzselektivität während der Strukturierung einer Kontaktstruktur des Halbleiterbauelements
US20090142891A1 (en) * 2007-11-30 2009-06-04 International Business Machines Corporation Maskless stress memorization technique for cmos devices
JP2009147199A (ja) * 2007-12-17 2009-07-02 Renesas Technology Corp 半導体装置および半導体装置の製造方法
JP5309619B2 (ja) * 2008-03-07 2013-10-09 ソニー株式会社 半導体装置およびその製造方法
US7863201B2 (en) * 2008-03-24 2011-01-04 Samsung Electronics Co., Ltd. Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance
JP2010141281A (ja) * 2008-11-11 2010-06-24 Renesas Technology Corp 半導体装置およびその製造方法
JP5282978B2 (ja) * 2009-12-18 2013-09-04 日立電線株式会社 Ｉｉｉ族窒化物半導体基板
CN102213877B (zh) * 2010-04-06 2013-10-02 北京京东方光电科技有限公司 阵列基板、液晶面板及其制造方法
US9997357B2 (en) 2010-04-15 2018-06-12 Lam Research Corporation Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
US9257274B2 (en) 2010-04-15 2016-02-09 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
US8637411B2 (en) 2010-04-15 2014-01-28 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9892917B2 (en) 2010-04-15 2018-02-13 Lam Research Corporation Plasma assisted atomic layer deposition of multi-layer films for patterning applications
US9373500B2 (en) 2014-02-21 2016-06-21 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
CN102299101B (zh) * 2010-06-25 2014-10-01 中芯国际集成电路制造(上海)有限公司 刻蚀终止层的制作方法
US8647993B2 (en) * 2011-04-11 2014-02-11 Novellus Systems, Inc. Methods for UV-assisted conformal film deposition
EP2714960B1 (en) * 2011-06-03 2018-02-28 Versum Materials US, LLC Compositions and processes for depositing carbon-doped silicon-containing films
JP2013008828A (ja) * 2011-06-24 2013-01-10 Taiyo Nippon Sanso Corp シリコン絶縁膜の形成方法
US8809152B2 (en) * 2011-11-18 2014-08-19 International Business Machines Corporation Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices
KR101847629B1 (ko) 2012-02-10 2018-04-10 삼성전자주식회사 반도체 소자
JP2012142586A (ja) * 2012-02-20 2012-07-26 Gas-Phase Growth Ltd 膜形成材料および膜形成方法
JP6538300B2 (ja) 2012-11-08 2019-07-03 ノベラス・システムズ・インコーポレーテッドＮｏｖｅｌｌｕｓ Ｓｙｓｔｅｍｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 感受性基材上にフィルムを蒸着するための方法
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US10566187B2 (en) 2015-03-20 2020-02-18 Lam Research Corporation Ultrathin atomic layer deposition film accuracy thickness control
CN106611701A (zh) * 2015-10-27 2017-05-03 中微半导体设备(上海)有限公司 一种半导体器件的制备方法
JP6385965B2 (ja) * 2016-01-22 2018-09-05 株式会社東芝 高周波スイッチ
US9773643B1 (en) 2016-06-30 2017-09-26 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US10062563B2 (en) 2016-07-01 2018-08-28 Lam Research Corporation Selective atomic layer deposition with post-dose treatment
US10037884B2 (en) 2016-08-31 2018-07-31 Lam Research Corporation Selective atomic layer deposition for gapfill using sacrificial underlayer
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
US10566446B2 (en) * 2018-05-30 2020-02-18 Globalfoundries Inc. Mitigation of hot carrier damage in field-effect transistors
US11222820B2 (en) 2018-06-27 2022-01-11 International Business Machines Corporation Self-aligned gate cap including an etch-stop layer
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
KR20210129656A (ko) 2019-01-23 2021-10-28 코르보 유에스, 인크. Rf 반도체 디바이스 및 이를 형성하는 방법
KR20210129658A (ko) 2019-01-23 2021-10-28 코르보 유에스, 인크. Rf 반도체 디바이스 및 이를 형성하는 방법
US20210134699A1 (en) * 2019-11-01 2021-05-06 Qorvo Us, Inc. Rf devices with nanotube particles for enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4946710A (en) * 1987-06-02 1990-08-07 National Semiconductor Corporation Method for preparing PLZT, PZT and PLT sol-gels and fabricating ferroelectric thin films
JP3050193B2 (ja) * 1997-11-12 2000-06-12 日本電気株式会社 半導体装置及びその製造方法
US6323519B1 (en) 1998-10-23 2001-11-27 Advanced Micro Devices, Inc. Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process
US6261891B1 (en) * 2000-01-28 2001-07-17 United Microelectronics Corp. Method of forming a passivation layer of a DRAM
US6515350B1 (en) * 2000-02-22 2003-02-04 Micron Technology, Inc. Protective conformal silicon nitride films and spacers
US6518626B1 (en) 2000-02-22 2003-02-11 Micron Technology, Inc. Method of forming low dielectric silicon oxynitride spacer films highly selective of etchants
US6559007B1 (en) 2000-04-06 2003-05-06 Micron Technology, Inc. Method for forming flash memory device having a tunnel dielectric comprising nitrided oxide
JP2001319972A (ja) * 2000-05-12 2001-11-16 Sony Corp 半導体装置の製造方法
US6850250B2 (en) 2000-08-29 2005-02-01 Sony Corporation Method and apparatus for a declarative representation of distortion correction for add-on graphics in broadcast video
US20020081811A1 (en) 2000-12-27 2002-06-27 Pietro Foglietti Low-temperature deposition of silicon nitride/oxide stack
JP2003086708A (ja) 2000-12-08 2003-03-20 Hitachi Ltd 半導体装置及びその製造方法
KR100385857B1 (ko) * 2000-12-27 2003-06-02 한국전자통신연구원 SiGe MODFET 소자 제조방법
US6500772B2 (en) 2001-01-08 2002-12-31 International Business Machines Corporation Methods and materials for depositing films on semiconductor substrates
JP4771607B2 (ja) 2001-03-30 2011-09-14 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP2003060201A (ja) * 2001-08-13 2003-02-28 Hitachi Ltd 半導体装置の製造方法
US6534807B2 (en) 2001-08-13 2003-03-18 International Business Machines Corporation Local interconnect junction on insulator (JOI) structure
JP2003060076A (ja) * 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
US6660598B2 (en) 2002-02-26 2003-12-09 International Business Machines Corporation Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
KR100953332B1 (ko) * 2002-12-31 2010-04-20 동부일렉트로닉스 주식회사 반도체 장치의 제조 방법
JP4653949B2 (ja) * 2003-12-10 2011-03-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
KR100652791B1 (ko) * 2003-12-18 2006-11-30 주식회사 하이닉스반도체 반도체소자 제조 방법

Also Published As

Publication number Publication date
CN100536161C (zh) 2009-09-02
WO2006014471A1 (en) 2006-02-09
KR100903891B1 (ko) 2009-06-19
KR20080112370A (ko) 2008-12-24
KR101022898B1 (ko) 2011-03-16
JP2008506262A (ja) 2008-02-28
TWI345553B (en) 2011-07-21
US7488690B2 (en) 2009-02-10
US20060009041A1 (en) 2006-01-12
KR20070029829A (ko) 2007-03-14
CN1989622A (zh) 2007-06-27

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