TW200529293A - Masking methods - Google Patents

Masking methods Download PDF

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Publication number
TW200529293A
TW200529293A TW093125232A TW93125232A TW200529293A TW 200529293 A TW200529293 A TW 200529293A TW 093125232 A TW093125232 A TW 093125232A TW 93125232 A TW93125232 A TW 93125232A TW 200529293 A TW200529293 A TW 200529293A
Authority
TW
Taiwan
Prior art keywords
substrate
amorphous carbon
boron
photomask
doped amorphous
Prior art date
Application number
TW093125232A
Other languages
English (en)
Other versions
TWI287827B (en
Inventor
Zhi-Ping Yin
Gurtej S Sandhu
Original Assignee
Micron Technology Inc
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Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW200529293A publication Critical patent/TW200529293A/zh
Application granted granted Critical
Publication of TWI287827B publication Critical patent/TWI287827B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/952—Utilizing antireflective layer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

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200529293 九、發明說明： 【發明所屬之技術領域】 本發明關係在積體電路製造中光罩半導體基板的方法。 【先前技術】 積體電路-般在半導體基板上形成，如梦日日日圓或其他半 導體材料。—般而t，使用不同材料層如半導電、導電或 絕緣材料以形成積體電路。例如，使用不同方法處理:同 材料’如，摻雜、離子植入、沉積、姓刻，生長等。半導 體處理的-連續目標為繼續致力於減少個別電子組件的尺 寸’因而成為更小及更密的積體電路。 種圖案化及處理半導體基板的技術為微影蝕刻。其一 般包括光阻層的沉積，然後加以處理以改變該層在某些溶 劑中的溶解度。例如，可以將部份光阻層透過光罩/主光罩 曝光光化能，以改變曝光區對非曝光區的溶劑溶解度以比 車，L積狀L的/合解度。然後，根據光阻的種類移除該等曝 光或未曝光部份，因而在基板上留下光阻的光罩圖案。可 以處理鄰近光罩部份的基板鄰近區，例如，由蝕刻或離子 植入，以執行鄰近該光罩材料之基板的理想處理。 一在某些例子中，已知的光罩/微影蝕刻步驟使用不同的多 光阻層。另外，可以一或更多其他層結合該微影光罩及圖 y、 種私序在忒光阻層（或泫等光阻層）沉積之前於基板 上面形成一般所謂的「硬光罩」。然後，圖案化該光阻層， 例如，如上述在硬光罩上形成光罩組塊。然後，使用該光 阻作為光罩以蝕刻硬光罩以轉移該光阻圖案至硬光罩。然 95476.doc 200529293 後立刻移除或不移除該光 用光阻更強固的光罩圖案 飿刻。 上述硬光罩提供一比單獨使 ’例如蝕射光阻必須完全腐蝕/ -種用來作為硬光罩的材料為非晶碳 作為硬光罩而㈣氧化物材 aa^ 率約比移除非晶碳快1〇倍。叙钮刻移除氧化物的速 述微影：刻方法以外，還有其他光單方法。例如， :收 利用¥电閘極’—般經由半導體材料的通道區 電性摻雜源極々極半導體材料區-般在通道區的 反面接收，而間極位於其間通道區的上面或下面。在某些 =::Γ想，經過源崎極區的摻雜分佈比其遠端一處 低更接近料㈣。—種提供該種㈣分佈的處理 方法為百先形成一理想的導電開極，約略在半導體基板的 理4通道區上面。然後，將適當植入量的導電性增強雜質 植入基板的半導體材料内，利用閘極結構防止該種雜質植 入該通道區。所以’絕緣層能局部沉積在間極結構上面及 異向性姓刻以形成絕緣性側壁間隔物於該開極上面。這些 側壁間隔物有效㈣作為光罩，其保護閘極㈣及防止I 剛形成的間隔物下面產生一後續植入。因此，可使用側壁 間隔物作為後續植入較高劑量的源極/汲極雜質的光罩，以 元成理想源極/汲極區的輪扉的形成。 雖然本發明的目的在處理上述問題，但並不限於此。本 發明只受附件申請專利範圍如文字表述（不包括上述背景 技術說明’剩餘的部份說明書或圖）的限制及其相當原理所 95476.doc 200529293 限制。 【發明内容】 本發明包括光罩方法。在實施例中，在一實施例中，一 光罩材料包括纟一半導體基板上形成一特徵之上形成的删 換雜非晶碳。該光罩材料包括至少約〇 5原子百分比㈣。 .亥光罩材料貝貝上為異向性蝕刻以有效形成一異向性蝕刻 側壁間隔物’該間隔物包括位於該特徵側壁上的硼摻雜非 晶碳。然|處理鄰近該間隔物的基板並使用包括間隔物之 該领摻雜非晶碳作為—光罩。處理鄰近關隔物的基板 後自5亥基板蝕刻包括間隔物之該硼摻雜非晶碳。 可以了解尚有其他觀點及實施例。 【實施方式】 本發明的揭示係為實現美國專利法的基本㈣「為促進 科學及有用技術的進步」（第一章第八節）。 首先參考圖1-8說明根據本發明的範例性光罩方法。首先 參考圖卜所顯示的半㈣基板片段的參考號碼為10。在本 文中’名詞「半導體基板」《「半導電基板」的定義皆為 任何包括半導電材料的結構，其包括但不限於，主要半導 電材料如半導體晶圓（單獨或包括其他材料的組件）及半導 電材料層(單獨或包括其他材料的組件)。名詞「基板」表示 任何支撐結構，其包括但不限於，上述的半導體基板。同 装在本文中，名言可「層」包括單數及複數，除非另有說 明0 在本例中，基板H)包括-主要單^基板12。其上面具 95476.doc 200529293 有一些特欲14。考慮任何可辨認的結構特徵，不論是既有 或尚待發展。舉例而已，例子包括圖案化光阻層、部份或 完全場效電晶體閘極或其他電路結構、基板内的蝕刻區 等。舉例而已，圖1的特徵14顯示基板12上形成的一些圖案 化材料形狀。側壁丨6在所示的具體實施例中實質上垂直基 板12。光罩材料18包括、或由特徵14上形成的领摻雜非晶 石反組成。δ亥種光罩材料包括至少約〇·5原子百分比的硼。一 範例ί± #乂仏具體貫施例包括一從約丨〇原子百分比至約W 原子百分比的蝴濃度。另外的例子，舉例而已，包括從約 1.0原子百分比至約50原子百分比的石朋濃度；從大於原 子百分比至約1〇·〇原子百分比的领濃度；從大於〇原子百 分比至約15.〇原子百分比的石朋濃度；從大於15 〇原子百分比 至約20.0原子百分比的领濃度；以及從大於则原子百分比 至約75.0原子百分比的硼濃度。 曰f一範例性具體實施例中，該特徵可包括未摻雜硼的非 曰曰厌在本文中，「未摻雜硼」表示不具有任何可偵測量的 一 果至v特欲14的最外部份為未摻雜硼的非晶碳，則 光罩材料18在該非晶碳材料上面形成（意即相接觸）。、 ”-形成㈣雜非晶碳材料i 8的較佳範例係使用化學汽相 ’儿積(CVD)’及需要或不需要電漿增強。另外 化學汽相沉積中或之德產在户 _ ^ 灸產生。在一砣例性較佳具體實施例 :化予咖積使用至少c2h6、CA、C2H2、C3H6及LA H另外在—較佳具體實施例令，化學汽相沉積使用至 2 6、Β4Η滅叫C〇之—，及因而在剛沉積的《雜處 95476.doc 200529293 形成非晶碳。 舉例而已，範例性化學汽相沉積工具包括Santa Clara， California，應用材料公司出品的 Applied Materials Centura 處理器及Producer處理器。進一步舉例而已，下列提供利用 該等處理器的化學汽相沉積材料1 8的範例性較佳方法。一 種範例性處理氣體為C3H6，其範例性流率為300 seem至900 seem，600 seem為一特例。B2H6為一範例性的蝴源氣體， 其可與03116，流動，及其範例性流率從100 seem至2000 seem，根據其他氣體的流率及根據預定形成硼摻雜非晶碳 層的硼濃度而定。另外範例性載體或其他反應性或非反應 性氣體也可以利用，例如，從0 seem至500 seem的He及/或 H2。一範例性較佳基板溫度為400 ° C至650 ° C，及一範例性 較佳壓力範圍為3 Τοιτ至7 Τοιτ。一晶圓表面至氣體喷頭的 範例性理想距離為190 mils至240 mils。一容量耦合單電極 電漿沉積工具（如上述）的範例性較佳功率施加範圍為10 0瓦 特至800瓦特（對於200 mm晶圓而言）。進一步舉例而已，範 例性非電漿增強CVD參數包括一約為500°C至800°C的溫 度、壓力為50 mTorr至200 mTorr、流量為50 seem至1000 seem 的C3H6、流量為 100 seem 至 2000 seem 的 B2H6，及含有 或沒有任何He及/或H2。 在沉積過程中已決定的硼摻雜量影響特徵斜坡上沉積材 料1 8的正形度。總之，較高的硼濃度具有較佳的斜坡覆蓋 範圍。例如在上述參數範圍内，B2H6對C3H6的體積流率比 為0.4，與水平面相比在垂直斜坡上約有26%的覆蓋範圍， 95476.doc 200529293 同時hH6對CsH6的流率比為2·1，與水平面相比在垂直斜坡 上約有64%的覆蓋範圍。流率〇·4提供材料is—原子硼濃度 約為3.0°/◦石朋，而流率2.1則提供約16%领。決定電極上的RF 功率並不特別影響相對正形性。在一實際減少的例子中， 與水平面相比，垂直面上的斜坡覆蓋範圍約為74%，喷頭/ 晶圓表面的距離為215 mils、功率為250瓦特、及先驅流率 為 1250 sccm b2H6、650 seem C3H6、基板溫度為 550°C及反 應室壓力為5 Ton*。根據該應用來決定需要或不需要高正形 度0 參考圖2 ’光罩材料18實質上已異向性蝕刻並有效形成一 異向性蝕刻側壁間隔物20，其包括位於特徵14的側壁16上 的硼摻雜非晶碳。舉例而已，異向性蝕刻此類材料的範例 性程序包括使用CL及/或其他氟化物的組合，該氟化物包 含 5 seem 至 20 sccm 的氣體、20 sccm 至 6〇 %(^的3〇2及5〇 seem至120 seem的〇2。一範例性基板溫度為5。€至^。匸，反 應室壓力為5 mTon:至15 mT〇rr ’及源電漿功率為15〇至25〇 瓦特及偏壓功率為30至100瓦特（每晶圓直徑2〇〇mm)。 、使用包括間隔物之《雜非晶碳作為光I，然後處理鄰 近該？隔物的基板。舉例而6，使用包括間隔物的硼摻雜 非晶碳作為光罩的基板處理可包括離子植人基板、姓刻& 板及在基板上沉積之任何-者或其組合。例如，圖 :才直入型的範例性處理以形成擴散區22。圖4顯㈣刻 祀例性處理以形成相對基板的凹穴或溝渠部份Μ。圖$顯干 沉積程序的例子’使用包括間隔物2Q的卿雜非晶碳作為 95476.doc -10 - 200529293 光罩以便於由間隔物20覆蓋的基板材料12上面立刻沉積層 2 6 ’藉以在基板12上沉積一層2 6。舉例而已，圖6顯示一此 選擇性沉積/處理的型式，使用包括間隔物2〇的硼摻雜非晶 碳遮罩該處理之下的基板材料12，以於基板材料12上面形 成層28。舉例而已，該種沉積可包括磊晶矽生長及/或熱處
理及/或其他選擇性沉積/形成方法（不論是既有或尚待發 展）。 X 基板處理後，蝕刻基板上包括間隔物的硼摻雜非晶碳。 圖7顯不圖3所示的處理的後續處理。一種最佳蝕刻處理程 序使用包括電漿的〇2來蝕刻包括間隔物的硼摻雜非晶碳。 舉例而已，一般範例性較佳程序利用具有基板溫度為3〇〇。匸 至650 C基板至喷頭的距離為4〇〇 ^^1§至8、壓力 為 4 Ton* 至 9 Ton*、〇2氣體流量1〇〇〇 sccm 至25〇〇 %〇茁、及 «功率範圍為_瓦特至議瓦特的〇2磨光電毁反應 至在此條件下處理實質上可在75秒内完成含有0.5%至 1.0/。领的包括間隔物之领摻雜非晶碳之薄膜b⑼埃厚度的 等向姓刻。 一 毛見哪4雜浪度提供斜坡覆蓋範圍及減 輕均質唯氧電魏巍势丨 之間的_和。雖然較高硼濃度造成較 佳斜坡覆盖範圍、齡古、曲 同朋?辰度，但唯氧電漿較難從基板中 姓刻此類材料。μ 口為硼摻雜超過10原子百分比，在上述停 件下唯氧電漿蝕刻變Α又π &， ^ d欠為不可接受的緩慢。舉例而已，一包 έ CF4的钱刻氣體蝕刻 曰 括間隔物的非晶碳，但不受硼摻雜 ΐ影響。 95476.doc 200529293 使用包含電漿的〇 2蝕刻—基板的犧牲間隔物的能力在上 述條件下須實質上選擇二氧切、氮切、單0，及多 晶石夕之任何-者來進㈣刻可具有特㈣益。此類 擇的《雜非晶碳比二氧切、氮切、單㈣、及多晶 石夕之任何-者的比較_率至少為2:1。因此，如果在㈣ 基板㈣包括間隔物之犧牲师雜非晶碳之中或之前立刻 將基板上的任何材料曝光，則可選擇任何曝光材料姓刻均 為有利。 參考圖8,也在一範例性實施例中，基板的特徵14(未顯 岣也完成敍刻。當然，可以自該基板中敍刻包括間隔⑽ 的硼摻雜非晶碳之前或之後發生。或者，根據形成的結構 及形成的特徵形式，保留該特徵在該基板上一段時間或構 成最後完成的電路系統結構的一部份。 參考圖9-12說明另外的範例性處理例子。圖9顯示一基板 片段40,其包括半導體基板材料42。一對閘極結構私及牝 在基板材料42上面形成。舉例而已，該對閘極包括一閑極 氧化層48、-導電多碎層5()、―収金屬切火金屬石夕化 層52、及一絕緣帽54。閘極結構44及46作為一對相鄰特徵， 其上可形成上述的光罩材料及進行後續處理，如上述。在 一範例性考慮觀點中，特徵44及46可使用具有最小開口尺 寸的光罩微影蝕刻處理形成，例如，尺寸rA」相當於特徵 44及46的最近壁之間的間隔距離。光罩/主光罩的尺寸「a 可稍小或稍大於圖9所示的實際尺寸rA」，例如，根據微影 蝕刻處理的方位及/或像差而定。在一考慮的實施例中，= 95476.doc -12 - 200529293 =開口尺^例如尺寸「A」）較理想為該光罩方法及本文所 述方法之4)或之後的所有半導體基板微影钱刻處理所利用 的最J開口尺寸。例如’由微影蝕刻處理獲得的特徵料及 6之間的距_為處理基板時生產程序技術上所能獲得的最 小尺寸。相對基板42形成範例性擴散區58。 參考圖10，光罩材料60包括硼摻雜非晶碳，其形成在所 示的基板及特徵的上面。此類材料較理想具有任何相同特 性，如根據首先具體實施例說明的光罩材料18的說明。 參考圖11，光罩材料60實質上異向性蝕刻並有效形成相 隔異向性蝕刻側壁間隔物62及側壁間隔物64對。相鄰異向 性蝕刻側壁間隔物62由最短距離rB」分離，因而距離「B」 比圖9所示最小開口距離「Α」更小。鄰近該等間隔物之基 板的範例性處理為植入型式以形成區66並靠近該等間隔 物。 多考圖12，使用上述處理完成自基板敍刻包括間隔物a 及64的獨摻雜非晶碳。 參考圖13-15舉例說明另外的範例性處理例子。圖13顯示 一基板片段70，其包括半導體基板材料72。一層74，例如 二氧化矽，在材料72上面形成。例如未摻雜硼的非晶碳的 另外層76於材料74上面被接受。穿過層76形成一開口 ”並 具有壁78。壁78可作為層76相鄰特徵的一部份，其定義開 口 77的至少一些部份。在一範例性考慮觀點中，特徵78可 使用具有最小開口尺寸的光罩微影蝕刻處理形成，例如， 尺寸「C」相當於定義開口 77的最近壁之間的間隔距離。如 95476.doc -13- 200529293 上述尺寸「A」，弁置/ 所m 寸」可稍小或稍大於 圖13所不結構之間的實 .^ A …丁、尺寸C」，例如，根據微影蝕刻 處理的方位及/或像差而定。在一考慮的實施例中，最小開 口尺例如尺寸「c」）較理想為該光罩方法及本文所述方 彳或之後的所有半導體基板微影似彳處理所利用的最 寸例如由彳政影蝕刻處理獲得的特徵78之間的 離可為處理4基板時生產程序技術上所能獲得的最小尺 寸0 光罩材料80包括财雜非晶碳，其在所示的基板及特徵 的上面形成。此類材料較理想具有任何相同特性，如根據 1·先具體實施例說明的光罩材料18的說明。 參考圖14 ’光罩材料8G實質上異向性敍刻並有效形成相 隔異向性蝕刻側壁間隔物82對。相鄰異向性蝕刻側壁間隔 物82由最短距離「D」分離，因而距離「D」比圖13所示最 小開口距離「C」更小。鄰近該等間隔物的基板之範例性處 理為蚀刻層74的型式，以形成開口 84達靠近間隔物82之基 板材料7 2。 多考圖15，使用上述處理完成自基板姓刻包括間隔物$ 2 的該删摻雜非晶碳。
申請曰期2003年6月17曰的美國專利申請序號 10/463,185，標題為「侧摻雜非晶碳膜用作半導體裝置形成 的硬姓刻光罩（Bor〇n-D〇ped Amorphous Carbon Film For Use As A Hard Etch Mask During The Formation Of A
Semiconductoi· Device)」，發明人 Zhiping Yin 及 Gurtej 95476.doc -14- 200529293
Sarnlhu，全文以提示方式併入本文。 根據法令，本發明已經或多或少 的特徵。不過，必項了 ° 寸定的構造及方法 特徵，因為本文揭露的構件包括m ^及所示的特定 所以’本發明主張任何根據相心备明的較佳型式。 皆在所附中請專利範圍之内田的原理解釋的型式或修改 【圖式簡單說明】 說明參考下列附圖。 理步驟之半導體晶圓片段的 本發明之較佳具體實施例的 圖1為根據本發明觀點的處 不意斷面圖。 圖1晶圓片段的視圖 圖2晶圓片段的視圖 〇 圖2為在圖1所述的後續處理步驟中 圖3為在圖2所述的後續處理步驟中 圖4為在圖3所述以外的其他視圖。 圖5為在圖3所述以外的其他視圖。 圖6仍為在圖3所述以外的其他視圖 圖7為在圖3所述的後續處理步驟中圖以圓片段的視圖 圖8為在圖7所述的後續處理步驟中圖7晶_段的㈣c 圖9為根據本發明觀點的處理步驟之另外半導體晶圓片 段的示意斷面圖。 圖9晶圓片段的視 圖10為在圖9所述的後續處理步驟中 圖。 圖11為在圖10所述的後續處理步驟中圖1〇晶圓片段的視 〇 圖12為在圖11所速的後續處理步驟中圖丨丨晶圓片段的視 95476.doc -15- 200529293 圖。 圖13為根據本發明觀點的處理步驟之另外半導體晶圓片 段的示意斷面圖。 圖14為在圖13所述的後續處理步驟中圖13晶圓片段的視 圖。 圖15為在圖14所述的後續處理步驟中圖14晶圓片段的視 圖。 【主要元件符號說明】 10 、 40 、 70 半導體基板片段 12 早晶砍基板 14 特徵 16 側壁 18、60 光罩材料 20 、 62 、 64 ， 82 側壁間隔物 22 、 58 、 66 擴散區 24 溝渠部份 26 層 28 層 42、72 半導體基板材料 44，46 閘極 48 閘極氧化層 50 導電多矽層 52 防火金屬矽化層 54 絕緣層 95476.doc -16- 200529293 74 層 76 層 77 開口 78 壁 80 光罩材料 82 側壁間隔物 84 開口 95476.doc - 17-

Claims (1)

  1. 200529293 申請專利範圍： j. -種光罩方法，包括·· 形成-光罩材料，其包括在—半導體基板上形成的特 徵上面的硼換雜非晶碳，該光草材料包括至少约0.5原子 百分比的领； 實質上異向性敍刻該光罩材料以有效形成一異向性敍 刻側壁間隔物，該間隔物於該特徵側壁上面包括該领摻 雜非晶碳； ，使用包㈣隔物的㈣摻雜非晶碳作為光罩並處理鄰 近該間隔物的該基板；及 在處理該基板後，自該基板餘刻包括間隔物的該㈣ 雜非晶碳。 =明求項1之方法’其中在該特徵上面形成的該光罩材料 包括未摻雜硼的非晶碳。 ，、2之方法中遠t罩材料在未推雜删的非晶碳 上面形成。 月，=1之方法’其中該光罩材料在一對相鄰特徵上形 側辟異向性㈣係有效形成—對相隔異向性姓刻 側壁間隔物。 5.如請求項4之方法，其中， ”有取小開口尺寸的光罩藉由微影敍刻處理形成 德了目鄰特徵；該最小開口尺寸為該光罩方法之前及之 何及所有半導體基板的微影钱刻處理使用的最小開 口尺寸；及 95476.doc 200529293 該等相鄰異向性蝕刻側壁間隔物相隔一最短距離，該 最紐距離小於該最小開口尺寸。 长員1之方法，其中该光罩材料主要由石朋摻雜非晶碳 組成。 长員1之方法，其中该光罩材料由领摻雜非晶碳組 成。 8 ·々明求項1之方法，其中該形成包括cvd 〇 9·如凊求項8之方法，其中該CVD為電漿增強。 1〇·如睛求項8之方法，其卡該CVD未電漿增強。 11 ·如凊求項8之方法，其中硼摻雜在CVD中發生。 12·如睛求項8之方法，其中硼摻雜在CVD後發生。 月求項1之方法，其中該形成包括CVD使用C2H6、 4 C2H2、C3H6& C3H8之至少一者，及使用 B2h6、 及BH3C〇之至少一者。 14·如明求項13之方法，其中該CVD為電漿增強。 15.如：求項13之方法，其中該⑽未電漿增強。 16·如印求項1之方法，#中該特徵側壁係實質上垂直該基 17 :二求項1之方法，其中該光罩材料包括丨.0原子百分比至 •'、子百分比的蝴。 18·如請求項1之方法，苴 -^光罩材料包括大於5.0原子百分 匕至1〇.0原子百分比的领。 1 9.如清求項】$古、土 jj.. / 、 / ，/、中該光罩材料包括大於10.0原子百 刀比至15.0原子百分比的硼。 95476.doc 200529293 2 〇 ·如請求項1 、之方法，其中該光罩材料包括大於15〇原子百 分比至2〇.〇原子百分比的硼。 21 ·如請求jg 1 、之方法，其中該光罩材料包括大於2〇·〇原子百 刀匕至75.0原子百分比的蝴。 2 2 ·如請求項1 紅 <方法，其中該基板使用包括間隔物的該硼摻 亦隹非Β日衩作為光罩之該處理包括蝕刻該基板。 月长員1之方法，其中該基板使用包括間隔物的該硼摻 雜非晶碳作為光罩之該處理包括離子植入該基板。 2 4 ·如請求項1夕士 、乏方法，其中該基板使用包括間隔物的該硼摻 阳妷作為光罩之該處理包括於基板上沉積。 月求員1之方法，其中該蝕刻使用包括電漿的〇2。 26·如請求項1之方法，進-步包括在該基板之該處理後，自 基板飯刻該特徵。 27.如請求項26之方法，其中在自該基板蝕刻包括間隔物的 «亥蝴4雜非晶奴之後’自該基板蚀刻該特徵。 28· —種光罩方法，包括·· 其包括在一半導體基板上 化學汽相沉積一光罩材料 形成的特徵上_摻雜非晶碳，該光罩材料包括至少 約1.0原子百分比至約20原子百分比的硼； 實質上異向性蝕刻該光罩材料 以有效形成一異向性蝕 刻側壁間隔物 雜非晶碳； 該間隔物於該特徵側壁上面包括該硼摻 使用包括間隔物的該蝴摻雜非晶碳作為一光罩並處理 鄰近該間隔物的該基板；及 95476.doc 200529293 在基板之該處理後，使用— 括〇2之電裝實質卜；II樓 曝光二氧化石夕、氮化石夕及石夕 小 、、 王V —者，自該基板蝕 包括間隔物的該石朋摻雜非晶碳。 29·如請求項28之方法，其中在該特 城上形成的該光罩材料 包括未捧雜领的非晶碳。 30·如請求項29之方法，其中該光罩姑 疋旱材枓在未摻雜硼的非晶 碳上形成。 31. 一對相鄰特徵上 對相隔異向性姓 如請求項28之方法，其中該光罩材料在 形成，該實質異向性蝕刻係有效形成一 刻側壁間隔物。 32·如請求項31之方法，其中， 使用具有最小開Π尺寸的光罩由微影㈣處理形成該等 相鄰特徵；該最小開口尺寸為該光罩方法之前及之後任何 及所有半導體基板的微影蝕刻處理使用的最小開口尺寸； 及 該等相鄰異向性蝕刻側壁間隔物相隔一最短距離，該最 短距離小於該最小開口尺寸。 33·如請求項28之方法，其中該光罩材料主要由硼摻雜非晶 碳組成。 34·如請求項28之方法，其中該CVD為電漿增強。 3 5 ·如請求項28之方法，其中該CVD未電漿增強。 36·如請求項28之方法，其中硼摻雜在該CVD中發生。 37. 如請求項28之方法，其中硼摻雜在該CVD後發生。 38。 如請求項28之方法，其中該化學汽相沉積使用c2H6、 95476.doc 200529293 C2H4、C2H2、C3H6& C3H8之至少一者；及使用 b2h6、b4Hiq 及bh3co之至少一者。 39.如請求項28之方法，其中該特徵側壁係實質上垂直該基 板0 40.如請求項28之方法，其中該基板使用包括間隔物的該硼 摻雜非晶碳作為光罩之該處理包括蝕刻該基板。 札如請求項28之方法，其中該基板使用包括間隔物的石朋摻 雜非晶碳作為光罩之該處理包括離子植入該基板。 明求項28之方法，其中該基板使用包括間隔物的硼摻 雜非晶碳作為光罩之該處理包括於該基板上沉積。 43·如:求項28之方法，進一步包括在該基板之該處理後， 自該基板颠刻該特徵。 士明求項43之方法’其中自該基板蝕刻包括間隔物的硼 摻雜非晶碳之後，自該基板㈣該特徵。 95476.doc
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US7470606B2 (en) 2008-12-30
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