TW200502986A - Semiconductor memory device, semiconductor device, and portable electronic apparatus - Google Patents
Semiconductor memory device, semiconductor device, and portable electronic apparatusInfo
- Publication number
- TW200502986A TW200502986A TW093109549A TW93109549A TW200502986A TW 200502986 A TW200502986 A TW 200502986A TW 093109549 A TW093109549 A TW 093109549A TW 93109549 A TW93109549 A TW 93109549A TW 200502986 A TW200502986 A TW 200502986A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor
- channel region
- gate electrode
- portable electronic
- electronic apparatus
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 238000009792 diffusion process Methods 0.000 abstract 1
- 230000006870 function Effects 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7887—Programmable transistors with more than two possible different levels of programmation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7923—Programmable transistors with more than two possible different levels of programmation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003136354A JP2004342767A (ja) | 2003-05-14 | 2003-05-14 | 半導体記憶装置及び半導体装置、並びに携帯電子機器 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200502986A true TW200502986A (en) | 2005-01-16 |
TWI248087B TWI248087B (en) | 2006-01-21 |
Family
ID=33410740
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093109549A TWI248087B (en) | 2003-05-14 | 2004-04-07 | Semiconductor memory device, semiconductor device, and portable electronic apparatus |
Country Status (5)
Country | Link |
---|---|
US (1) | US7238984B2 (zh) |
JP (1) | JP2004342767A (zh) |
KR (1) | KR100615895B1 (zh) |
CN (1) | CN100431156C (zh) |
TW (1) | TWI248087B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI382530B (zh) * | 2009-04-03 | 2013-01-11 | Acer Inc | A method and device for utilizing thin film transistor as nonvolatile memory |
TWI471982B (zh) * | 2011-12-14 | 2015-02-01 | Nanya Technology Corp | 能降低鄰近字元線或鄰近電晶體影響之半導體元件及其製作方法 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7369438B2 (en) * | 2004-12-28 | 2008-05-06 | Aplus Flash Technology, Inc. | Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications |
JP2007103424A (ja) * | 2005-09-30 | 2007-04-19 | Oki Electric Ind Co Ltd | メモリセル及びそのメモリセルを有する半導体不揮発性メモリの構造。 |
US20070291526A1 (en) * | 2006-06-15 | 2007-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure for a non-volatile memory device |
KR100956601B1 (ko) * | 2008-03-25 | 2010-05-11 | 주식회사 하이닉스반도체 | 반도체 소자의 수직 채널 트랜지스터 및 그 형성 방법 |
JP5452146B2 (ja) * | 2009-09-17 | 2014-03-26 | セイコーインスツル株式会社 | 半導体装置 |
CN102473682B (zh) * | 2009-09-25 | 2014-06-18 | 株式会社东芝 | 非易失性半导体存储器 |
KR101152446B1 (ko) * | 2010-12-08 | 2012-06-01 | 한양대학교 산학협력단 | 프린징 효과 및 정전차폐를 이용하는 플래시 메모리 |
KR101198253B1 (ko) * | 2010-12-30 | 2012-11-07 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
US20120241710A1 (en) | 2011-03-21 | 2012-09-27 | Nanyang Technological University | Fabrication of RRAM Cell Using CMOS Compatible Processes |
JP2013077603A (ja) | 2011-09-29 | 2013-04-25 | Toshiba Corp | メモリ装置 |
CN103165614B (zh) * | 2011-12-13 | 2015-09-23 | 无锡华润上华科技有限公司 | 一种otp存储单元及其制作方法 |
US8698118B2 (en) * | 2012-02-29 | 2014-04-15 | Globalfoundries Singapore Pte Ltd | Compact RRAM device and methods of making same |
US9276041B2 (en) | 2012-03-19 | 2016-03-01 | Globalfoundries Singapore Pte Ltd | Three dimensional RRAM device, and methods of making same |
US9484072B1 (en) | 2015-10-06 | 2016-11-01 | Nscore, Inc. | MIS transistors configured to be placed in programmed state and erased state |
US9966141B2 (en) | 2016-02-19 | 2018-05-08 | Nscore, Inc. | Nonvolatile memory cell employing hot carrier effect for data storage |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63204770A (ja) * | 1987-02-20 | 1988-08-24 | Oki Electric Ind Co Ltd | 半導体記憶装置及びその製造方法 |
JPS63237580A (ja) * | 1987-03-26 | 1988-10-04 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2522853B2 (ja) * | 1990-06-29 | 1996-08-07 | シャープ株式会社 | 半導体記憶装置の製造方法 |
JPH05299616A (ja) * | 1992-04-16 | 1993-11-12 | Hitachi Ltd | 半導体記憶装置 |
JPH05304277A (ja) | 1992-04-28 | 1993-11-16 | Rohm Co Ltd | 半導体装置の製法 |
US5424979A (en) * | 1992-10-02 | 1995-06-13 | Matsushita Electric Industrial Co., Ltd. | Non-volatile memory cell |
US5408115A (en) | 1994-04-04 | 1995-04-18 | Motorola Inc. | Self-aligned, split-gate EEPROM device |
US5838041A (en) * | 1995-10-02 | 1998-11-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having memory cell transistor provided with offset region acting as a charge carrier injecting region |
JPH09116119A (ja) | 1995-10-13 | 1997-05-02 | Sony Corp | 不揮発性半導体記憶装置 |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
JPH11289059A (ja) * | 1998-04-06 | 1999-10-19 | Hitachi Ltd | 半導体集積回路装置の製造方法および半導体集積回路装置 |
JPH11354748A (ja) * | 1998-06-12 | 1999-12-24 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
TW488064B (en) * | 1999-03-08 | 2002-05-21 | Toshiba Corp | Nonvolatile semiconductor device and manufacturing method, nonvolatile semiconductor memory device and manufacturing method, and semiconductor memory device mixed with nonvolatile and volatile semiconductor memory devices and manufacturing method |
JP3973819B2 (ja) * | 1999-03-08 | 2007-09-12 | 株式会社東芝 | 半導体記憶装置およびその製造方法 |
JP4899241B2 (ja) | 1999-12-06 | 2012-03-21 | ソニー株式会社 | 不揮発性半導体記憶装置およびその動作方法 |
US6417049B1 (en) * | 2000-02-01 | 2002-07-09 | Taiwan Semiconductor Manufacturing Company | Split gate flash cell for multiple storage |
JP3930256B2 (ja) * | 2001-02-07 | 2007-06-13 | スパンション エルエルシー | 半導体装置及びその製造方法 |
US7352024B2 (en) * | 2001-02-22 | 2008-04-01 | Sharp Kabushiki Kaisha | Semiconductor storage device and semiconductor integrated circuit |
US6681287B2 (en) * | 2001-07-02 | 2004-01-20 | Nanoamp Solutions, Inc. | Smart memory |
JP3880818B2 (ja) * | 2001-08-30 | 2007-02-14 | シャープ株式会社 | メモリ膜、メモリ素子、半導体記憶装置、半導体集積回路および携帯電子機器 |
EP1300888B1 (en) * | 2001-10-08 | 2013-03-13 | STMicroelectronics Srl | Process for manufacturing a dual charge storage location memory cell |
JP2003282744A (ja) | 2002-03-22 | 2003-10-03 | Seiko Epson Corp | 不揮発性記憶装置 |
US6774640B2 (en) * | 2002-08-20 | 2004-08-10 | St Assembly Test Services Pte Ltd. | Test coupon pattern design to control multilayer saw singulated plastic ball grid array substrate mis-registration |
KR100505108B1 (ko) * | 2003-02-12 | 2005-07-29 | 삼성전자주식회사 | 소노스 기억셀 및 그 제조방법 |
-
2003
- 2003-05-14 JP JP2003136354A patent/JP2004342767A/ja active Pending
-
2004
- 2004-04-07 TW TW093109549A patent/TWI248087B/zh not_active IP Right Cessation
- 2004-04-19 US US10/826,612 patent/US7238984B2/en not_active Expired - Fee Related
- 2004-05-12 KR KR1020040033308A patent/KR100615895B1/ko not_active IP Right Cessation
- 2004-05-14 CN CNB2004100432209A patent/CN100431156C/zh not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI382530B (zh) * | 2009-04-03 | 2013-01-11 | Acer Inc | A method and device for utilizing thin film transistor as nonvolatile memory |
TWI471982B (zh) * | 2011-12-14 | 2015-02-01 | Nanya Technology Corp | 能降低鄰近字元線或鄰近電晶體影響之半導體元件及其製作方法 |
US9024377B2 (en) | 2011-12-14 | 2015-05-05 | Nanya Technology Corp. | Semiconductor device capable of reducing influences of adjacent word lines or adjacent transistors and fabricating method thereof |
US9214571B2 (en) | 2011-12-14 | 2015-12-15 | Nanya Technology Corp. | Semiconductor device capable of reducing influences of adjacent word lines or adjacent transistors and fabricating method thereof |
Also Published As
Publication number | Publication date |
---|---|
JP2004342767A (ja) | 2004-12-02 |
KR100615895B1 (ko) | 2006-08-28 |
CN100431156C (zh) | 2008-11-05 |
US20040228200A1 (en) | 2004-11-18 |
CN1551362A (zh) | 2004-12-01 |
US7238984B2 (en) | 2007-07-03 |
TWI248087B (en) | 2006-01-21 |
KR20040098547A (ko) | 2004-11-20 |
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