JP2013077603A - メモリ装置 - Google Patents
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- JP2013077603A JP2013077603A JP2011215016A JP2011215016A JP2013077603A JP 2013077603 A JP2013077603 A JP 2013077603A JP 2011215016 A JP2011215016 A JP 2011215016A JP 2011215016 A JP2011215016 A JP 2011215016A JP 2013077603 A JP2013077603 A JP 2013077603A
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 83
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- 238000010586 diagram Methods 0.000 description 11
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 239000011370 conductive nanoparticle Substances 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 8
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- SDGKUVSVPIIUCF-UHFFFAOYSA-N 2,6-dimethylpiperidine Chemical compound CC1CCCC(C)N1 SDGKUVSVPIIUCF-UHFFFAOYSA-N 0.000 description 2
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- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/122—Single quantum well structures
- H01L29/127—Quantum box structures
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
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- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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Abstract
【解決手段】微結晶である第1の導電性微粒子を含む微結晶層22と、微結晶層22を挟むトンネル絶縁膜21、23とを有する第1の二重トンネル接合構造と、微結晶である第2の導電性微粒子を含む微結晶層26と、微結晶層26を挟むトンネル絶縁膜25、27とを有する第2の二重トンネル接合構造と、第1の二重トンネル接合構造と第2の二重トンネル接合構造との間に配置され、情報電荷を蓄積する電荷蓄積層と、第1の二重トンネル接合構造、電荷蓄積層、及び第2の二重トンネル接合構造を挟む第1、第2の導電層とを備える。第1の導電性微粒子の平均粒径は、第2の導電性微粒子の平均粒径と異なっている。
【選択図】図1
Description
まず、第1実施形態のメモリ装置について説明する。
図1は、第1実施形態のメモリ装置の構造を示す断面図である。
次に、第1実施形態のメモリ装置の製造方法を説明する。
第1実施形態では、シリコン微結晶(シリコン微粒子)は粒径が3nm以下と小さいため、電子1個の充電エネルギーは熱揺らぎよりも十分大きいというクーロンブロッケイド条件を満たしている。よって、シリコン微粒子中に1個の電子が帯電する時、クーロンブロッケイド効果と量子閉じ込め効果によりシリコン微粒子に高いエネルギー状態が形成され、電子がシリコン微粒子を通り抜けるときエネルギー障壁ができることになる。
第1実施形態では上下の配線20,28の材料としてn+ポリシリコンを用いたが、他の導電性材料(例えば、金属または半導体)を用いてもよい。特に、配線20,28の材料として金属が用いられることは低抵抗化の観点から望ましい。この場合、金属の仕事関数はシリコンの電子親和力よりも大きいため、配線からの電子のエネルギー位置が変化する。第2実施形態では、上下の配線が金属で形成された例を説明する。
第1実施形態では、書き込み時の貫通電流を抑止するために、“ΔE>3×ΔE2”の関係を満たすことが望ましい。よって、エネルギー障壁ΔE2がΔEよりもかなり低くなければならないため、図11に示すように、下側の配線20と情報電荷の蓄積部である微結晶層24との間のリークが十分抑制できず、記憶保持が不十分である場合がある。解決策として、“ΔE>3×ΔE2”を満たしながらΔE2を大きくすることがあげられるが、この場合ΔEを著しく大きくする必要があり、微結晶層26が含む微粒子に対して難度の高い極微小な粒径制御が要求される。そこで、第3実施形態では、書き込み時の貫通電流を抑制する条件、“ΔE>3×ΔE2”を緩和する構造を提案する。
前記第1〜第3実施形態では、情報電荷を蓄積する層にシリコンの微結晶層24を用いたが、情報電荷が蓄積可能なもので、かつ消去状態の読み出し時に弾道電子がエネルギー緩和して誤書き込みされなければ、他の材料を用いてもよい。この場合でも、第1〜第3実施形態で説明したのと同様な効果を有する。以下の第4〜第6実施形態に、第1実施形態におけるシリコンの微結晶層24に換えて、電荷蓄積層として他の材料を用いた例を説明する。
図19は、第5実施形態のメモリ装置の構造を示す断面図である。
図20は、第6実施形態のメモリ装置の構造を示す断面図である。
図21は、第7実施形態のメモリ装置の構造を示す断面図である。
次に、第1〜第7実施形態のメモリ装置をメモリセルとして備えるクロスポイント型メモリについて説明する。
Claims (5)
- 微結晶である第1の導電性微粒子を含む第1の微結晶層と、前記第1の微結晶層を挟む第1、第2のトンネル絶縁膜とを有する第1の二重トンネル接合構造と、
微結晶である第2の導電性微粒子を含む第2の微結晶層と、前記第2の微結晶層を挟む第3、第4のトンネル絶縁膜とを有する第2の二重トンネル接合構造と、
前記第1の二重トンネル接合構造と前記第2の二重トンネル接合構造との間に配置され、情報電荷を蓄積する電荷蓄積層と、
前記第1の二重トンネル接合構造、前記電荷蓄積層、及び前記第2の二重トンネル接合構造を挟む第1、第2の導電層と、
を具備し、
前記第1の導電性微粒子の平均粒径は、前記第2の導電性微粒子の平均粒径と異なっていることを特徴とするメモリ装置。 - 前記電荷蓄積層は、前記第1、第2の導電性微粒子の平均粒径よりも大きな平均粒径を持つ第3の導電性微粒子を含むことを特徴とする請求項1に記載のメモリ装置。
- 前記第1、第2の導電性微粒子は、クーロンブロッケイド条件を満たすことを特徴とする請求項1または2に記載のメモリ装置。
- 前記第1、第2の導電性微粒子は、Si微結晶であることを特徴とする請求項1乃至3のいずれかに記載のメモリ装置。
- 前記第1の二重トンネル接合構造と前記第1の導電層との間に配置された第4の導電性微粒子を含む第4の微結晶層をさらに具備し、
前記第4の導電性微粒子は、前記第1の導電性微粒子の平均粒径よりも大きな平均粒径を持つことを特徴とする請求項1乃至4のいずれかに記載のメモリ装置。
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US8969843B2 (en) | 2013-02-21 | 2015-03-03 | Kabushiki Kaisha Toshiba | Memory device |
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US9721654B1 (en) | 2016-03-18 | 2017-08-01 | Kabushiki Kaisha Toshiba | Memory device |
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