SU1561834A3 - Устройство адресации к пам ти - Google Patents

Устройство адресации к пам ти Download PDF

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Publication number
SU1561834A3
SU1561834A3 SU874202747A SU4202747A SU1561834A3 SU 1561834 A3 SU1561834 A3 SU 1561834A3 SU 874202747 A SU874202747 A SU 874202747A SU 4202747 A SU4202747 A SU 4202747A SU 1561834 A3 SU1561834 A3 SU 1561834A3
Authority
SU
USSR - Soviet Union
Prior art keywords
address
group
counter
inputs
memory
Prior art date
Application number
SU874202747A
Other languages
English (en)
Russian (ru)
Inventor
Екота Харуо
Original Assignee
Япония, Представленная Генеральным Директором Агентства Промышленных Наук И Технологии (Фирма)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by Япония, Представленная Генеральным Директором Агентства Промышленных Наук И Технологии (Фирма) filed Critical Япония, Представленная Генеральным Директором Агентства Промышленных Наук И Технологии (Фирма)
Application granted granted Critical
Publication of SU1561834A3 publication Critical patent/SU1561834A3/ru

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
SU874202747A 1985-10-15 1987-06-12 Устройство адресации к пам ти SU1561834A3 (ru)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60229537A JPS6289149A (ja) 1985-10-15 1985-10-15 多ポ−トメモリシステム

Publications (1)

Publication Number Publication Date
SU1561834A3 true SU1561834A3 (ru) 1990-04-30

Family

ID=16893724

Family Applications (1)

Application Number Title Priority Date Filing Date
SU874202747A SU1561834A3 (ru) 1985-10-15 1987-06-12 Устройство адресации к пам ти

Country Status (7)

Country Link
US (1) US4930066A (enExample)
EP (1) EP0248906B1 (enExample)
JP (1) JPS6289149A (enExample)
KR (1) KR880700354A (enExample)
DE (1) DE3688505T2 (enExample)
SU (1) SU1561834A3 (enExample)
WO (1) WO1987002488A1 (enExample)

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US8677105B2 (en) 2006-11-14 2014-03-18 Soft Machines, Inc. Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines
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Also Published As

Publication number Publication date
JPH042976B2 (enExample) 1992-01-21
KR880700354A (ko) 1988-02-22
DE3688505T2 (de) 1993-09-09
WO1987002488A1 (fr) 1987-04-23
EP0248906A4 (en) 1989-08-22
EP0248906A1 (en) 1987-12-16
DE3688505D1 (de) 1993-07-01
EP0248906B1 (en) 1993-05-26
US4930066A (en) 1990-05-29
JPS6289149A (ja) 1987-04-23

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