DE3688505D1 - Multiportspeichersystem. - Google Patents

Multiportspeichersystem.

Info

Publication number
DE3688505D1
DE3688505D1 DE8686902020T DE3688505T DE3688505D1 DE 3688505 D1 DE3688505 D1 DE 3688505D1 DE 8686902020 T DE8686902020 T DE 8686902020T DE 3688505 T DE3688505 T DE 3688505T DE 3688505 D1 DE3688505 D1 DE 3688505D1
Authority
DE
Germany
Prior art keywords
storage system
multiport storage
multiport
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686902020T
Other languages
English (en)
Other versions
DE3688505T2 (de
Inventor
Haruo Yokota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Publication of DE3688505D1 publication Critical patent/DE3688505D1/de
Application granted granted Critical
Publication of DE3688505T2 publication Critical patent/DE3688505T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Dram (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE8686902020T 1985-10-15 1986-03-24 Multiportspeichersystem. Expired - Fee Related DE3688505T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60229537A JPS6289149A (ja) 1985-10-15 1985-10-15 多ポ−トメモリシステム
PCT/JP1986/000136 WO1987002488A1 (en) 1985-10-15 1986-03-24 Multi-port memory system

Publications (2)

Publication Number Publication Date
DE3688505D1 true DE3688505D1 (de) 1993-07-01
DE3688505T2 DE3688505T2 (de) 1993-09-09

Family

ID=16893724

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686902020T Expired - Fee Related DE3688505T2 (de) 1985-10-15 1986-03-24 Multiportspeichersystem.

Country Status (7)

Country Link
US (1) US4930066A (de)
EP (1) EP0248906B1 (de)
JP (1) JPS6289149A (de)
KR (1) KR880700354A (de)
DE (1) DE3688505T2 (de)
SU (1) SU1561834A3 (de)
WO (1) WO1987002488A1 (de)

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JPH07107792B2 (ja) * 1988-01-19 1995-11-15 株式会社東芝 マルチポートメモリ
US5146581A (en) * 1988-02-24 1992-09-08 Sanyo Electric Co., Ltd. Subprogram executing data processing system having bank switching control storing in the same address area in each of memory banks
US5247649A (en) * 1988-05-06 1993-09-21 Hitachi, Ltd. Multi-processor system having a multi-port cache memory
JP2872251B2 (ja) * 1988-10-12 1999-03-17 株式会社日立製作所 情報処理システム
US5043874A (en) * 1989-02-03 1991-08-27 Digital Equipment Corporation Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory
JP2673390B2 (ja) * 1991-03-13 1997-11-05 三菱電機株式会社 マルチポートメモリ
JPH08501647A (ja) * 1992-09-21 1996-02-20 ユニシス・コーポレイション ディスクドライブ複合のためのマルチポートバッファメモリシステム
US5337414A (en) * 1992-09-22 1994-08-09 Unisys Corporation Mass data storage and retrieval system
WO1996007139A1 (en) * 1994-09-01 1996-03-07 Mcalpine Gary L A multi-port memory system including read and write buffer interfaces
KR960042372A (ko) * 1995-05-10 1996-12-21 가나이 쯔또무 멀티채널 메모리시스템, 전송정보 동기화방법 및 신호전송회로
WO1997011419A2 (en) * 1995-09-08 1997-03-27 Shablamm Computer, Inc. Synchronous multi-port random access memory
US5717646A (en) * 1996-12-05 1998-02-10 Kyi; Ben-I Random access multiport memory capable of simultaneously accessing memory cells from a plurality of interface ports
US6108756A (en) * 1997-01-17 2000-08-22 Integrated Device Technology, Inc. Semaphore enhancement to allow bank selection of a shared resource memory device
US6212607B1 (en) 1997-01-17 2001-04-03 Integrated Device Technology, Inc. Multi-ported memory architecture using single-ported RAM
US5978889A (en) * 1997-11-05 1999-11-02 Timeplex, Inc. Multiple device data transfer utilizing a multiport memory with opposite oriented memory page rotation for transmission and reception
US6874013B2 (en) 1999-05-24 2005-03-29 Koninklijke Philips Electronics N.V. Data processing arrangement and memory system
DE19937176A1 (de) * 1999-08-06 2001-02-15 Siemens Ag Multiprozessor-System
JP2002007201A (ja) * 2000-06-21 2002-01-11 Nec Corp メモリシステム、メモリインターフェース及びメモリチップ
US7143185B1 (en) * 2000-08-29 2006-11-28 Advanced Micro Devices, Inc. Method and apparatus for accessing external memories
JP2002109885A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体記憶装置
US7380085B2 (en) * 2001-11-14 2008-05-27 Intel Corporation Memory adapted to provide dedicated and or shared memory to multiple processors and method therefor
US6895488B2 (en) * 2002-05-22 2005-05-17 Lsi Logic Corporation DSP memory bank rotation
US7747833B2 (en) 2005-09-30 2010-06-29 Mosaid Technologies Incorporated Independent link and bank selection
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
WO2007036050A1 (en) 2005-09-30 2007-04-05 Mosaid Technologies Incorporated Memory with output control
US20070130374A1 (en) * 2005-11-15 2007-06-07 Intel Corporation Multiported memory with configurable ports
EP2011018B1 (de) 2006-04-12 2016-07-13 Soft Machines, Inc. Vorrichtung und verfahren zur verarbeitung einer instruktionsmatrix zur definition paralleler und abhängiger operationen
US8059128B1 (en) * 2006-04-19 2011-11-15 Nvidia Corporation Apparatus and method for performing blit operations across parallel processors
CN101558649A (zh) * 2006-09-26 2009-10-14 皇家飞利浦电子股份有限公司 具有多个存储体的数据处理
EP2527972A3 (de) 2006-11-14 2014-08-06 Soft Machines, Inc. Vorrichtung und Verfahren zum Verarbeiten von komplexen Anweisungsformaten in einer Multi-Thread-Architektur, die verschiedene Kontextschaltungsmodi und Visualisierungsschemen unterstützt
US20080170571A1 (en) * 2007-01-12 2008-07-17 Utstarcom, Inc. Method and System for Synchronous Page Addressing in a Data Packet Switch
US8250312B2 (en) * 2009-04-29 2012-08-21 Micron Technology, Inc. Configurable multi-port memory devices and methods
WO2012037491A2 (en) 2010-09-17 2012-03-22 Soft Machines, Inc. Single cycle multi-branch prediction including shadow cache for early far branch prediction
EP2689326B1 (de) 2011-03-25 2022-11-16 Intel Corporation Speicherfragmente zur unterstützung einer codeblockausführung mittels durch partitionierbare engines realisierter virtueller kerne
CN108376097B (zh) 2011-03-25 2022-04-15 英特尔公司 用于通过使用由可分割引擎实例化的虚拟核来支持代码块执行的寄存器文件段
TWI533129B (zh) 2011-03-25 2016-05-11 軟體機器公司 使用可分割引擎實體化的虛擬核心執行指令序列程式碼區塊
EP2710480B1 (de) 2011-05-20 2018-06-20 Intel Corporation Verbindungsstruktur zur unterstützung der ausführung von instruktionssequenzen durch mehrere maschinen
TWI666551B (zh) 2011-05-20 2019-07-21 美商英特爾股份有限公司 以複數個引擎作資源與互連結構的分散式分配以支援指令序列的執行
US8954700B2 (en) * 2011-08-02 2015-02-10 Cavium, Inc. Method and apparatus for managing processing thread migration between clusters within a processor
CN104040491B (zh) 2011-11-22 2018-06-12 英特尔公司 微处理器加速的代码优化器
IN2014CN03678A (de) 2011-11-22 2015-09-25 Soft Machines Inc
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
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WO2014151043A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US9760481B2 (en) 2014-06-13 2017-09-12 Sandisk Technologies Llc Multiport memory

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JPS5128450B2 (de) * 1971-10-06 1976-08-19
US3883854A (en) * 1973-11-30 1975-05-13 Ibm Interleaved memory control signal and data handling apparatus using pipelining techniques
JPS5148937A (en) * 1974-10-25 1976-04-27 Fujitsu Ltd Kiokusochi niokeru junjoseigyohoshiki
US4158227A (en) * 1977-10-12 1979-06-12 Bunker Ramo Corporation Paged memory mapping with elimination of recurrent decoding
US4285039A (en) * 1978-03-28 1981-08-18 Motorola, Inc. Memory array selection mechanism
US4254463A (en) * 1978-12-14 1981-03-03 Rockwell International Corporation Data processing system with address translation
US4707781A (en) * 1979-01-09 1987-11-17 Chopp Computer Corp. Shared memory computer method and apparatus
US4652993A (en) * 1984-04-02 1987-03-24 Sperry Corporation Multiple output port memory storage module
US4710868A (en) * 1984-06-29 1987-12-01 International Business Machines Corporation Interconnect scheme for shared memory local networks

Also Published As

Publication number Publication date
JPS6289149A (ja) 1987-04-23
US4930066A (en) 1990-05-29
EP0248906A1 (de) 1987-12-16
WO1987002488A1 (en) 1987-04-23
JPH042976B2 (de) 1992-01-21
EP0248906B1 (de) 1993-05-26
DE3688505T2 (de) 1993-09-09
KR880700354A (ko) 1988-02-22
EP0248906A4 (de) 1989-08-22
SU1561834A3 (ru) 1990-04-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee