SG70600A1 - Semiconductor element-mounting board manufacturing method for the board semiconductor device and manufacturing method for the device - Google Patents

Semiconductor element-mounting board manufacturing method for the board semiconductor device and manufacturing method for the device

Info

Publication number
SG70600A1
SG70600A1 SG1997002417A SG1997002417A SG70600A1 SG 70600 A1 SG70600 A1 SG 70600A1 SG 1997002417 A SG1997002417 A SG 1997002417A SG 1997002417 A SG1997002417 A SG 1997002417A SG 70600 A1 SG70600 A1 SG 70600A1
Authority
SG
Singapore
Prior art keywords
manufacturing
board
base member
semiconductor
semiconductor element
Prior art date
Application number
SG1997002417A
Other languages
English (en)
Inventor
Takaaki Higashida
Koichi Kumagai
Takahiro Matsuo
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of SG70600A1 publication Critical patent/SG70600A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128Assembling formed circuit to base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49156Manufacturing circuit on or in base with selective destruction of conductive paths
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49158Manufacturing circuit on or in base with molding of insulated base

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
SG1997002417A 1996-07-09 1997-07-09 Semiconductor element-mounting board manufacturing method for the board semiconductor device and manufacturing method for the device SG70600A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17903196A JP3420435B2 (ja) 1996-07-09 1996-07-09 基板の製造方法、半導体装置及び半導体装置の製造方法

Publications (1)

Publication Number Publication Date
SG70600A1 true SG70600A1 (en) 2000-02-22

Family

ID=16058909

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1997002417A SG70600A1 (en) 1996-07-09 1997-07-09 Semiconductor element-mounting board manufacturing method for the board semiconductor device and manufacturing method for the device

Country Status (5)

Country Link
US (3) US6265673B1 (ko)
JP (1) JP3420435B2 (ko)
KR (2) KR100284781B1 (ko)
CN (1) CN1160779C (ko)
SG (1) SG70600A1 (ko)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303878B1 (en) * 1997-07-24 2001-10-16 Denso Corporation Mounting structure of electronic component on substrate board
US6854985B1 (en) 1998-12-16 2005-02-15 Paricon Technologies Corporation Elastomeric interconnection device and methods for making same
US6802720B2 (en) * 1999-12-16 2004-10-12 Paricon Technologies Corporation Pin-array, separable, compliant electrical contact member
US6670558B2 (en) * 1999-12-29 2003-12-30 Intel Corporation Inline and “Y” input-output bus topology
JP3427086B2 (ja) * 2000-02-23 2003-07-14 Necエレクトロニクス株式会社 Icソケット
US6590283B1 (en) * 2000-02-28 2003-07-08 Agere Systems Inc. Method for hermetic leadless device interconnect using a submount
JP4023076B2 (ja) * 2000-07-27 2007-12-19 富士通株式会社 表裏導通基板及びその製造方法
KR100668939B1 (ko) * 2000-08-21 2007-01-12 앰코 테크놀로지 코리아 주식회사 보드 레벨 반도체 장치 및 그 제조 방법
KR20020028017A (ko) * 2000-10-06 2002-04-15 박종섭 고밀도 패키지
JP4744689B2 (ja) * 2000-12-11 2011-08-10 パナソニック株式会社 粘性流体転写装置及び電子部品実装装置
US6951980B2 (en) 2001-09-29 2005-10-04 Texas Instruments Incorporated Package for an electrical device
US7249954B2 (en) 2002-02-26 2007-07-31 Paricon Technologies Corporation Separable electrical interconnect with anisotropic conductive elastomer for translating footprint
JP4253475B2 (ja) * 2002-07-04 2009-04-15 パイオニア株式会社 発光素子駆動用半導体装置
DE10343255B4 (de) * 2003-09-17 2006-10-12 Infineon Technologies Ag Verfahren zum Herstellen elektrischer Verbindungen zwischen einem Halbleiterchip in einem BGA-Gehäuse und einer Leiterplatte
US7759949B2 (en) 2004-05-21 2010-07-20 Microprobe, Inc. Probes with self-cleaning blunt skates for contacting conductive pads
US9097740B2 (en) * 2004-05-21 2015-08-04 Formfactor, Inc. Layered probes with core
USRE43503E1 (en) 2006-06-29 2012-07-10 Microprobe, Inc. Probe skates for electrical testing of convex pad topologies
US9476911B2 (en) 2004-05-21 2016-10-25 Microprobe, Inc. Probes with high current carrying capability and laser machining methods
US8988091B2 (en) 2004-05-21 2015-03-24 Microprobe, Inc. Multiple contact probes
US7615476B2 (en) 2005-06-30 2009-11-10 Intel Corporation Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages
US7649367B2 (en) 2005-12-07 2010-01-19 Microprobe, Inc. Low profile probe having improved mechanical scrub and reduced contact inductance
US7312617B2 (en) 2006-03-20 2007-12-25 Microprobe, Inc. Space transformers employing wire bonds for interconnections with fine pitch contacts
US7452217B2 (en) * 2006-06-22 2008-11-18 Sankyo Kasei Co., Ltd. Connecting member for surface mounting circuit
US7520761B2 (en) * 2006-07-17 2009-04-21 Paricon Technologies Separable electrical interconnect with anisotropic conductive elastomer and adaptor with channel for engaging a frame
US8907689B2 (en) 2006-10-11 2014-12-09 Microprobe, Inc. Probe retention arrangement
US7514948B2 (en) 2007-04-10 2009-04-07 Microprobe, Inc. Vertical probe array arranged to provide space transformation
US7498198B2 (en) * 2007-04-30 2009-03-03 International Business Machines Corporation Structure and method for stress reduction in flip chip microelectronic packages using underfill materials with spatially varying properties
US8723546B2 (en) * 2007-10-19 2014-05-13 Microprobe, Inc. Vertical guided layered probe
JP2009212104A (ja) * 2008-02-29 2009-09-17 Toshiba Corp プリント回路板の製造方法、プリント回路板およびそのプリント回路板を備えた電子機器
US8230593B2 (en) * 2008-05-29 2012-07-31 Microprobe, Inc. Probe bonding method having improved control of bonding material
JP5511155B2 (ja) * 2008-06-25 2014-06-04 パナソニック株式会社 インターポーザ基板とその製造方法
EP2192825A1 (en) * 2008-11-26 2010-06-02 Osram Gesellschaft mit Beschränkter Haftung An injection tool for encapsulating electronic circuits with light sources, and related encapsulation process
US20120286416A1 (en) * 2011-05-11 2012-11-15 Tessera Research Llc Semiconductor chip package assembly and method for making same
US9241405B2 (en) * 2012-03-06 2016-01-19 Texas Instruments Incorporated Interposer with extruded feed-through vias
JP6383138B2 (ja) * 2013-02-25 2018-08-29 セイコーインスツル株式会社 電子デバイス
KR101478759B1 (ko) * 2013-04-30 2015-01-05 주식회사 세미콘라이트 기판 프레임 제조 방법 및 이를 포함하는 반도체 소자 제조 방법
CN103996627A (zh) * 2013-12-05 2014-08-20 申宇慈 制造含有图形阵列通孔的基板的方法和金属线集成体
CN104183545B (zh) * 2014-07-14 2017-05-17 申宇慈 制造导线框架体的方法和导线框架体
KR20160095487A (ko) * 2015-02-03 2016-08-11 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US9947634B1 (en) * 2017-06-13 2018-04-17 Northrop Grumman Systems Corporation Robust mezzanine BGA connector
CN113285330A (zh) * 2021-04-02 2021-08-20 昆仑伟思微电子(珠海)有限公司 一种同轴转接板的制作方法
EP4099807A1 (en) * 2021-06-01 2022-12-07 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier interconnection and manufacturing method

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1387587A (en) * 1971-07-22 1975-03-19 Plessey Co Ltd Electrical interconnectors and connector assemblies
US4202007A (en) * 1978-06-23 1980-05-06 International Business Machines Corporation Multi-layer dielectric planar structure having an internal conductor pattern characterized with opposite terminations disposed at a common edge surface of the layers
US4616406A (en) * 1984-09-27 1986-10-14 Advanced Micro Devices, Inc. Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit layers therein
JPS61237458A (ja) * 1985-04-15 1986-10-22 Hitachi Ltd 樹脂封止型半導体装置
US4778950A (en) * 1985-07-22 1988-10-18 Digital Equipment Corporation Anisotropic elastomeric interconnecting system
JPS62136865A (ja) * 1985-12-11 1987-06-19 Hitachi Ltd モジユ−ル実装構造
US4926241A (en) * 1988-02-19 1990-05-15 Microelectronics And Computer Technology Corporation Flip substrate for chip mount
US5036431A (en) * 1988-03-03 1991-07-30 Ibiden Co., Ltd. Package for surface mounted components
JPH0211375A (ja) 1988-06-30 1990-01-16 Canon Inc 記録装置
US4916523A (en) * 1988-09-19 1990-04-10 Advanced Micro Devices, Inc. Electrical connections via unidirectional conductive elastomer for pin carrier outside lead bond
CA2071549C (en) * 1989-12-11 2001-02-06 William L. Welch Foundation and method for preparing same
JP2536676B2 (ja) * 1990-07-30 1996-09-18 日本電気株式会社 マイクロピン集合体及びその製造方法
JPH04240759A (ja) 1991-01-24 1992-08-28 Nec Corp ピン構造体及びその製造方法
US5258648A (en) * 1991-06-27 1993-11-02 Motorola, Inc. Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery
JPH05251121A (ja) * 1991-12-18 1993-09-28 Xerox Corp 多層配線組立体
US5338208A (en) * 1992-02-04 1994-08-16 International Business Machines Corporation High density electronic connector and method of assembly
US5483421A (en) * 1992-03-09 1996-01-09 International Business Machines Corporation IC chip attachment
US5259110A (en) * 1992-04-03 1993-11-09 International Business Machines Corporation Method for forming a multilayer microelectronic wiring module
KR100335591B1 (ko) 1992-09-10 2002-08-24 텍사스 인스트루먼츠 인코포레이티드 집적회로디바이스의액티브회로영역상의와이어본딩방법및집적회로디바이스
US5535101A (en) * 1992-11-03 1996-07-09 Motorola, Inc. Leadless integrated circuit package
US5334804A (en) 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
EP0603928A1 (en) 1992-12-21 1994-06-29 Delco Electronics Corporation Hybrid circuit
JP2518508B2 (ja) * 1993-04-14 1996-07-24 日本電気株式会社 半導体装置
US5810607A (en) * 1995-09-13 1998-09-22 International Business Machines Corporation Interconnector with contact pads having enhanced durability
JP3087152B2 (ja) * 1993-09-08 2000-09-11 富士通株式会社 樹脂フィルム多層回路基板の製造方法
US5455456A (en) * 1993-09-15 1995-10-03 Lsi Logic Corporation Integrated circuit package lid
US5637176A (en) * 1994-06-16 1997-06-10 Fry's Metals, Inc. Methods for producing ordered Z-axis adhesive materials, materials so produced, and devices, incorporating such materials
US5541567A (en) * 1994-10-17 1996-07-30 International Business Machines Corporation Coaxial vias in an electronic substrate
US5477933A (en) * 1994-10-24 1995-12-26 At&T Corp. Electronic device interconnection techniques
JPH08167630A (ja) 1994-12-15 1996-06-25 Hitachi Ltd チップ接続構造
JP3132337B2 (ja) * 1995-03-24 2001-02-05 新神戸電機株式会社 液晶ディスプレイ装置

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US7036221B2 (en) 2006-05-02
US20040158979A1 (en) 2004-08-19
CN1160779C (zh) 2004-08-04
KR100284781B1 (ko) 2001-04-02
JP3420435B2 (ja) 2003-06-23
CN1182283A (zh) 1998-05-20
KR980012296A (ko) 1998-04-30
US6265673B1 (en) 2001-07-24
KR100327766B1 (ko) 2002-03-15
US20010042639A1 (en) 2001-11-22
JPH1027825A (ja) 1998-01-27

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