SG70150A1 - Method for dual gate oxide dual workfunction cmos - Google Patents
Method for dual gate oxide dual workfunction cmosInfo
- Publication number
- SG70150A1 SG70150A1 SG1999000336A SG1999000336A SG70150A1 SG 70150 A1 SG70150 A1 SG 70150A1 SG 1999000336 A SG1999000336 A SG 1999000336A SG 1999000336 A SG1999000336 A SG 1999000336A SG 70150 A1 SG70150 A1 SG 70150A1
- Authority
- SG
- Singapore
- Prior art keywords
- dual
- cmos
- gate oxide
- workfunction
- dual gate
- Prior art date
Links
- 230000009977 dual effect Effects 0.000 title 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/018,939 US6087225A (en) | 1998-02-05 | 1998-02-05 | Method for dual gate oxide dual workfunction CMOS |
Publications (1)
Publication Number | Publication Date |
---|---|
SG70150A1 true SG70150A1 (en) | 2000-01-25 |
Family
ID=21790519
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG1999000336A SG70150A1 (en) | 1998-02-05 | 1999-02-03 | Method for dual gate oxide dual workfunction cmos |
Country Status (8)
Country | Link |
---|---|
US (1) | US6087225A (zh) |
EP (1) | EP0935285A1 (zh) |
JP (1) | JP3111059B2 (zh) |
KR (1) | KR100331527B1 (zh) |
CN (1) | CN1134061C (zh) |
MY (1) | MY118598A (zh) |
SG (1) | SG70150A1 (zh) |
TW (1) | TW368734B (zh) |
Families Citing this family (73)
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JP3349937B2 (ja) * | 1997-12-22 | 2002-11-25 | 沖電気工業株式会社 | 半導体装置の製造方法 |
US6555455B1 (en) | 1998-09-03 | 2003-04-29 | Micron Technology, Inc. | Methods of passivating an oxide surface subjected to a conductive material anneal |
EP1005079B1 (en) * | 1998-11-26 | 2012-12-26 | STMicroelectronics Srl | Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry |
US6228708B1 (en) * | 1998-12-10 | 2001-05-08 | United Microelectronics Corp. | Method of manufacturing high voltage mixed-mode device |
JP2000311992A (ja) | 1999-04-26 | 2000-11-07 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
JP2001060630A (ja) * | 1999-08-23 | 2001-03-06 | Nec Corp | 半導体装置の製造方法 |
JP2001210726A (ja) * | 2000-01-24 | 2001-08-03 | Hitachi Ltd | 半導体装置及びその製造方法 |
KR100364599B1 (ko) * | 2001-02-13 | 2002-12-16 | 삼성전자 주식회사 | 반도체 소자 제조방법 |
US6297103B1 (en) * | 2000-02-28 | 2001-10-02 | Micron Technology, Inc. | Structure and method for dual gate oxide thicknesses |
US6686276B2 (en) * | 2000-03-09 | 2004-02-03 | Tower Semiconductor Ltd. | Semiconductor chip having both polycide and salicide gates and methods for making same |
FR2822293B1 (fr) * | 2001-03-13 | 2007-03-23 | Nat Inst Of Advanced Ind Scien | Transistor a effet de champ et double grille, circuit integre comportant ce transistor, et procede de fabrication de ce dernier |
US6335248B1 (en) | 2001-04-30 | 2002-01-01 | International Business Machines Corporation | Dual workfunction MOSFETs with borderless diffusion contacts for high-performance embedded DRAM technology |
US6518106B2 (en) * | 2001-05-26 | 2003-02-11 | Motorola, Inc. | Semiconductor device and a method therefor |
US6888198B1 (en) | 2001-06-04 | 2005-05-03 | Advanced Micro Devices, Inc. | Straddled gate FDSOI device |
DE10135870C1 (de) * | 2001-07-24 | 2003-02-20 | Infineon Technologies Ag | Verfahren zum Herstellen einer integrierten Halbleiterschaltung mit einem Speicher- und einem Logikbereich |
DE10137678A1 (de) * | 2001-08-01 | 2003-02-27 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleiterprodukts mit einem Speicher- und einem Logikbereich |
DE10140047B4 (de) | 2001-08-16 | 2006-05-04 | Infineon Technologies Ag | Verfahren zur Herstellung von Transistoren in integrierten Halbleiterschaltungen |
KR100449246B1 (ko) * | 2001-12-24 | 2004-09-18 | 주식회사 하이닉스반도체 | 반도체소자의 게이트전극 형성방법 |
US6664153B2 (en) * | 2002-02-08 | 2003-12-16 | Chartered Semiconductor Manufacturing Ltd. | Method to fabricate a single gate with dual work-functions |
US6709926B2 (en) * | 2002-05-31 | 2004-03-23 | International Business Machines Corporation | High performance logic and high density embedded dram with borderless contact and antispacer |
US6709932B1 (en) * | 2002-08-30 | 2004-03-23 | Texas Instruments Incorporated | Method for improving gate oxide integrity and interface quality in a multi-gate oxidation process |
US6787416B2 (en) * | 2002-09-24 | 2004-09-07 | Macronix International Co., Ltd. | Non volatile embedded memory with poly protection layer |
US6906398B2 (en) * | 2003-01-02 | 2005-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor chip with gate dielectrics for high-performance and low-leakage applications |
US6828181B2 (en) * | 2003-05-08 | 2004-12-07 | International Business Machines Corporation | Dual gate material process for CMOS technologies |
KR100956598B1 (ko) | 2003-06-30 | 2010-05-11 | 주식회사 하이닉스반도체 | 듀얼 게이트 산화막 구조의 게이트 형성방법 |
BE1015723A4 (nl) | 2003-10-17 | 2005-07-05 | Imec Inter Uni Micro Electr | Werkwijze voor het vervaardigen van halfgeleiderinrichtingen met gesilicideerde elektroden. |
US7160771B2 (en) * | 2003-11-28 | 2007-01-09 | International Business Machines Corporation | Forming gate oxides having multiple thicknesses |
US7064050B2 (en) * | 2003-11-28 | 2006-06-20 | International Business Machines Corporation | Metal carbide gate structure and method of fabrication |
US7115947B2 (en) * | 2004-03-18 | 2006-10-03 | International Business Machines Corporation | Multiple dielectric finfet structure and method |
US20060163670A1 (en) * | 2005-01-27 | 2006-07-27 | International Business Machines Corporation | Dual silicide process to improve device performance |
JP4205079B2 (ja) * | 2005-06-03 | 2009-01-07 | 株式会社東芝 | 半導体装置およびその製造方法 |
US20070007531A1 (en) * | 2005-07-08 | 2007-01-11 | Ho Kwak S | Semiconductor device and manufacturing method thereof |
JP2007096060A (ja) * | 2005-09-29 | 2007-04-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US7833849B2 (en) * | 2005-12-30 | 2010-11-16 | International Business Machines Corporation | Method of fabricating a semiconductor structure including one device region having a metal gate electrode located atop a thinned polygate electrode |
CN101483154B (zh) * | 2008-01-07 | 2010-08-25 | 中芯国际集成电路制造(上海)有限公司 | 一种双栅氧器件的栅极侧墙制造方法 |
CN101620994B (zh) * | 2008-06-30 | 2011-01-12 | 中芯国际集成电路制造(北京)有限公司 | 掺杂栅介质层、多晶硅层及叠层顶层的最小厚度确定方法 |
US8399310B2 (en) | 2010-10-29 | 2013-03-19 | Freescale Semiconductor, Inc. | Non-volatile memory and logic circuit process integration |
US8669158B2 (en) | 2012-01-04 | 2014-03-11 | Mark D. Hall | Non-volatile memory (NVM) and logic integration |
US8906764B2 (en) * | 2012-01-04 | 2014-12-09 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
US8658497B2 (en) | 2012-01-04 | 2014-02-25 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
US8951863B2 (en) | 2012-04-06 | 2015-02-10 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
US8722493B2 (en) | 2012-04-09 | 2014-05-13 | Freescale Semiconductor, Inc. | Logic transistor and non-volatile memory cell integration |
US9087913B2 (en) | 2012-04-09 | 2015-07-21 | Freescale Semiconductor, Inc. | Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic |
US8728886B2 (en) | 2012-06-08 | 2014-05-20 | Freescale Semiconductor, Inc. | Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric |
US9111865B2 (en) | 2012-10-26 | 2015-08-18 | Freescale Semiconductor, Inc. | Method of making a logic transistor and a non-volatile memory (NVM) cell |
CN103871855B (zh) * | 2012-12-17 | 2016-08-03 | 北大方正集团有限公司 | 一种集成电路双栅氧的制备方法 |
US8716089B1 (en) | 2013-03-08 | 2014-05-06 | Freescale Semiconductor, Inc. | Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage |
US8741719B1 (en) | 2013-03-08 | 2014-06-03 | Freescale Semiconductor, Inc. | Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique |
US9006093B2 (en) | 2013-06-27 | 2015-04-14 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high voltage transistor integration |
US9129996B2 (en) | 2013-07-31 | 2015-09-08 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) cell and high-K and metal gate transistor integration |
US8877585B1 (en) | 2013-08-16 | 2014-11-04 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration |
US8871598B1 (en) | 2013-07-31 | 2014-10-28 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology |
KR102055379B1 (ko) | 2013-08-08 | 2019-12-13 | 삼성전자 주식회사 | 트라이-게이트를 포함하는 반도체 소자 및 그 제조 방법 |
US9082837B2 (en) | 2013-08-08 | 2015-07-14 | Freescale Semiconductor, Inc. | Nonvolatile memory bitcell with inlaid high k metal select gate |
US9082650B2 (en) | 2013-08-21 | 2015-07-14 | Freescale Semiconductor, Inc. | Integrated split gate non-volatile memory cell and logic structure |
US9252246B2 (en) | 2013-08-21 | 2016-02-02 | Freescale Semiconductor, Inc. | Integrated split gate non-volatile memory cell and logic device |
US9275864B2 (en) | 2013-08-22 | 2016-03-01 | Freescale Semiconductor,Inc. | Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates |
US8932925B1 (en) | 2013-08-22 | 2015-01-13 | Freescale Semiconductor, Inc. | Split-gate non-volatile memory (NVM) cell and device structure integration |
US9136129B2 (en) | 2013-09-30 | 2015-09-15 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology |
US9129855B2 (en) | 2013-09-30 | 2015-09-08 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology |
US8901632B1 (en) | 2013-09-30 | 2014-12-02 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology |
US9231077B2 (en) | 2014-03-03 | 2016-01-05 | Freescale Semiconductor, Inc. | Method of making a logic transistor and non-volatile memory (NVM) cell |
US9252152B2 (en) | 2014-03-28 | 2016-02-02 | Freescale Semiconductor, Inc. | Method for forming a split-gate device |
US9472418B2 (en) | 2014-03-28 | 2016-10-18 | Freescale Semiconductor, Inc. | Method for forming a split-gate device |
US9112056B1 (en) | 2014-03-28 | 2015-08-18 | Freescale Semiconductor, Inc. | Method for forming a split-gate device |
US9379222B2 (en) | 2014-05-30 | 2016-06-28 | Freescale Semiconductor, Inc. | Method of making a split gate non-volatile memory (NVM) cell |
US9343314B2 (en) | 2014-05-30 | 2016-05-17 | Freescale Semiconductor, Inc. | Split gate nanocrystal memory integration |
US9257445B2 (en) | 2014-05-30 | 2016-02-09 | Freescale Semiconductor, Inc. | Method of making a split gate non-volatile memory (NVM) cell and a logic transistor |
CN104952734B (zh) | 2015-07-16 | 2020-01-24 | 矽力杰半导体技术(杭州)有限公司 | 半导体结构及其制造方法 |
US9570555B1 (en) | 2015-10-29 | 2017-02-14 | International Business Machines Corporation | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices |
US9972540B2 (en) | 2016-08-07 | 2018-05-15 | International Business Machines Corporation | Semiconductor device having multiple thickness oxides |
US10818341B1 (en) * | 2019-06-07 | 2020-10-27 | Nanya Technology Corporation | Sub-word line driver circuit with variable-thickness gate dielectric layer, semiconductor memory device having the same and method of forming the same |
US11791396B2 (en) | 2021-07-09 | 2023-10-17 | International Business Machines Corporation | Field effect transistor with multiple gate dielectrics and dual work-functions with precisely controlled gate lengths |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2583920B1 (fr) * | 1985-06-21 | 1987-07-31 | Commissariat Energie Atomique | Procede de fabrication d'un circuit integre et notamment d'une memoire eprom comportant deux composants distincts isoles electriquement |
JPH0383375A (ja) * | 1989-08-25 | 1991-04-09 | Sony Corp | 半導体装置 |
JPH04103162A (ja) * | 1990-08-23 | 1992-04-06 | Toshiba Corp | 絶縁膜を有する半導体装置の製造方法 |
JP3189284B2 (ja) * | 1991-02-14 | 2001-07-16 | ソニー株式会社 | 半導体装置の製造方法 |
JPH04276655A (ja) * | 1991-03-05 | 1992-10-01 | Olympus Optical Co Ltd | Cmos半導体装置の製造方法 |
JPH07335883A (ja) * | 1994-06-15 | 1995-12-22 | Toshiba Corp | 半導体装置の製造方法 |
US5480828A (en) * | 1994-09-30 | 1996-01-02 | Taiwan Semiconductor Manufacturing Corp. Ltd. | Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process |
JP3101515B2 (ja) * | 1995-01-20 | 2000-10-23 | 三洋電機株式会社 | Cmos半導体装置の製造方法 |
JP3243151B2 (ja) * | 1995-06-01 | 2002-01-07 | 東芝マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
DE69528971D1 (de) * | 1995-06-30 | 2003-01-09 | St Microelectronics Srl | Herstellungsverfahren eines Schaltkreises, der nichtflüchtige Speicherzellen und Randtransistoren von mindestens zwei unterschiedlichen Typen enthält, und entsprechender IC |
JPH09148449A (ja) * | 1995-11-20 | 1997-06-06 | Fujitsu Ltd | 半導体装置の製造方法 |
US5712201A (en) * | 1996-06-07 | 1998-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fabrication method for integrating logic and single level polysilicon DRAM devices on the same semiconductor chip |
US5668035A (en) * | 1996-06-10 | 1997-09-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for fabricating a dual-gate dielectric module for memory with embedded logic technology |
US5953599A (en) * | 1997-06-12 | 1999-09-14 | National Semiconductor Corporation | Method for forming low-voltage CMOS transistors with a thin layer of gate oxide and high-voltage CMOS transistors with a thick layer of gate oxide |
US5960289A (en) * | 1998-06-22 | 1999-09-28 | Motorola, Inc. | Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region |
-
1998
- 1998-02-05 US US09/018,939 patent/US6087225A/en not_active Expired - Lifetime
- 1998-06-17 TW TW087109624A patent/TW368734B/zh not_active IP Right Cessation
- 1998-10-28 MY MYPI98004916A patent/MY118598A/en unknown
-
1999
- 1999-01-04 CN CNB991009134A patent/CN1134061C/zh not_active Expired - Fee Related
- 1999-01-14 KR KR1019990000784A patent/KR100331527B1/ko not_active IP Right Cessation
- 1999-01-14 EP EP99300234A patent/EP0935285A1/en not_active Withdrawn
- 1999-01-29 JP JP11021159A patent/JP3111059B2/ja not_active Expired - Fee Related
- 1999-02-03 SG SG1999000336A patent/SG70150A1/en unknown
Also Published As
Publication number | Publication date |
---|---|
JPH11317459A (ja) | 1999-11-16 |
TW368734B (en) | 1999-09-01 |
KR100331527B1 (ko) | 2002-04-06 |
US6087225A (en) | 2000-07-11 |
CN1225507A (zh) | 1999-08-11 |
KR19990072249A (ko) | 1999-09-27 |
CN1134061C (zh) | 2004-01-07 |
MY118598A (en) | 2004-12-31 |
EP0935285A1 (en) | 1999-08-11 |
JP3111059B2 (ja) | 2000-11-20 |
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