SG47193A1 - Semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer and method of fabrication thereof - Google Patents

Semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer and method of fabrication thereof

Info

Publication number
SG47193A1
SG47193A1 SG1996011097A SG1996011097A SG47193A1 SG 47193 A1 SG47193 A1 SG 47193A1 SG 1996011097 A SG1996011097 A SG 1996011097A SG 1996011097 A SG1996011097 A SG 1996011097A SG 47193 A1 SG47193 A1 SG 47193A1
Authority
SG
Singapore
Prior art keywords
fabrication
integrated circuit
circuit device
silicide layer
electrical wiring
Prior art date
Application number
SG1996011097A
Other languages
English (en)
Inventor
Hiromi Todorobaru
Hideo Miura
Masayuki Suzuki
Shinji Nishihara
Shuji Ikeda
Masashi Sahara
Shinichi Ishida
Hiromi Abe
Atushi Ogishima
Hiroyuki Uchiyama
Nee Toda Sonoko Abe
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of SG47193A1 publication Critical patent/SG47193A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7845Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being a conductive material, e.g. silicided S/D or Gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
SG1996011097A 1995-11-14 1996-11-13 Semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer and method of fabrication thereof SG47193A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP29522095A JP3443219B2 (ja) 1995-11-14 1995-11-14 半導体集積回路装置およびその製造方法
JP03165596A JP3498089B2 (ja) 1995-11-14 1996-02-20 半導体装置

Publications (1)

Publication Number Publication Date
SG47193A1 true SG47193A1 (en) 1998-03-20

Family

ID=26370161

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996011097A SG47193A1 (en) 1995-11-14 1996-11-13 Semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer and method of fabrication thereof

Country Status (6)

Country Link
US (3) US6031288A (ja)
JP (2) JP3443219B2 (ja)
KR (1) KR100216092B1 (ja)
CN (1) CN1139129C (ja)
MY (1) MY115056A (ja)
SG (1) SG47193A1 (ja)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815762B2 (en) * 1997-05-30 2004-11-09 Hitachi, Ltd. Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines
US6838320B2 (en) * 2000-08-02 2005-01-04 Renesas Technology Corp. Method for manufacturing a semiconductor integrated circuit device
US5976976A (en) 1997-08-21 1999-11-02 Micron Technology, Inc. Method of forming titanium silicide and titanium by chemical vapor deposition
JP3919921B2 (ja) 1997-09-26 2007-05-30 三菱電機株式会社 半導体装置
US6329681B1 (en) * 1997-12-18 2001-12-11 Yoshitaka Nakamura Semiconductor integrated circuit device and method of manufacturing the same
KR100470944B1 (ko) * 1997-12-31 2005-07-18 주식회사 하이닉스반도체 반도체소자의비트라인형성방법
JP4931267B2 (ja) * 1998-01-29 2012-05-16 ルネサスエレクトロニクス株式会社 半導体装置
US6284316B1 (en) * 1998-02-25 2001-09-04 Micron Technology, Inc. Chemical vapor deposition of titanium
KR100292943B1 (ko) 1998-03-25 2001-09-17 윤종용 디램장치의제조방법
WO2000017939A1 (fr) * 1998-09-22 2000-03-30 Hitachi, Ltd. Dispositif a semi-conducteur et son procede de production
US6448631B2 (en) * 1998-09-23 2002-09-10 Artisan Components, Inc. Cell architecture with local interconnect and method for making same
JP2000188292A (ja) * 1998-12-21 2000-07-04 Mitsubishi Electric Corp 半導体装置および製造方法
KR100325302B1 (ko) * 1999-06-16 2002-02-21 김영환 반도체 소자의 제조방법
JP3943294B2 (ja) * 1999-08-18 2007-07-11 株式会社ルネサステクノロジ 半導体集積回路装置
US6440850B1 (en) 1999-08-27 2002-08-27 Micron Technology, Inc. Structure for an electrical contact to a thin film in a semiconductor structure and method for making the same
JP4117101B2 (ja) * 2000-08-30 2008-07-16 株式会社ルネサステクノロジ 半導体装置とその製造方法
KR100393971B1 (ko) * 2000-12-29 2003-08-06 주식회사 하이닉스반도체 임베디드 디램 로직의 비트라인 및 그 형성방법
JP2003100769A (ja) * 2001-09-20 2003-04-04 Nec Corp 半導体装置およびその製造方法
JP2003093370A (ja) * 2001-09-26 2003-04-02 Sony Corp 指紋検出装置
US7725732B1 (en) * 2003-12-16 2010-05-25 Ballard Claudio R Object authentication system
KR100637690B1 (ko) * 2005-04-25 2006-10-24 주식회사 하이닉스반도체 고상에피택시 방식을 이용한 반도체소자 및 그의 제조 방법
US7923362B2 (en) * 2005-06-08 2011-04-12 Telefunken Semiconductors Gmbh & Co. Kg Method for manufacturing a metal-semiconductor contact in semiconductor components
DE102005026301B3 (de) * 2005-06-08 2007-01-11 Atmel Germany Gmbh Verfahren zum Herstellen eines Metall- Halbleiter-Kontakts bei Halbleiterbauelementen
KR100799119B1 (ko) * 2005-08-29 2008-01-29 주식회사 하이닉스반도체 반도체메모리소자 제조 방법
KR100750943B1 (ko) * 2006-07-03 2007-08-22 삼성전자주식회사 반도체 장치의 배선 구조물 및 그 형성 방법
DE102007004884A1 (de) * 2007-01-31 2008-08-14 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum durch stromlose Abscheidung unter Anwendung einer selektiv vorgesehenen Aktivierungsschicht
US20080240936A1 (en) * 2007-04-02 2008-10-02 Douglas Kent Ritterling Portable air compressor
US8183145B2 (en) 2007-10-11 2012-05-22 International Business Machines Corporation Structure and methods of forming contact structures
US20110182754A1 (en) * 2008-10-07 2011-07-28 Adam Gathers Portable air compressor
JP5376916B2 (ja) * 2008-11-26 2013-12-25 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
EP2320085A3 (en) * 2009-11-05 2012-01-25 Techtronic Power Tools Technology Limited Portable air compressor
TWI423410B (zh) * 2010-12-31 2014-01-11 Au Optronics Corp 金屬導電結構及其製作方法
US8772159B2 (en) * 2012-02-01 2014-07-08 United Microelectronics Corp. Method of fabricating electrical contact
KR101934426B1 (ko) * 2012-11-26 2019-01-03 삼성전자 주식회사 반도체 장치 및 그 제조 방법
JP6648544B2 (ja) * 2016-02-08 2020-02-14 三菱電機株式会社 半導体装置
JP2018152514A (ja) * 2017-03-14 2018-09-27 富士電機株式会社 半導体装置の製造方法および半導体装置
JP7283036B2 (ja) * 2018-07-13 2023-05-30 富士電機株式会社 半導体装置および製造方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3314879A1 (de) * 1983-04-25 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von stabilen, niederohmigen kontakten in integrierten halbleiterschaltungen
US4920071A (en) * 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
US4914500A (en) 1987-12-04 1990-04-03 At&T Bell Laboratories Method for fabricating semiconductor devices which include sources and drains having metal-containing material regions, and the resulting devices
US4994410A (en) * 1988-04-04 1991-02-19 Motorola, Inc. Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process
US4829024A (en) * 1988-09-02 1989-05-09 Motorola, Inc. Method of forming layered polysilicon filled contact by doping sensitive endpoint etching
US5166771A (en) * 1990-01-12 1992-11-24 Paradigm Technology, Inc. Self-aligning contact and interconnect structure
JPH0541378A (ja) * 1991-03-15 1993-02-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR970009274B1 (ko) * 1991-11-11 1997-06-09 미쓰비시덴키 가부시키가이샤 반도체장치의 도전층접속구조 및 그 제조방법
US5397912A (en) * 1991-12-02 1995-03-14 Motorola, Inc. Lateral bipolar transistor
US5444302A (en) 1992-12-25 1995-08-22 Hitachi, Ltd. Semiconductor device including multi-layer conductive thin film of polycrystalline material
US5381302A (en) * 1993-04-02 1995-01-10 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same
US5382533A (en) * 1993-06-18 1995-01-17 Micron Semiconductor, Inc. Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron injection
JP2596331B2 (ja) 1993-09-08 1997-04-02 日本電気株式会社 半導体装置およびその製造方法
JP3666893B2 (ja) 1993-11-19 2005-06-29 株式会社日立製作所 半導体メモリ装置
JPH07263576A (ja) 1994-03-25 1995-10-13 Hitachi Ltd 半導体集積回路装置およびその製造方法
JPH08107087A (ja) 1994-10-06 1996-04-23 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH08191054A (ja) * 1995-01-10 1996-07-23 Kawasaki Steel Corp 半導体装置及びその製造方法
US5614422A (en) 1995-03-17 1997-03-25 Harris Corporation Process for doping two levels of a double poly bipolar transistor after formation of second poly layer
US5484747A (en) * 1995-05-25 1996-01-16 United Microelectronics Corporation Selective metal wiring and plug process
US5686761A (en) * 1995-06-06 1997-11-11 Advanced Micro Devices, Inc. Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology
SG46751A1 (en) * 1996-01-11 1998-02-20 Taiwan Semiconductor Mfg A modified tungsten-plug contact process
US5918120A (en) * 1998-07-24 1999-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and Ti/TiN bit lines
US5893734A (en) * 1998-09-14 1999-04-13 Vanguard International Semiconductor Corporation Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory (DRAM) using tungsten landing plug contacts

Also Published As

Publication number Publication date
US6503803B2 (en) 2003-01-07
US6268658B1 (en) 2001-07-31
KR970030370A (ko) 1997-06-26
JPH09139475A (ja) 1997-05-27
MY115056A (en) 2003-03-31
JP3443219B2 (ja) 2003-09-02
US6031288A (en) 2000-02-29
CN1139129C (zh) 2004-02-18
KR100216092B1 (ko) 1999-08-16
CN1161573A (zh) 1997-10-08
JPH09232422A (ja) 1997-09-05
JP3498089B2 (ja) 2004-02-16
US20010023958A1 (en) 2001-09-27

Similar Documents

Publication Publication Date Title
SG47193A1 (en) Semiconductor integrated circuit device for connecting semiconductor region and electrical wiring metal via titanium silicide layer and method of fabrication thereof
GB2304231B (en) Semiconductor integrated circuit device and method of manufacturing the same
GB2326765B (en) Method of manufacturing semiconductor device having multilayer wiring
AU5793996A (en) Heat sink and retainer for electronic integrated circuits
SG77181A1 (en) Hybrid wiring board semiconductor apparatus flexiblesubstrate and fabrication method of hybrid wiring board
SG75953A1 (en) Process for producing semiconductor integrated circuit device and semiconductor integrated circuit device
GB9511567D0 (en) Wiring structure of semiconductor device and method for manufacturing the same
HK1109248A1 (en) Semiconductor integrated circuit and method for designing semiconductor integrated circuit
EP0740340A3 (en) Structure and method of mounting a semiconductor device
SG75830A1 (en) Process for mounting electronic device and semiconductor device
EP0780894A3 (en) Method for manufacturing holes and submicron contacts in an integrated circuit
GB2345382B (en) Layout method of semiconductor device
GB2336034B (en) Semiconductor wafer fabrication of die-bottom contacts for electronic devices
GB2347268B (en) Method of semiconductor device fabrication
GB2337636B (en) Semiconductor wafer fabrication of inside-wrapped contacts for electronic devices
SG68095A1 (en) Fabrication method of wiring substrate for mounting semiconductor element and semiconductor device
GB2298657B (en) Methods of forming metal interconnects in semiconductor devices
SG54398A1 (en) Semiconductor integrated circuit device and method for manufacturing the same
EP0984485A4 (en) MANUFACTURING METHOD FOR WIRING SEMICONDUCTOR ARRANGEMENTS
EP0740342A3 (en) Semiconductor device and wiring method
SG55222A1 (en) A method of forming a low stress silicide conductors on a semiconductor chip
SG73599A1 (en) Semiconductor device and method of manufacturing the same and electronic apparatus
SG74105A1 (en) Semiconductor device method of manufacturing the same circuit board and electronic instrument
GB2306781B (en) Method for forming metal wiring of semiconductor device
AU6319796A (en) Method of production of semiconductor integrated circuit device