SG152207A1 - Methods for forming high aspect ratio features on a substrate - Google Patents

Methods for forming high aspect ratio features on a substrate

Info

Publication number
SG152207A1
SG152207A1 SG200808129-1A SG2008081291A SG152207A1 SG 152207 A1 SG152207 A1 SG 152207A1 SG 2008081291 A SG2008081291 A SG 2008081291A SG 152207 A1 SG152207 A1 SG 152207A1
Authority
SG
Singapore
Prior art keywords
high aspect
substrate
methods
features
aspect ratio
Prior art date
Application number
SG200808129-1A
Other languages
English (en)
Inventor
Kenny Linh Doan
Kathryn Keswick
Subhash Deshmukh
Stephan Wege
Wonseok Lee
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of SG152207A1 publication Critical patent/SG152207A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
SG200808129-1A 2007-11-02 2008-10-31 Methods for forming high aspect ratio features on a substrate SG152207A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/934,589 US20100330805A1 (en) 2007-11-02 2007-11-02 Methods for forming high aspect ratio features on a substrate

Publications (1)

Publication Number Publication Date
SG152207A1 true SG152207A1 (en) 2009-05-29

Family

ID=40297950

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200808129-1A SG152207A1 (en) 2007-11-02 2008-10-31 Methods for forming high aspect ratio features on a substrate

Country Status (7)

Country Link
US (1) US20100330805A1 (ko)
EP (1) EP2056341A3 (ko)
JP (1) JP5553501B2 (ko)
KR (1) KR101103214B1 (ko)
CN (1) CN101431023B (ko)
SG (1) SG152207A1 (ko)
TW (1) TW200935519A (ko)

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CN109923662A (zh) 2016-11-08 2019-06-21 应用材料公司 用于图案化应用的自底向上的柱状体的几何控制
US10770349B2 (en) 2017-02-22 2020-09-08 Applied Materials, Inc. Critical dimension control for self-aligned contact patterning
JP6861535B2 (ja) * 2017-02-28 2021-04-21 東京エレクトロン株式会社 処理方法及びプラズマ処理装置
WO2018200212A1 (en) 2017-04-25 2018-11-01 Applied Materials, Inc. Selective deposition of tungsten for simplified process flow of tungsten oxide pillar formation
US10840186B2 (en) 2017-06-10 2020-11-17 Applied Materials, Inc. Methods of forming self-aligned vias and air gaps
TW201906035A (zh) 2017-06-24 2019-02-01 美商微材料有限責任公司 生產完全自我對準的介層窗及觸點之方法
WO2019046402A1 (en) 2017-08-31 2019-03-07 Micromaterials Llc METHODS FOR GENERATING SELF-ALIGNED INTERCONNECTION HOLES
WO2019046399A1 (en) 2017-08-31 2019-03-07 Micromaterials Llc METHODS FOR PRODUCING SELF-ALIGNED INTERCONNECTION HOLES
CN111133579B (zh) 2017-09-05 2023-09-01 应用材料公司 3d存储器结构中由下而上方式的高深宽比孔洞形成
WO2019050735A1 (en) 2017-09-06 2019-03-14 Micromaterials Llc METHODS FOR PRODUCING SELF-ALIGNED INTERCONNECTION HOLES
JP2019106538A (ja) 2017-12-07 2019-06-27 マイクロマテリアルズ エルエルシー 制御可能な金属およびバリアライナー凹部のための方法
EP3499557A1 (en) 2017-12-15 2019-06-19 Micromaterials LLC Selectively etched self-aligned via processes
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TW202002219A (zh) 2018-05-08 2020-01-01 美商微材料有限責任公司 用來產生高的深寬比的完全自對準的通孔的選擇性移除過程
TW202011547A (zh) 2018-05-16 2020-03-16 美商微材料有限責任公司 用於產生完全自對準的通孔的方法
WO2019236350A1 (en) 2018-06-08 2019-12-12 Micromaterials Llc A method for creating a fully self-aligned via
US11962284B2 (en) * 2018-07-30 2024-04-16 Kyocera Corporation Composite substrate
WO2020031224A1 (ja) 2018-08-06 2020-02-13 株式会社日立ハイテクノロジーズ プラズマ処理方法およびプラズマアッシング装置
US11164938B2 (en) 2019-03-26 2021-11-02 Micromaterials Llc DRAM capacitor module
KR20220024406A (ko) * 2019-06-04 2022-03-03 램 리써치 코포레이션 패터닝시 반응성 이온 에칭을 위한 중합 보호 라이너
CN111508929B (zh) * 2020-04-17 2022-02-22 北京北方华创微电子装备有限公司 图形片及半导体中间产物
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Also Published As

Publication number Publication date
JP5553501B2 (ja) 2014-07-16
JP2009135478A (ja) 2009-06-18
CN101431023A (zh) 2009-05-13
CN101431023B (zh) 2011-04-13
US20100330805A1 (en) 2010-12-30
TW200935519A (en) 2009-08-16
KR101103214B1 (ko) 2012-01-05
EP2056341A2 (en) 2009-05-06
KR20090045868A (ko) 2009-05-08
EP2056341A3 (en) 2010-03-03

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