SG11202008234UA - Method for producing a thin film consisting of an alkaline-based ferroelectric material - Google Patents

Method for producing a thin film consisting of an alkaline-based ferroelectric material

Info

Publication number
SG11202008234UA
SG11202008234UA SG11202008234UA SG11202008234UA SG11202008234UA SG 11202008234U A SG11202008234U A SG 11202008234UA SG 11202008234U A SG11202008234U A SG 11202008234UA SG 11202008234U A SG11202008234U A SG 11202008234UA SG 11202008234U A SG11202008234U A SG 11202008234UA
Authority
SG
Singapore
Prior art keywords
alkaline
producing
thin film
ferroelectric material
film consisting
Prior art date
Application number
SG11202008234UA
Other languages
English (en)
Inventor
Alexis Drouin
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202008234UA publication Critical patent/SG11202008234UA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/516Insulating materials associated therewith with at least one ferroelectric layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00Piezoelectric or electrostrictive devices
    • H10N30/01Manufacture or treatment
    • H10N30/07Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Optical Modulation, Optical Deflection, Nonlinear Optics, Optical Demodulation, Optical Logic Elements (AREA)
  • Semiconductor Memories (AREA)
SG11202008234UA 2018-03-12 2019-02-18 Method for producing a thin film consisting of an alkaline-based ferroelectric material SG11202008234UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1852122A FR3078822B1 (fr) 2018-03-12 2018-03-12 Procede de preparation d’une couche mince de materiau ferroelectrique a base d’alcalin
PCT/FR2019/050356 WO2019175487A1 (fr) 2018-03-12 2019-02-18 Procede de preparation d'une couche mince de materiau ferroelectriqie a base d'alcalin

Publications (1)

Publication Number Publication Date
SG11202008234UA true SG11202008234UA (en) 2020-09-29

Family

ID=62751028

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202008234UA SG11202008234UA (en) 2018-03-12 2019-02-18 Method for producing a thin film consisting of an alkaline-based ferroelectric material

Country Status (8)

Country Link
US (2) US11309399B2 (ja)
EP (1) EP3766094B1 (ja)
JP (1) JP7344217B2 (ja)
KR (1) KR102624401B1 (ja)
CN (1) CN111837216B (ja)
FR (1) FR3078822B1 (ja)
SG (1) SG11202008234UA (ja)
WO (1) WO2019175487A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3094573B1 (fr) * 2019-03-29 2021-08-13 Soitec Silicon On Insulator Procede de preparation d’une couche mince de materiau ferroelectrique
CN115548128B (zh) * 2022-12-05 2023-04-14 浙江大学杭州国际科创中心 一种铁电半导体器件、制备方法以及实现多铁电相的方法

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2565346B2 (ja) * 1987-06-26 1996-12-18 清水 郁子 分極反転領域を有するLiNbO▲下3▼/LiTaO▲下3▼単結晶圧電基板及びその製造方法
SE462352B (sv) * 1988-10-25 1990-06-11 Optisk Forskning Inst Vaagledare samt foerfarande foer framstaellning av saadan
JP3052501B2 (ja) * 1990-11-30 2000-06-12 松下電器産業株式会社 波長変換素子の製造方法
JPH05249522A (ja) * 1992-03-06 1993-09-28 Fujitsu Ltd 分極反転素子の製造方法
US5363462A (en) * 1993-07-02 1994-11-08 Eastman Kodak Company Multilayer waveguide using a nonlinear LiNb Ta1-x O3 optical film
US5436758A (en) * 1994-06-17 1995-07-25 Eastman Kodak Company Quasi-phasematched frequency converters
US6251754B1 (en) * 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
US6159825A (en) * 1997-05-12 2000-12-12 Silicon Genesis Corporation Controlled cleavage thin film separation process using a reusable substrate
US6699521B1 (en) * 2000-04-17 2004-03-02 The United States Of America As Represented By The Secretary Of The Army Method of fabricating a ferroelectric/pyroelectric infrared detector using a crystallographically oriented electrode and a rock salt structure material substrate
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
US6710912B1 (en) * 2002-12-23 2004-03-23 General Electric Company Technique for quasi-phase matching
JP3994163B2 (ja) * 2003-09-26 2007-10-17 独立行政法人物質・材料研究機構 Nbt強誘電体薄膜の製造方法
FR2861497B1 (fr) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
FR2863771B1 (fr) 2003-12-10 2007-03-02 Soitec Silicon On Insulator Procede de traitement d'une tranche multicouche presentant un differentiel de caracteristiques thermiques
WO2006037783A1 (fr) * 2004-10-04 2006-04-13 S.O.I.Tec Silicon On Insulator Technologies Procédé de transfert d'une couche mince comprenant une perturbation controlée d'une structure cristalline
FR2883659B1 (fr) * 2005-03-24 2007-06-22 Soitec Silicon On Insulator Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur
US7928317B2 (en) * 2006-06-05 2011-04-19 Translucent, Inc. Thin film solar cell
FR2907966B1 (fr) * 2006-10-27 2009-01-30 Soitec Silicon On Insulator Procede de fabrication d'un substrat.
FR2914492A1 (fr) * 2007-03-27 2008-10-03 Soitec Silicon On Insulator Procede de fabrication de structures avec couches ferroelectriques reportees.
US7838066B2 (en) * 2007-12-20 2010-11-23 Seagate Technology Llc Ferroelectric media with robust servo marks and storage areas with low leakage current
WO2009081651A1 (ja) * 2007-12-25 2009-07-02 Murata Manufacturing Co., Ltd. 複合圧電基板の製造方法
FR2926674B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
FR2929758B1 (fr) * 2008-04-07 2011-02-11 Commissariat Energie Atomique Procede de transfert a l'aide d'un substrat ferroelectrique
FR2930072B1 (fr) * 2008-04-15 2010-08-20 Commissariat Energie Atomique Procede de transfert d'une couche mince par echange protonique.
FR2930674A1 (fr) * 2008-04-29 2009-10-30 Soitec Silicon On Insulator Procede de traitement d'une heterostructure comportant une couche mince en materiau ferroelectrique
FR2938120B1 (fr) * 2008-10-31 2011-04-08 Commissariat Energie Atomique Procede de formation d'une couche monocristalline dans le domaine micro-electronique
US8546238B2 (en) * 2009-04-22 2013-10-01 Commissariat A L'energie Atomique Et Aux Energies Method for transferring at least one micro-technological layer
JP5569537B2 (ja) * 2009-11-26 2014-08-13 株式会社村田製作所 圧電デバイスの製造方法
JP5429200B2 (ja) * 2010-05-17 2014-02-26 株式会社村田製作所 複合圧電基板の製造方法および圧電デバイス
FR2961515B1 (fr) * 2010-06-22 2012-08-24 Commissariat Energie Atomique Procede de realisation d'une couche mince de silicium monocristallin sur une couche de polymere
FR2995444B1 (fr) * 2012-09-10 2016-11-25 Soitec Silicon On Insulator Procede de detachement d'une couche
CN103296003A (zh) * 2013-05-29 2013-09-11 上海宏力半导体制造有限公司 电容结构及其形成方法
JP6396853B2 (ja) * 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法

Also Published As

Publication number Publication date
CN111837216B (zh) 2024-02-20
EP3766094A1 (fr) 2021-01-20
US20220285520A1 (en) 2022-09-08
FR3078822B1 (fr) 2020-02-28
JP7344217B2 (ja) 2023-09-13
US11309399B2 (en) 2022-04-19
JP2021515989A (ja) 2021-06-24
WO2019175487A1 (fr) 2019-09-19
EP3766094B1 (fr) 2022-04-27
US20210036124A1 (en) 2021-02-04
KR20200128536A (ko) 2020-11-13
CN111837216A (zh) 2020-10-27
KR102624401B1 (ko) 2024-01-12
FR3078822A1 (fr) 2019-09-13

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