SG11202008234UA - Method for producing a thin film consisting of an alkaline-based ferroelectric material - Google Patents

Method for producing a thin film consisting of an alkaline-based ferroelectric material

Info

Publication number
SG11202008234UA
SG11202008234UA SG11202008234UA SG11202008234UA SG11202008234UA SG 11202008234U A SG11202008234U A SG 11202008234UA SG 11202008234U A SG11202008234U A SG 11202008234UA SG 11202008234U A SG11202008234U A SG 11202008234UA SG 11202008234U A SG11202008234U A SG 11202008234UA
Authority
SG
Singapore
Prior art keywords
alkaline
producing
thin film
ferroelectric material
film consisting
Prior art date
Application number
SG11202008234UA
Inventor
Alexis Drouin
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202008234UA publication Critical patent/SG11202008234UA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/516Insulating materials associated therewith with at least one ferroelectric layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00Piezoelectric or electrostrictive devices
    • H10N30/01Manufacture or treatment
    • H10N30/07Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Semiconductor Memories (AREA)
  • Optical Modulation, Optical Deflection, Nonlinear Optics, Optical Demodulation, Optical Logic Elements (AREA)
SG11202008234UA 2018-03-12 2019-02-18 Method for producing a thin film consisting of an alkaline-based ferroelectric material SG11202008234UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1852122A FR3078822B1 (en) 2018-03-12 2018-03-12 PROCESS FOR THE PREPARATION OF A THIN LAYER OF ALKALINE BASED FERROELECTRIC MATERIAL
PCT/FR2019/050356 WO2019175487A1 (en) 2018-03-12 2019-02-18 Method for producing a thin film consisting of an alkaline-based ferroelectric material

Publications (1)

Publication Number Publication Date
SG11202008234UA true SG11202008234UA (en) 2020-09-29

Family

ID=62751028

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202008234UA SG11202008234UA (en) 2018-03-12 2019-02-18 Method for producing a thin film consisting of an alkaline-based ferroelectric material

Country Status (8)

Country Link
US (2) US11309399B2 (en)
EP (1) EP3766094B1 (en)
JP (1) JP7344217B2 (en)
KR (1) KR102624401B1 (en)
CN (1) CN111837216B (en)
FR (1) FR3078822B1 (en)
SG (1) SG11202008234UA (en)
WO (1) WO2019175487A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3094573B1 (en) * 2019-03-29 2021-08-13 Soitec Silicon On Insulator PROCESS FOR PREPARING A THIN LAYER OF FERROELECTRIC MATERIAL
CN115548128B (en) * 2022-12-05 2023-04-14 浙江大学杭州国际科创中心 Ferroelectric semiconductor device, preparation method and method for realizing multiple ferroelectric phases

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JP3052501B2 (en) * 1990-11-30 2000-06-12 松下電器産業株式会社 Manufacturing method of wavelength conversion element
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FR2816445B1 (en) * 2000-11-06 2003-07-25 Commissariat Energie Atomique METHOD FOR MANUFACTURING A STACKED STRUCTURE COMPRISING A THIN LAYER ADHERING TO A TARGET SUBSTRATE
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FR2861497B1 (en) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator METHOD FOR CATASTROPHIC TRANSFER OF A FINE LAYER AFTER CO-IMPLANTATION
FR2863771B1 (en) 2003-12-10 2007-03-02 Soitec Silicon On Insulator PROCESS FOR PROCESSING A MULTILAYER WAFER HAVING A DIFFERENTIAL OF THERMAL CHARACTERISTICS
WO2006037783A1 (en) * 2004-10-04 2006-04-13 S.O.I.Tec Silicon On Insulator Technologies Method for transferring a thin film comprising a controlled disturbance of a crystal structure
FR2883659B1 (en) * 2005-03-24 2007-06-22 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A HETERO-STRUCTURE COMPRISING AT LEAST ONE THICK LAYER OF SEMICONDUCTOR MATERIAL
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FR2907966B1 (en) * 2006-10-27 2009-01-30 Soitec Silicon On Insulator PROCESS FOR PRODUCING A SUBSTRATE
FR2914492A1 (en) * 2007-03-27 2008-10-03 Soitec Silicon On Insulator Substrate's thin ferroelectric layer manufacturing method for manufacturing e.g. piezoelectric sensor, involves subjecting resulting structure having transferred thin layer to electrical field to improve ferroelectric properties of layer
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FR2926674B1 (en) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator METHOD FOR MANUFACTURING COMPOSITE STRUCTURE WITH STABLE BONDING OXIDE LAYER
FR2929758B1 (en) * 2008-04-07 2011-02-11 Commissariat Energie Atomique TRANSFER METHOD USING A FERROELECTRIC SUBSTRATE
FR2930072B1 (en) * 2008-04-15 2010-08-20 Commissariat Energie Atomique METHOD OF TRANSFERRING A THIN LAYER BY PROTONIC EXCHANGE
FR2930674A1 (en) * 2008-04-29 2009-10-30 Soitec Silicon On Insulator Heterostructure e.g. silicon-on-insulator type substrate, fabricating method for e.g. optoelectronic field, involves subjecting heterostructure to ionic implantation operation using ions of atomic species within ferroelectric thin layer
FR2938120B1 (en) * 2008-10-31 2011-04-08 Commissariat Energie Atomique PROCESS FOR FORMATION OF A MONOCRYSTALLINE LAYER IN THE MICROELECTRONIC DOMAIN
US8546238B2 (en) * 2009-04-22 2013-10-01 Commissariat A L'energie Atomique Et Aux Energies Method for transferring at least one micro-technological layer
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JP5429200B2 (en) * 2010-05-17 2014-02-26 株式会社村田製作所 Method for manufacturing composite piezoelectric substrate and piezoelectric device
FR2961515B1 (en) * 2010-06-22 2012-08-24 Commissariat Energie Atomique METHOD FOR PRODUCING A MONOCRYSTALLINE SILICON THIN LAYER ON A POLYMER LAYER
FR2995444B1 (en) * 2012-09-10 2016-11-25 Soitec Silicon On Insulator METHOD FOR DETACHING A LAYER
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JP6396853B2 (en) * 2015-06-02 2018-09-26 信越化学工業株式会社 Method for manufacturing composite wafer having oxide single crystal thin film

Also Published As

Publication number Publication date
CN111837216A (en) 2020-10-27
CN111837216B (en) 2024-02-20
WO2019175487A1 (en) 2019-09-19
KR20200128536A (en) 2020-11-13
US11309399B2 (en) 2022-04-19
EP3766094B1 (en) 2022-04-27
US20210036124A1 (en) 2021-02-04
JP7344217B2 (en) 2023-09-13
US20220285520A1 (en) 2022-09-08
KR102624401B1 (en) 2024-01-12
JP2021515989A (en) 2021-06-24
FR3078822A1 (en) 2019-09-13
FR3078822B1 (en) 2020-02-28
EP3766094A1 (en) 2021-01-20

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