SG11202110012UA - Method for preparing a thin layer of ferroelectric material - Google Patents

Method for preparing a thin layer of ferroelectric material

Info

Publication number
SG11202110012UA
SG11202110012UA SG11202110012UA SG11202110012UA SG11202110012UA SG 11202110012U A SG11202110012U A SG 11202110012UA SG 11202110012U A SG11202110012U A SG 11202110012UA SG 11202110012U A SG11202110012U A SG 11202110012UA SG 11202110012U A SG11202110012U A SG 11202110012UA
Authority
SG
Singapore
Prior art keywords
preparing
thin layer
ferroelectric material
ferroelectric
thin
Prior art date
Application number
SG11202110012UA
Inventor
Alexis Drouin
Isabelle Huyet
Morgane Logiou
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202110012UA publication Critical patent/SG11202110012UA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02559—Characteristics of substrate, e.g. cutting angles of lithium niobate or lithium-tantalate substrates
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02535—Details of surface acoustic wave devices
    • H03H9/02543—Characteristics of substrate, e.g. cutting angles
    • H03H9/02574—Characteristics of substrate, e.g. cutting angles of combined substrates, multilayered substrates, piezoelectrical layers on not-piezoelectrical substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/20—Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H10N30/853—Ceramic compositions
    • H10N30/8542—Alkali metal based oxides, e.g. lithium, sodium or potassium niobates
SG11202110012UA 2019-03-29 2020-03-26 Method for preparing a thin layer of ferroelectric material SG11202110012UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1903359A FR3094573B1 (en) 2019-03-29 2019-03-29 PROCESS FOR PREPARING A THIN LAYER OF FERROELECTRIC MATERIAL
PCT/EP2020/058460 WO2020200986A1 (en) 2019-03-29 2020-03-26 Method for preparing a thin layer of ferroelectric material

Publications (1)

Publication Number Publication Date
SG11202110012UA true SG11202110012UA (en) 2021-10-28

Family

ID=67742635

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202110012UA SG11202110012UA (en) 2019-03-29 2020-03-26 Method for preparing a thin layer of ferroelectric material

Country Status (10)

Country Link
US (1) US20240072753A1 (en)
EP (1) EP3948966B1 (en)
JP (1) JP2022528388A (en)
KR (1) KR20210144772A (en)
CN (1) CN113544869A (en)
FI (1) FI3948966T3 (en)
FR (1) FR3094573B1 (en)
SG (1) SG11202110012UA (en)
TW (1) TW202105780A (en)
WO (1) WO2020200986A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI771049B (en) * 2021-06-08 2022-07-11 環球晶圓股份有限公司 Wafer fixture structure and processing apparatus for causing high-temperature creep deformation
FR3129033B1 (en) 2021-11-10 2023-12-29 Soitec Silicon On Insulator METHOD FOR PREPARING A THIN LAYER OF FERROELECTRIC MATERIAL
FR3137490A1 (en) * 2022-07-04 2024-01-05 Soitec METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A BARRIER LAYER TO THE DIFFUSION OF ATOMIC SPECIES
FR3138596A1 (en) * 2022-07-29 2024-02-02 Soitec Process for preparing a thin single-domain layer of ferroelectric material comprising lithium
FR3141592A1 (en) * 2022-10-26 2024-05-03 Soitec Piezoelectric substrate on insulator (POI) and method of manufacturing a piezoelectric substrate on insulator (POI)
FR3141591A1 (en) * 2022-10-26 2024-05-03 Soitec Piezoelectric substrate on insulator (POI) and method of manufacturing a piezoelectric substrate on insulator (POI)
FR3141590A1 (en) * 2022-10-26 2024-05-03 Soitec Piezoelectric substrate on insulator (POI) and method of manufacturing a piezoelectric substrate on insulator (POI)

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6593212B1 (en) * 2001-10-29 2003-07-15 The United States Of America As Represented By The Secretary Of The Navy Method for making electro-optical devices using a hydrogenion splitting technique
FR2860341B1 (en) 2003-09-26 2005-12-30 Soitec Silicon On Insulator METHOD FOR MANUFACTURING LOWERED LOWER MULTILAYER STRUCTURE
FR2914492A1 (en) 2007-03-27 2008-10-03 Soitec Silicon On Insulator Substrate's thin ferroelectric layer manufacturing method for manufacturing e.g. piezoelectric sensor, involves subjecting resulting structure having transferred thin layer to electrical field to improve ferroelectric properties of layer
WO2009081651A1 (en) 2007-12-25 2009-07-02 Murata Manufacturing Co., Ltd. Composite piezoelectric substrate manufacturing method
FR2933233B1 (en) 2008-06-30 2010-11-26 Soitec Silicon On Insulator GOOD RESISTANCE HIGH RESISTIVITY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
FR2953640B1 (en) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech METHOD FOR MANUFACTURING A SEMICONDUCTOR TYPE STRUCTURE ON INSULATION, WITH REDUCED ELECTRICAL LOSSES AND CORRESPONDING STRUCTURE
EP2690782B1 (en) * 2011-03-22 2020-09-09 Murata Manufacturing Co., Ltd. Piezoelectric device and manufacturing method for piezoelectric device
US9768056B2 (en) 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
FR3068508B1 (en) * 2017-06-30 2019-07-26 Soitec METHOD OF TRANSFERRING A THIN LAYER TO A SUPPORT SUBSTRATE HAVING DIFFERENT THERMAL EXPANSION COEFFICIENTS
FR3078822B1 (en) * 2018-03-12 2020-02-28 Soitec PROCESS FOR THE PREPARATION OF A THIN LAYER OF ALKALINE BASED FERROELECTRIC MATERIAL

Also Published As

Publication number Publication date
EP3948966A1 (en) 2022-02-09
CN113544869A (en) 2021-10-22
US20240072753A1 (en) 2024-02-29
WO2020200986A1 (en) 2020-10-08
FR3094573A1 (en) 2020-10-02
FR3094573B1 (en) 2021-08-13
TW202105780A (en) 2021-02-01
KR20210144772A (en) 2021-11-30
FI3948966T3 (en) 2024-01-02
EP3948966B1 (en) 2023-11-08
JP2022528388A (en) 2022-06-10

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