SG11201404576TA - Methods of providing thin layers of crystalline semiconductor material, and related structures and devices - Google Patents

Methods of providing thin layers of crystalline semiconductor material, and related structures and devices

Info

Publication number
SG11201404576TA
SG11201404576TA SG11201404576TA SG11201404576TA SG11201404576TA SG 11201404576T A SG11201404576T A SG 11201404576TA SG 11201404576T A SG11201404576T A SG 11201404576TA SG 11201404576T A SG11201404576T A SG 11201404576TA SG 11201404576T A SG11201404576T A SG 11201404576TA
Authority
SG
Singapore
Prior art keywords
methods
devices
semiconductor material
crystalline semiconductor
thin layers
Prior art date
Application number
SG11201404576TA
Other languages
English (en)
Inventor
Mariam Sadaka
Ionut Radu
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/402,464 external-priority patent/US9136134B2/en
Priority claimed from FR1252148A external-priority patent/FR2987936B1/fr
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201404576TA publication Critical patent/SG11201404576TA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Weting (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
SG11201404576TA 2012-02-22 2013-02-01 Methods of providing thin layers of crystalline semiconductor material, and related structures and devices SG11201404576TA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/402,464 US9136134B2 (en) 2012-02-22 2012-02-22 Methods of providing thin layers of crystalline semiconductor material, and related structures and devices
FR1252148A FR2987936B1 (fr) 2012-03-09 2012-03-09 Procedes de fabrication de fines couches de materiau semi-conducteur cristallin, et structures et dispositifs connexes
PCT/IB2013/000139 WO2013124719A1 (en) 2012-02-22 2013-02-01 Methods of providing thin layers of crystalline semiconductor material, and related structures and devices

Publications (1)

Publication Number Publication Date
SG11201404576TA true SG11201404576TA (en) 2014-10-30

Family

ID=47901230

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201404576TA SG11201404576TA (en) 2012-02-22 2013-02-01 Methods of providing thin layers of crystalline semiconductor material, and related structures and devices

Country Status (6)

Country Link
JP (1) JP6193271B2 (ja)
KR (1) KR102031725B1 (ja)
CN (1) CN104115259B (ja)
SG (1) SG11201404576TA (ja)
TW (1) TWI588886B (ja)
WO (1) WO2013124719A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112382555B (zh) * 2020-11-12 2024-07-19 广东先导微电子科技有限公司 一种磷化铟衬底的清洗方法
WO2023234368A1 (ja) * 2022-06-02 2023-12-07 セントラル硝子株式会社 基材の処理方法、および基材の製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223081A (en) * 1991-07-03 1993-06-29 Doan Trung T Method for roughening a silicon or polysilicon surface for a semiconductor substrate
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3187498B2 (ja) * 1992-01-27 2001-07-11 株式会社東芝 半導体装置
JPH07254574A (ja) * 1994-03-16 1995-10-03 Sony Corp 電極形成方法
KR100199064B1 (ko) * 1995-10-17 1999-07-01 구자홍 박막 트랜지스터 제조방법
FR2755537B1 (fr) 1996-11-05 1999-03-05 Commissariat Energie Atomique Procede de fabrication d'un film mince sur un support et structure ainsi obtenue
FR2767416B1 (fr) 1997-08-12 1999-10-01 Commissariat Energie Atomique Procede de fabrication d'un film mince de materiau solide
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2795865B1 (fr) 1999-06-30 2001-08-17 Commissariat Energie Atomique Procede de realisation d'un film mince utilisant une mise sous pression
FR2818010B1 (fr) 2000-12-08 2003-09-05 Commissariat Energie Atomique Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses
US7256104B2 (en) * 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus
FR2855908B1 (fr) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention d'une structure comprenant au moins un substrat et une couche ultramince
WO2006117900A1 (ja) * 2005-04-26 2006-11-09 Sharp Kabushiki Kaisha 半導体装置の製造方法及び半導体装置
TW200733386A (en) * 2005-11-29 2007-09-01 Sharp Kk Semiconductor device
JP4380709B2 (ja) * 2007-01-31 2009-12-09 セイコーエプソン株式会社 半導体装置の製造方法
KR100875432B1 (ko) * 2007-05-31 2008-12-22 삼성모바일디스플레이주식회사 다결정 실리콘층의 제조 방법, 이를 이용하여 형성된박막트랜지스터, 그의 제조방법 및 이를 포함하는유기전계발광표시장치

Also Published As

Publication number Publication date
JP2015515122A (ja) 2015-05-21
JP6193271B2 (ja) 2017-09-06
KR20140129116A (ko) 2014-11-06
TW201347033A (zh) 2013-11-16
WO2013124719A1 (en) 2013-08-29
KR102031725B1 (ko) 2019-10-14
TWI588886B (zh) 2017-06-21
CN104115259A (zh) 2014-10-22
CN104115259B (zh) 2017-03-22

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