FR2987936B1 - Procedes de fabrication de fines couches de materiau semi-conducteur cristallin, et structures et dispositifs connexes - Google Patents

Procedes de fabrication de fines couches de materiau semi-conducteur cristallin, et structures et dispositifs connexes

Info

Publication number
FR2987936B1
FR2987936B1 FR1252148A FR1252148A FR2987936B1 FR 2987936 B1 FR2987936 B1 FR 2987936B1 FR 1252148 A FR1252148 A FR 1252148A FR 1252148 A FR1252148 A FR 1252148A FR 2987936 B1 FR2987936 B1 FR 2987936B1
Authority
FR
France
Prior art keywords
methods
devices
semiconductor material
crystalline semiconductor
related structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1252148A
Other languages
English (en)
Other versions
FR2987936A1 (fr
Inventor
Mariam Sadaka
Ionut Radu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec Silicon on Insulator Technologies SA
Original Assignee
Soitec Silicon on Insulator Technologies SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon on Insulator Technologies SA filed Critical Soitec Silicon on Insulator Technologies SA
Priority to FR1252148A priority Critical patent/FR2987936B1/fr
Priority claimed from KR1020147024957A external-priority patent/KR102031725B1/ko
Publication of FR2987936A1 publication Critical patent/FR2987936A1/fr
Application granted granted Critical
Publication of FR2987936B1 publication Critical patent/FR2987936B1/fr
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
FR1252148A 2012-03-09 2012-03-09 Procedes de fabrication de fines couches de materiau semi-conducteur cristallin, et structures et dispositifs connexes Active FR2987936B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR1252148A FR2987936B1 (fr) 2012-03-09 2012-03-09 Procedes de fabrication de fines couches de materiau semi-conducteur cristallin, et structures et dispositifs connexes

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
FR1252148A FR2987936B1 (fr) 2012-03-09 2012-03-09 Procedes de fabrication de fines couches de materiau semi-conducteur cristallin, et structures et dispositifs connexes
KR1020147024957A KR102031725B1 (ko) 2012-02-22 2013-02-01 결정질 반도체 재료의 박층 제공방법 및 관련 구조 및 장치
JP2014558222A JP6193271B2 (ja) 2012-02-22 2013-02-01 結晶半導体材料の薄層を設ける方法、ならびに関連する構造体およびデバイス
SG11201404576TA SG11201404576TA (en) 2012-02-22 2013-02-01 Methods of providing thin layers of crystalline semiconductor material, and related structures and devices
PCT/IB2013/000139 WO2013124719A1 (fr) 2012-02-22 2013-02-01 Procédés permettant d'obtenir des couches minces de matériau semi-conducteur cristallin, et structures et dispositifs associés
CN201380009416.3A CN104115259B (zh) 2012-02-22 2013-02-01 设置晶体半导体材料薄层的方法以及有关的结构和器件
TW102106329A TWI588886B (zh) 2012-02-22 2013-02-22 製造半導體裝置之方法

Publications (2)

Publication Number Publication Date
FR2987936A1 FR2987936A1 (fr) 2013-09-13
FR2987936B1 true FR2987936B1 (fr) 2016-11-04

Family

ID=46489375

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1252148A Active FR2987936B1 (fr) 2012-03-09 2012-03-09 Procedes de fabrication de fines couches de materiau semi-conducteur cristallin, et structures et dispositifs connexes

Country Status (1)

Country Link
FR (1) FR2987936B1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223081A (en) * 1991-07-03 1993-06-29 Doan Trung T Method for roughening a silicon or polysilicon surface for a semiconductor substrate
KR100199064B1 (ko) * 1995-10-17 1999-07-01 구자홍 박막 트랜지스터 제조방법
US7256104B2 (en) * 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus

Also Published As

Publication number Publication date
FR2987936A1 (fr) 2013-09-13

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