SG10202010251PA - Semiconductor memory device and method of operating the same - Google Patents

Semiconductor memory device and method of operating the same

Info

Publication number
SG10202010251PA
SG10202010251PA SG10202010251PA SG10202010251PA SG10202010251PA SG 10202010251P A SG10202010251P A SG 10202010251PA SG 10202010251P A SG10202010251P A SG 10202010251PA SG 10202010251P A SG10202010251P A SG 10202010251PA SG 10202010251P A SG10202010251P A SG 10202010251PA
Authority
SG
Singapore
Prior art keywords
operating
same
memory device
semiconductor memory
semiconductor
Prior art date
Application number
SG10202010251PA
Other languages
English (en)
Inventor
Kyung Park Jong
Hyun Seo Ji
Original Assignee
Sk Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sk Hynix Inc filed Critical Sk Hynix Inc
Publication of SG10202010251PA publication Critical patent/SG10202010251PA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
SG10202010251PA 2019-11-05 2020-10-15 Semiconductor memory device and method of operating the same SG10202010251PA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190140458A KR20210054376A (ko) 2019-11-05 2019-11-05 반도체 메모리 장치 및 그 동작 방법

Publications (1)

Publication Number Publication Date
SG10202010251PA true SG10202010251PA (en) 2021-06-29

Family

ID=75686559

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10202010251PA SG10202010251PA (en) 2019-11-05 2020-10-15 Semiconductor memory device and method of operating the same

Country Status (5)

Country Link
US (1) US11328766B2 (zh)
KR (1) KR20210054376A (zh)
CN (1) CN112786093B (zh)
SG (1) SG10202010251PA (zh)
TW (1) TW202119421A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230041949A1 (en) * 2021-08-05 2023-02-09 Macronix International Co., Ltd. Programming memory devices

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7652929B2 (en) * 2007-09-17 2010-01-26 Sandisk Corporation Non-volatile memory and method for biasing adjacent word line for verify during programming
US7995388B1 (en) * 2008-08-05 2011-08-09 Anobit Technologies Ltd. Data storage using modified voltages
US8199579B2 (en) * 2009-09-16 2012-06-12 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
KR101798013B1 (ko) 2010-12-30 2017-11-16 삼성전자주식회사 비휘발성 메모리 장치의 프로그램 방법
US8526233B2 (en) * 2011-05-23 2013-09-03 Sandisk Technologies Inc. Ramping pass voltage to enhance channel boost in memory device, with optional temperature compensation
KR102106866B1 (ko) * 2013-01-29 2020-05-06 삼성전자주식회사 멀티레벨 불휘발성 메모리 장치 및 프로그램 방법
KR20160061765A (ko) 2014-11-24 2016-06-01 에스케이하이닉스 주식회사 반도체 장치
KR20160120990A (ko) * 2015-04-09 2016-10-19 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그것의 동작 방법
KR102274280B1 (ko) * 2015-06-22 2021-07-07 삼성전자주식회사 불휘발성 메모리 장치의 동작 방법
KR102498248B1 (ko) * 2016-02-04 2023-02-10 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그것의 동작 방법
KR102572610B1 (ko) * 2016-05-17 2023-09-01 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 동작 방법
KR20180013127A (ko) * 2016-07-28 2018-02-07 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이의 동작 방법
KR102491134B1 (ko) * 2018-09-21 2023-01-25 에스케이하이닉스 주식회사 메모리 시스템, 그것의 동작 방법 및 비휘발성 메모리 장치
KR102643666B1 (ko) * 2018-11-23 2024-03-06 에스케이하이닉스 주식회사 반도체 장치 및 그 동작 방법

Also Published As

Publication number Publication date
US11328766B2 (en) 2022-05-10
US20210134359A1 (en) 2021-05-06
KR20210054376A (ko) 2021-05-13
CN112786093A (zh) 2021-05-11
TW202119421A (zh) 2021-05-16
CN112786093B (zh) 2024-05-17

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