SE409779B - Sett att framstella en halvledaranordning - Google Patents
Sett att framstella en halvledaranordningInfo
- Publication number
- SE409779B SE409779B SE7610157A SE7610157A SE409779B SE 409779 B SE409779 B SE 409779B SE 7610157 A SE7610157 A SE 7610157A SE 7610157 A SE7610157 A SE 7610157A SE 409779 B SE409779 B SE 409779B
- Authority
- SE
- Sweden
- Prior art keywords
- manufacture
- way
- semiconductor device
- semiconductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/147—Silicides
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL7510903A NL7510903A (nl) | 1975-09-17 | 1975-09-17 | Werkwijze voor het vervaardigen van een halfgelei- derinrichting, en inrichting vervaardigd volgens de werkwijze. |
Publications (2)
Publication Number | Publication Date |
---|---|
SE7610157L SE7610157L (sv) | 1977-03-18 |
SE409779B true SE409779B (sv) | 1979-09-03 |
Family
ID=19824476
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE7610157A SE409779B (sv) | 1975-09-17 | 1976-09-14 | Sett att framstella en halvledaranordning |
Country Status (11)
Country | Link |
---|---|
US (1) | US4080719A (sv) |
JP (1) | JPS5236477A (sv) |
AU (1) | AU504189B2 (sv) |
CA (1) | CA1055618A (sv) |
CH (1) | CH610142A5 (sv) |
DE (1) | DE2640525C2 (sv) |
FR (1) | FR2325192A1 (sv) |
GB (1) | GB1543235A (sv) |
IT (1) | IT1068506B (sv) |
NL (1) | NL7510903A (sv) |
SE (1) | SE409779B (sv) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4878099A (en) * | 1982-12-08 | 1989-10-31 | International Rectifier Corporation | Metallizing system for semiconductor wafers |
Families Citing this family (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4078947A (en) * | 1976-08-05 | 1978-03-14 | International Business Machines Corporation | Method for forming a narrow channel length MOS field effect transistor |
US4180596A (en) * | 1977-06-30 | 1979-12-25 | International Business Machines Corporation | Method for providing a metal silicide layer on a substrate |
US4231051A (en) * | 1978-06-06 | 1980-10-28 | Rockwell International Corporation | Process for producing minimal geometry devices for VSLI applications utilizing self-aligned gates and self-aligned contacts, and resultant structures |
US4234362A (en) * | 1978-11-03 | 1980-11-18 | International Business Machines Corporation | Method for forming an insulator between layers of conductive material |
US4210465A (en) * | 1978-11-20 | 1980-07-01 | Ncr Corporation | CISFET Processing including simultaneous implantation of spaced polycrystalline silicon regions and non-memory FET channel |
US4276557A (en) * | 1978-12-29 | 1981-06-30 | Bell Telephone Laboratories, Incorporated | Integrated semiconductor circuit structure and method for making it |
US4364166A (en) * | 1979-03-01 | 1982-12-21 | International Business Machines Corporation | Semiconductor integrated circuit interconnections |
NL8002609A (nl) * | 1979-06-11 | 1980-12-15 | Gen Electric | Samengestelde geleidende structuur en werkwijze voor het vervaardigen daarvan. |
FR2461360A1 (fr) * | 1979-07-10 | 1981-01-30 | Thomson Csf | Procede de fabrication d'un transistor a effet de champ du type dmos a fonctionnement vertical et transistor obtenu par ce procede |
US4305200A (en) * | 1979-11-06 | 1981-12-15 | Hewlett-Packard Company | Method of forming self-registering source, drain, and gate contacts for FET transistor structures |
JPS5671976A (en) * | 1979-11-19 | 1981-06-15 | Seiko Epson Corp | Preparation method of mos type semiconductor system |
JPS5679473A (en) * | 1979-11-30 | 1981-06-30 | Mitsubishi Electric Corp | Preparing method of metal gate film |
US4287661A (en) * | 1980-03-26 | 1981-09-08 | International Business Machines Corporation | Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation |
US5202574A (en) * | 1980-05-02 | 1993-04-13 | Texas Instruments Incorporated | Semiconductor having improved interlevel conductor insulation |
JPS56161674A (en) * | 1980-05-16 | 1981-12-12 | Nec Corp | Metal oxide semiconductor device |
JPS5735370A (en) * | 1980-08-12 | 1982-02-25 | Nec Corp | Semiconductor device |
NL186352C (nl) * | 1980-08-27 | 1990-11-01 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
US4622735A (en) * | 1980-12-12 | 1986-11-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing a semiconductor device utilizing self-aligned silicide regions |
JPS57167677A (en) * | 1981-03-31 | 1982-10-15 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
JPS582068A (ja) * | 1981-06-26 | 1983-01-07 | Toshiba Corp | 半導体装置およびその製造方法 |
US4441247A (en) * | 1981-06-29 | 1984-04-10 | Intel Corporation | Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate |
JPS584924A (ja) * | 1981-07-01 | 1983-01-12 | Hitachi Ltd | 半導体装置の電極形成方法 |
US4445266A (en) * | 1981-08-07 | 1984-05-01 | Mostek Corporation | MOSFET Fabrication process for reducing overlap capacitance and lowering interconnect impedance |
DE3132809A1 (de) * | 1981-08-19 | 1983-03-10 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von integrierten mos-feldeffekttransistoren, insbesondere von komplementaeren mos-feldeffekttransistorenschaltungen mit einer aus metallsiliziden bestehenden zusaetzlichen leiterbahnebene |
DE3211761A1 (de) * | 1982-03-30 | 1983-10-06 | Siemens Ag | Verfahren zum herstellen von integrierten mos-feldeffekttransistorschaltungen in siliziumgate-technologie mit silizid beschichteten diffusionsgebieten als niederohmige leiterbahnen |
US4485550A (en) * | 1982-07-23 | 1984-12-04 | At&T Bell Laboratories | Fabrication of schottky-barrier MOS FETs |
FR2533371B1 (fr) * | 1982-09-21 | 1985-12-13 | Thomson Csf | Structure de grille pour circuit integre comportant des elements du type grille-isolant-semi-conducteur et procede de realisation d'un circuit integre utilisant une telle structure |
US4521952A (en) * | 1982-12-02 | 1985-06-11 | International Business Machines Corporation | Method of making integrated circuits using metal silicide contacts |
DE3304588A1 (de) * | 1983-02-10 | 1984-08-16 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von mos-transistoren mit flachen source/drain-gebieten, kurzen kanallaengen und einer selbstjustierten, aus einem metallsilizid bestehenden kontaktierungsebene |
DE3304642A1 (de) * | 1983-02-10 | 1984-08-16 | Siemens AG, 1000 Berlin und 8000 München | Integrierte halbleiterschaltung mit bipolartransistor-strukturen und verfahren zu ihrer herstellung |
US4503601A (en) * | 1983-04-18 | 1985-03-12 | Ncr Corporation | Oxide trench structure for polysilicon gates and interconnects |
US4545116A (en) * | 1983-05-06 | 1985-10-08 | Texas Instruments Incorporated | Method of forming a titanium disilicide |
FR2555365B1 (fr) * | 1983-11-22 | 1986-08-29 | Efcis | Procede de fabrication de circuit integre avec connexions de siliciure de tantale et circuit integre realise selon ce procede |
JPS60130844A (ja) * | 1983-12-20 | 1985-07-12 | Toshiba Corp | 半導体装置の製造方法 |
US4641417A (en) * | 1984-06-25 | 1987-02-10 | Texas Instruments Incorporated | Process for making molybdenum gate and titanium silicide contacted MOS transistors in VLSI semiconductor devices |
US5098854A (en) * | 1984-07-09 | 1992-03-24 | National Semiconductor Corporation | Process for forming self-aligned silicide base contact for bipolar transistor |
US4609568A (en) * | 1984-07-27 | 1986-09-02 | Fairchild Camera & Instrument Corporation | Self-aligned metal silicide process for integrated circuits having self-aligned polycrystalline silicon electrodes |
US5045916A (en) * | 1985-01-22 | 1991-09-03 | Fairchild Semiconductor Corporation | Extended silicide and external contact technology |
US5227316A (en) * | 1985-01-22 | 1993-07-13 | National Semiconductor Corporation | Method of forming self aligned extended base contact for a bipolar transistor having reduced cell size |
US5061986A (en) * | 1985-01-22 | 1991-10-29 | National Semiconductor Corporation | Self-aligned extended base contact for a bipolar transistor having reduced cell size and improved electrical characteristics |
US4635347A (en) * | 1985-03-29 | 1987-01-13 | Advanced Micro Devices, Inc. | Method of fabricating titanium silicide gate electrodes and interconnections |
US4965218A (en) * | 1985-10-21 | 1990-10-23 | Itt Corporation | Self-aligned gate realignment employing planarizing overetch |
NL8800222A (nl) * | 1988-01-29 | 1989-08-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op zelfregistrerende wijze metaalsilicide wordt aangebracht. |
JPH01298765A (ja) * | 1988-05-27 | 1989-12-01 | Fujitsu Ltd | 半導体装置及びその製造方法 |
WO1990001795A1 (en) * | 1988-08-12 | 1990-02-22 | Micron Technology, Inc. | Self-aligned silicide process in forming semiconductor sidewalls |
KR920003461A (ko) * | 1990-07-30 | 1992-02-29 | 김광호 | 접촉영역 형성방법 및 그를 이용한 반도체장치의 제조방법 |
US6107194A (en) * | 1993-12-17 | 2000-08-22 | Stmicroelectronics, Inc. | Method of fabricating an integrated circuit |
US6284584B1 (en) | 1993-12-17 | 2001-09-04 | Stmicroelectronics, Inc. | Method of masking for periphery salicidation of active regions |
JPH07263684A (ja) * | 1994-03-25 | 1995-10-13 | Mitsubishi Electric Corp | 電界効果トランジスタの製造方法 |
US5545574A (en) * | 1995-05-19 | 1996-08-13 | Motorola, Inc. | Process for forming a semiconductor device having a metal-semiconductor compound |
JP3389075B2 (ja) * | 1997-10-01 | 2003-03-24 | 株式会社東芝 | 半導体装置の製造方法 |
US6894355B1 (en) * | 2002-01-11 | 2005-05-17 | Advanced Micro Devices, Inc. | Semiconductor device with silicide source/drain and high-K dielectric |
US6599831B1 (en) * | 2002-04-30 | 2003-07-29 | Advanced Micro Devices, Inc. | Metal gate electrode using silicidation and method of formation thereof |
JP2005150217A (ja) * | 2003-11-12 | 2005-06-09 | Fujitsu Ltd | 半導体装置及びその製造方法 |
KR100550345B1 (ko) * | 2004-10-11 | 2006-02-08 | 삼성전자주식회사 | 반도체 장치의 실리사이드막 형성방법 |
JP4733609B2 (ja) * | 2006-10-10 | 2011-07-27 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US8994489B2 (en) | 2011-10-19 | 2015-03-31 | Micron Technology, Inc. | Fuses, and methods of forming and using fuses |
US8723155B2 (en) | 2011-11-17 | 2014-05-13 | Micron Technology, Inc. | Memory cells and integrated devices |
US9252188B2 (en) | 2011-11-17 | 2016-02-02 | Micron Technology, Inc. | Methods of forming memory cells |
US9553262B2 (en) | 2013-02-07 | 2017-01-24 | Micron Technology, Inc. | Arrays of memory cells and methods of forming an array of memory cells |
US9881971B2 (en) | 2014-04-01 | 2018-01-30 | Micron Technology, Inc. | Memory arrays |
US9343506B2 (en) | 2014-06-04 | 2016-05-17 | Micron Technology, Inc. | Memory arrays with polygonal memory cells having specific sidewall orientations |
CN112928153B (zh) * | 2019-12-05 | 2023-07-04 | 中芯国际集成电路制造(天津)有限公司 | 半导体结构及其形成方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3745647A (en) * | 1970-10-07 | 1973-07-17 | Rca Corp | Fabrication of semiconductor devices |
US3699646A (en) * | 1970-12-28 | 1972-10-24 | Intel Corp | Integrated circuit structure and method for making integrated circuit structure |
US3761327A (en) * | 1971-03-19 | 1973-09-25 | Itt | Planar silicon gate mos process |
NL7204543A (sv) * | 1971-04-08 | 1972-10-10 | ||
NL7205000A (sv) * | 1972-04-14 | 1973-10-16 | ||
US3777364A (en) * | 1972-07-31 | 1973-12-11 | Fairchild Camera Instr Co | Methods for forming metal/metal silicide semiconductor device interconnect system |
JPS5431793B2 (sv) * | 1973-10-12 | 1979-10-09 | ||
US3958323A (en) * | 1975-04-29 | 1976-05-25 | International Business Machines Corporation | Three mask self aligned IGFET fabrication process |
-
1975
- 1975-09-17 NL NL7510903A patent/NL7510903A/xx not_active Application Discontinuation
-
1976
- 1976-09-09 DE DE2640525A patent/DE2640525C2/de not_active Expired
- 1976-09-09 US US05/721,661 patent/US4080719A/en not_active Expired - Lifetime
- 1976-09-13 AU AU17658/76A patent/AU504189B2/en not_active Expired
- 1976-09-14 GB GB38015/76A patent/GB1543235A/en not_active Expired
- 1976-09-14 CH CH1166776A patent/CH610142A5/xx not_active IP Right Cessation
- 1976-09-14 CA CA261,160A patent/CA1055618A/en not_active Expired
- 1976-09-14 SE SE7610157A patent/SE409779B/sv unknown
- 1976-09-14 IT IT27191/76A patent/IT1068506B/it active
- 1976-09-15 FR FR7627707A patent/FR2325192A1/fr active Granted
- 1976-09-17 JP JP51110883A patent/JPS5236477A/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4878099A (en) * | 1982-12-08 | 1989-10-31 | International Rectifier Corporation | Metallizing system for semiconductor wafers |
Also Published As
Publication number | Publication date |
---|---|
DE2640525C2 (de) | 1985-06-20 |
JPS5236477A (en) | 1977-03-19 |
US4080719A (en) | 1978-03-28 |
IT1068506B (it) | 1985-03-21 |
NL7510903A (nl) | 1977-03-21 |
DE2640525A1 (de) | 1977-03-31 |
GB1543235A (en) | 1979-03-28 |
CH610142A5 (sv) | 1979-03-30 |
AU504189B2 (en) | 1979-10-04 |
CA1055618A (en) | 1979-05-29 |
FR2325192B1 (sv) | 1982-11-12 |
AU1765876A (en) | 1978-03-23 |
FR2325192A1 (fr) | 1977-04-15 |
SE7610157L (sv) | 1977-03-18 |
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