WO1990001795A1 - Self-aligned silicide process in forming semiconductor sidewalls - Google Patents

Self-aligned silicide process in forming semiconductor sidewalls Download PDF

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Publication number
WO1990001795A1
WO1990001795A1 PCT/US1988/002726 US8802726W WO9001795A1 WO 1990001795 A1 WO1990001795 A1 WO 1990001795A1 US 8802726 W US8802726 W US 8802726W WO 9001795 A1 WO9001795 A1 WO 9001795A1
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Prior art keywords
polysilicon
layer
nitride
titanium
depositing
Prior art date
Application number
PCT/US1988/002726
Other languages
French (fr)
Inventor
Clifford A. Maxwell
Tyler A. Lowrey
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Micron Technology, Inc.
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Publication date
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Priority to PCT/US1988/002726 priority Critical patent/WO1990001795A1/en
Publication of WO1990001795A1 publication Critical patent/WO1990001795A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Definitions

  • This invention relates to the manufacture of semiconductor circuit devices. More specifically the invention relates to manufacture of multilayer semiconductor circuit devices in which isolation of levels of polysilicon is achieved.
  • the invention uses various materials which are electrically either conductive, insulative or semiconductive, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor".
  • semiconductor materials One of the semiconductor materials used is silicon, which appears as single crystal silicon and polycrystalline silicon material, referred to as "poly" throughout this disclosure.
  • Titanium suicide local interconnects have been extensively used to make contact to N+/P+ active area and to act as local routings connecting gates and N+/P+ active area in VLSI circuits.
  • silicon is sputtered onto a surface which has been coated with a thin titanium blanket, and a local interconnect mask is used to define the interconnection pattern in the polysilicon.
  • This approach requires a special etch that has high selectivity to the underlying refractory metal and it is often difficult to obtain good uniformity in the thin polysilicon layer prepared by the sputtering technique.
  • TiN one of the by-products in the silicidation process
  • Other techniques have been applied in order to establish electrical connection to trench structures, in which silicon is reacted with a refractory metal in order to form a conductive suicide strap across a trench.
  • DRAMs dynamic random access memory semiconductor devices
  • metallization layers eg., aluminum
  • the proposed iSi2 interconnect provides a low resistance self-aligned contact procedure for the bitline formation, and greatly reduces the spacing necessary between the access transistors, thus enabling a more efficient/compact layout of the memory cell.
  • Suicide coatings increase the speed and efficiency of DRAMs and similar semiconductors by reducing sheet resistance of silicon circuit elements, and consequently reducing the RC delay of circuits including these elements. This can be seen by examining typical sheet resistances, given in ohms per square, although the specific circuit configuration would determine the exact sheet resistances.
  • Polysilicon has a typical sheet resistance of approximately 20 ⁇ /square.
  • N+ material typically exhibits a sheet resistance of 35 ⁇ /square, and P+ material typically exhibits a sheet resistance of 60 ⁇ /square.
  • TiSi2 typically has a sheet resistance of less than 1 ⁇ /square, so that silicon material coated with the TiSi2 would also have a sheet resistance of less than 1 ⁇ /square.
  • This invention relates to the salicidation of conductive levels on DRAM semiconductor devices.
  • silicidation is performed after transistor gates are defined, so that the suicide interconnects are self aligned. This proceedure also permits the transistor source and drains to be established prior to the sputtering of refractory metal.
  • a double level poly salicide process would require capping off the second level poly with oxide; thus not allowing that level to be salicide strapped. It is therefore desired to provide a salicide process in which the second level of poly may be strapped. While these needs initially are being addressed for 1Meg and 4Meg DRAMs, it is anticipated that the inventive techniques will be used for higher and lower capacity DRAMs.
  • VLSI very large scale integrated circuit
  • This invention relates to the salicidation of conductive levels on DRAM semiconductor devices. It provides for a consistant and efficient sidewall isolation of a later level of polysilicon thus allowing this level to be strapped with salicide as well as previous poly levels and active areas. The salicidation of all conductive levels reduces sheet resistance and improves speed.
  • a first nitride level is deposited, over a first poly layer, for use as cell dielectric.
  • a second poly layer is deposited over the nitride level, followed by a second level of nitride.
  • the second poly layer and the second lever of nitride are patterned with a photoresist material and etched, by first etching the nitride then etching the poly.
  • the resist is then removed and the surface is exposed to thermal oxidation.
  • the nitride on top of poly 2 and the original nitride exposed after the poly 2 etch are removed simultaneously in a selective etch.
  • the surface of active areas, including both poly layers, are now free to be exposed to a selective salicide formation process.
  • a poly pattern is established, along . with source and drain implants.
  • Oxide is established along poly sidewalls in a manner which permits sidewall isolation.
  • a refractory metal such as titanium is sputtered onto the top surface of the wafer and is sintered in a nitrogen atmosphere.
  • TiSi2 is formed where the titanium is exposed to elemental silicon, while oxide patterns result in the titanium reacting only with the nitrogen. The titanium nitride and any unreacted titanium may then be selectively etched, leaving a desired pattern of TiSi2 «
  • the invention makes use of a nitride-poly-nitride stack to isolate a region of the poly which is subsequently oxidized. Nitride at the bottom of the sandwich protects all other regions from this oxidation step. Nitride on top protects the poly upper surface from the same oxidation, so that only the sidewall of the poly is oxidized.
  • the nitride barrier on the upper surface of the later level poly inhibits oxidation and allows this poly to be strapped with salicide while the sidewall oxide protects against shorts by inhibiting salicidation at the sidewall.
  • the invention allows for the salicidation of a second level of poly in addition to the previous poly level and the active area, and provides the advantage of an improved sidewall isolation over prior art CVD oxide spacers.
  • oxide sidewall produced by this process is of uniform thickness and does not thin out at the bottom as an oxide spacer could. This process avoids problems seen with oxide spacers associated with the poly 2 sidewall profile, in which low angle profiles were not fully covered after spacer formation.
  • Eliminating the second spacer deposition and etch avoids detrimental field isolation oxide thinning (spacer 2 overetch) that can compromise high voltage operation and performance. Also during overetch, recession of the isolation LOCOS edge may occur. This LOCOS recession can lead to salicide spiking through the diffusion junction due to the effective junction depth reduction at the junction/LOCOS sidewall. In practice, the second spacer over- etch acts to limit the minimum available diffusion junction depth. This restricts scaling of the transistor devices. 4) Eliminating the second spacer etch avoids problems associated with source/drain diffusion silicon etching during the spacer overetch. This silicon etch results from finite selectivity of the anisotropic dry etch used during spacer formation.
  • Relatively easy steps are required to facilitate salicidation (silicidation) of poly 2; that is extra nitride deposition and etch, and extra steam oxidation. This contrasts with the difficult steps associated with spacer formation. Spacer oxide formation requires more steps than this nitride-poly-nitride process and can result in poly 2-to-active region shorts under certain conditions.
  • Figure 1 shows a cross-sectional view of a poly 1 and poly 2, indicating the nitride-poly-nitride stack
  • Figure 2 shows the wafer of Figure 1 after poly 2 pattern and etch
  • Figure 3 shows resist strip and the subsequent sidewall oxidation
  • Figure 4 shows the resulting structure after nitride etch
  • Figure 5 shows a blanket layer of titanium sputtered onto the surface of the wafer
  • Figure 6 shows the wafer after salicide.
  • a wafer 13 is processed through a series of steps which result in a circuit pattern being formed on the wafer as a part of the wafer.
  • the initial preparation is generally standard preparation used to prepare the wafer for the processing.
  • oxide which includes gate oxide 15, is grown on the wafer 13, and the underlying portion of the wafer forms a substrate.
  • a first level of polysilicon referred to as poly 1
  • poly 1 A first level of polysilicon, referred to as poly 1
  • the oxide is later stripped, but source/drain reox 23 remains.
  • An oxide-spacer 25 is used to offset the poly 1 , which forms a transistor gate structure, from source and drain regions.
  • the oxide-spacer helps to prevent shorting of the source/drain regions to the edge of the transistor gate during salicide formation.
  • a thin blanket layer of nitride 27 is deposited on top of the surface of the wafer 13.
  • the nitride 27 is preferably deposited on the surface by chemical vapor deposition (CVD) , although the nitride 27 may be grown or deposited in any of a variety of manners.
  • This nitride layer 27 forms cell dielectric and electrically isolates the second poly layer (poly 2) from the substrate N+ region. -
  • the Poly 2 deposition is followed by thermal phosphorus doping using PH3 gas. This is preferrably done at a temperature of approximately 900 degrees C with a range of temperature between 700 and 1100 degrees C.
  • the second polysilicon layer (poly 2) deposition is followed by a second level of nitride 37.
  • the second level of nitride and poly 2 are patterned with a photoresist material 39 and etched, first etching the nitride then etching poly 2, as shown in Figure 2.
  • the resist 39 is then removed and the surface of the wafer 13 is exposed to thermal oxidation to form a sidewall oxide * layer 41.
  • a short oxide etch follows to clear a thin oxide which is grown on the exposed surfaces, of the nitride layers 27, 37. This is followed by a nitride etch which clears the second nitride layer 37 from the surface of poly 2 and any exposed nitride 27 from the surface of the remaining circuitry, as shown in Figure 4.
  • the surface of the wafer 13 may now be exposed to a selective silicide formation process.
  • a blanket layer of ⁇ 600A titanium is sputtered onto the surface of the wafer 13, as shown in Figure 5.
  • a low temperature ( ⁇ 650C) sinter then is performed in N ambient.
  • titanium reacts with the silicon to form titanium silicide, primarily TiSi2.
  • the titanium does not react with the oxide (Si ⁇ 2), but instead becomes TiN or remains as elemental titanium.
  • the location of the spacer oxide 25 and the sidewall oxide 41 coincide with locations where silicide formation is not desired, and where TiSi does not form.
  • the TiN and unreacted titanium are washed from the wafer 13 in a salicide piranha, which is a wet etch which leaves the TiSi2 in place, as shown in Figure 6.
  • a silicide anneal ( ⁇ 800C) is performed to lower the sheet resistivity of the TiSi2 layer.

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Abstract

Salicidation of conductive levels in DRAM semiconductor devices is described. A poly I pattern is established, along with source drain implants. Oxide (25) is established along poly sidewalls in a manner which permits sidewall isolation. An isolating nitride (27) is formed, followed by a poly II pattern covered with another isolating nitride (37). An exposed sidewall of the poly II is oxidized to form oxide pattern (41). A refractory metal, such as titanium, is sputtered onto the top surface of the wafer and is sintered in a nitrogen atmosphere. TiSi2 is formed where the titanium is exposed to elemental silicon, while oxide patterns result in the titanium reacting only with the nitrogen. The titanium nitride and any unreacted titanium may then be selectively etched, leaving a desired pattern of TiSi2.

Description

SELF-ALIGNED SILICIDE PROCESS IN FORMING SEMICONDUCTOR SIDEWALLS
Field of the Invention
This invention relates to the manufacture of semiconductor circuit devices. More specifically the invention relates to manufacture of multilayer semiconductor circuit devices in which isolation of levels of polysilicon is achieved.
Background of the Invention
The invention uses various materials which are electrically either conductive, insulative or semiconductive, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". One of the semiconductor materials used is silicon, which appears as single crystal silicon and polycrystalline silicon material, referred to as "poly" throughout this disclosure.
Sidewall isolation of all polysilicon layers is necessary in the construction of high density high performance semiconductor circuit devices utilizing salicide process techniques. One prior art process is to form a sidewall oxide spacer using an oxide deposition and anisotropic etchback technique. Other approaches oxidize the poly 2, leaving the top and sidewall of the second level poly ("poly 2") to be capped off with oxide. Sheet resistance would then be high for poly 2. The several steps required by spacer oxide formation can result in poly 2 to active region shorts under certain conditions.
Titanium suicide local interconnects have been extensively used to make contact to N+/P+ active area and to act as local routings connecting gates and N+/P+ active area in VLSI circuits. In one process, silicon is sputtered onto a surface which has been coated with a thin titanium blanket, and a local interconnect mask is used to define the interconnection pattern in the polysilicon. This approach requires a special etch that has high selectivity to the underlying refractory metal and it is often difficult to obtain good uniformity in the thin polysilicon layer prepared by the sputtering technique. In another system, TiN (one of the by-products in the silicidation process) is used as the local interconnect material, even though the resistivity of TiN is much higher than iSi2. Other techniques have been applied in order to establish electrical connection to trench structures, in which silicon is reacted with a refractory metal in order to form a conductive suicide strap across a trench.
Conventional processes for establishing interconnects on dynamic random access memory semiconductor devices (DRAMs) have included the use of metallization layers (eg., aluminum), which form bitlines and other local interconnects via a non self-aligned contact scheme, limiting the minimal spacing allowed between the access transistors. The proposed iSi2 interconnect provides a low resistance self-aligned contact procedure for the bitline formation, and greatly reduces the spacing necessary between the access transistors, thus enabling a more efficient/compact layout of the memory cell.
Suicide coatings increase the speed and efficiency of DRAMs and similar semiconductors by reducing sheet resistance of silicon circuit elements, and consequently reducing the RC delay of circuits including these elements. This can be seen by examining typical sheet resistances, given in ohms per square, although the specific circuit configuration would determine the exact sheet resistances. Polysilicon has a typical sheet resistance of approximately 20Ω/square. N+ material typically exhibits a sheet resistance of 35Ω/square, and P+ material typically exhibits a sheet resistance of 60Ω/square. TiSi2 typically has a sheet resistance of less than 1 Ω/square, so that silicon material coated with the TiSi2 would also have a sheet resistance of less than 1 Ω/square.
This invention relates to the salicidation of conductive levels on DRAM semiconductor devices. In the salicide process, silicidation is performed after transistor gates are defined, so that the suicide interconnects are self aligned. This proceedure also permits the transistor source and drains to be established prior to the sputtering of refractory metal. Under the prior art process limitations, a double level poly salicide process would require capping off the second level poly with oxide; thus not allowing that level to be salicide strapped. It is therefore desired to provide a salicide process in which the second level of poly may be strapped. While these needs initially are being addressed for 1Meg and 4Meg DRAMs, it is anticipated that the inventive techniques will be used for higher and lower capacity DRAMs.
It is also anticipated that these needs would be used for other very large scale integrated circuit (VLSI) semiconductor devices.
Summary of the Invention
This invention relates to the salicidation of conductive levels on DRAM semiconductor devices. It provides for a consistant and efficient sidewall isolation of a later level of polysilicon thus allowing this level to be strapped with salicide as well as previous poly levels and active areas. The salicidation of all conductive levels reduces sheet resistance and improves speed.
In accordance with the present invention, a first nitride level is deposited, over a first poly layer, for use as cell dielectric. A second poly layer is deposited over the nitride level, followed by a second level of nitride. The second poly layer and the second lever of nitride are patterned with a photoresist material and etched, by first etching the nitride then etching the poly. The resist is then removed and the surface is exposed to thermal oxidation. Finally, the nitride on top of poly 2 and the original nitride exposed after the poly 2 etch are removed simultaneously in a selective etch. The surface of active areas, including both poly layers, are now free to be exposed to a selective salicide formation process.
In the salicide formation process, a poly pattern is established, along . with source and drain implants. Oxide is established along poly sidewalls in a manner which permits sidewall isolation. A refractory metal, such as titanium is sputtered onto the top surface of the wafer and is sintered in a nitrogen atmosphere. TiSi2 is formed where the titanium is exposed to elemental silicon, while oxide patterns result in the titanium reacting only with the nitrogen. The titanium nitride and any unreacted titanium may then be selectively etched, leaving a desired pattern of TiSi2«
The invention makes use of a nitride-poly-nitride stack to isolate a region of the poly which is subsequently oxidized. Nitride at the bottom of the sandwich protects all other regions from this oxidation step. Nitride on top protects the poly upper surface from the same oxidation, so that only the sidewall of the poly is oxidized.
The nitride barrier on the upper surface of the later level poly inhibits oxidation and allows this poly to be strapped with salicide while the sidewall oxide protects against shorts by inhibiting salicidation at the sidewall.
The invention allows for the salicidation of a second level of poly in addition to the previous poly level and the active area, and provides the advantage of an improved sidewall isolation over prior art CVD oxide spacers.
The nitride-poly-nitride stack offers several advantages over previous process methods:
1 ) The oxide sidewall produced by this process is of uniform thickness and does not thin out at the bottom as an oxide spacer could. This process avoids problems seen with oxide spacers associated with the poly 2 sidewall profile, in which low angle profiles were not fully covered after spacer formation.
2) Spacer formation for poly" 2 would result in a "double spacer" for poly 1 that unduely increases the series resistance from the salicided source/drain to the transistor channel region. This compromises some of the potential performance improvement provided by salicidation.
3) Eliminating the second spacer deposition and etch avoids detrimental field isolation oxide thinning (spacer 2 overetch) that can compromise high voltage operation and performance. Also during overetch, recession of the isolation LOCOS edge may occur. This LOCOS recession can lead to salicide spiking through the diffusion junction due to the effective junction depth reduction at the junction/LOCOS sidewall. In practice, the second spacer over- etch acts to limit the minimum available diffusion junction depth. This restricts scaling of the transistor devices. 4) Eliminating the second spacer etch avoids problems associated with source/drain diffusion silicon etching during the spacer overetch. This silicon etch results from finite selectivity of the anisotropic dry etch used during spacer formation.
5) This process allows for selective "non-salicidation" , in that it is possible to selectively avoid salicidation of poly 1 without adding process steps. This is done by simply overlapping poly 2 over poly 1. All poly 1 overlapped by poly 2 will not be subject to the salicide or suicide process.
6 ) Relatively easy steps are required to facilitate salicidation (silicidation) of poly 2; that is extra nitride deposition and etch, and extra steam oxidation. This contrasts with the difficult steps associated with spacer formation. Spacer oxide formation requires more steps than this nitride-poly-nitride process and can result in poly 2-to-active region shorts under certain conditions.
Brief Description of the Drawings
Figure 1 shows a cross-sectional view of a poly 1 and poly 2, indicating the nitride-poly-nitride stack;
Figure 2 shows the wafer of Figure 1 after poly 2 pattern and etch; Figure 3 shows resist strip and the subsequent sidewall oxidation;
Figure 4 shows the resulting structure after nitride etch;
Figure 5 shows a blanket layer of titanium sputtered onto the surface of the wafer; and
Figure 6 shows the wafer after salicide.
Detailed Description of the Preferred Embodiment
After initial preparation, a wafer 13 is processed through a series of steps which result in a circuit pattern being formed on the wafer as a part of the wafer. The initial preparation is generally standard preparation used to prepare the wafer for the processing. After the initial processing, oxide , which includes gate oxide 15, is grown on the wafer 13, and the underlying portion of the wafer forms a substrate.
A first level of polysilicon, referred to as poly 1 , is applied and a layer of oxide is grown over the wafer 13. The oxide is later stripped, but source/drain reox 23 remains.
An oxide-spacer 25 is used to offset the poly 1 , which forms a transistor gate structure, from source and drain regions. The oxide-spacer helps to prevent shorting of the source/drain regions to the edge of the transistor gate during salicide formation. A thin blanket layer of nitride 27 is deposited on top of the surface of the wafer 13. The nitride 27 is preferably deposited on the surface by chemical vapor deposition (CVD) , although the nitride 27 may be grown or deposited in any of a variety of manners. This nitride layer 27 forms cell dielectric and electrically isolates the second poly layer (poly 2) from the substrate N+ region. -
The Poly 2 deposition is followed by thermal phosphorus doping using PH3 gas. This is preferrably done at a temperature of approximately 900 degrees C with a range of temperature between 700 and 1100 degrees C. The second polysilicon layer (poly 2) deposition is followed by a second level of nitride 37.
The second level of nitride and poly 2 are patterned with a photoresist material 39 and etched, first etching the nitride then etching poly 2, as shown in Figure 2.
Referring to Figure 3, the resist 39 is then removed and the surface of the wafer 13 is exposed to thermal oxidation to form a sidewall oxide* layer 41. A short oxide etch follows to clear a thin oxide which is grown on the exposed surfaces, of the nitride layers 27, 37. This is followed by a nitride etch which clears the second nitride layer 37 from the surface of poly 2 and any exposed nitride 27 from the surface of the remaining circuitry, as shown in Figure 4. The surface of the wafer 13 may now be exposed to a selective silicide formation process.
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A blanket layer of ~600A titanium is sputtered onto the surface of the wafer 13, as shown in Figure 5. A low temperature (~650C) sinter then is performed in N ambient. During the sintering step, titanium reacts with the silicon to form titanium silicide, primarily TiSi2. The titanium does not react with the oxide (Siθ2), but instead becomes TiN or remains as elemental titanium.
The location of the spacer oxide 25 and the sidewall oxide 41 coincide with locations where silicide formation is not desired, and where TiSi does not form. The TiN and unreacted titanium are washed from the wafer 13 in a salicide piranha, which is a wet etch which leaves the TiSi2 in place, as shown in Figure 6. After removing the unreacted Ti and TiN by a wet etch, a silicide anneal (~800C) is performed to lower the sheet resistivity of the TiSi2 layer.

Claims

Claims
1. Method of forming a semiconductor circuit device on a wafer made of semiconductor material comprising:
a) defining active areas on the wafer;
b) depositing a first layer of polysilicon on the active areas;
c) depositing an initial nitride layer on the wafer;
d) depositing a second polysilicon layer over the initial nitride layer;
e) depositing a second nitride layer over the second polysilicon layer;
f) exposing a sidewall of the second polysilicon layer by etching the second nitride layer and the second polysilicon layer while retaining a substantial portion of the initial nitride layer;
g) oxidizing the exposed sidewall of the second polysilicon layer;
h) stripping any exposed nitride remaining from the first and second nitride depositions;
i) sputter depositing titanium onto a substantial portion of the wafer after the deposition of the silicon; j ) sintering the titanium in a low temperature sintering step, the deposition and sintering effecting a reaction of the titanium with elemental silicon to form TiSi2 and
k) removing unreacted titanium and removing any TiN which may be left behind after said low temperature sintering, said removal being accomplished after said sintering step.
2. Method as described in claim 2, further characterized by:
forming the polysilicon in a pattern which defines a pattern of the TiSi2.
3. Method as described in claim 1 , further characterized by:
forming the polysilicon in a pattern which defines a pattern of the TiSi2.
4. Method as described in claim 3, • further characterized by:
after applying the polysilicon, etching the polysilicon to form sloped edges on the polysilicon.
5. Method as described in claim 1 , further characterized by:
after sintering the titanium, annealing the iSi2 in a silicide anneal process.
6. Method as described in claim 5, further characterized by:
said low temperature sintering process being at a temperature of less than 690 C.
7. Method as described in claim 1 , further characterized by:
said sputter deposition of titanium being sufficient for the formation of a thickness of less than 2000A of the iSi2 on the wafer.
8. Method of forming suicided N+/P+ active areas and local interconnects on to a semiconductor circuit device characterized by:
a) preparing a silicon substrate;
b) defining active areas, forming a first layer of polysilicon, and defining field isolation regions;
c) depositing an initial nitride layer over active areas, first layer of polysilicon, and field isolation, regions;
d) depositing a second polysilicon layer over the initial nitride layer;
e) depositing a second nitride layer over the second polysilicon layer;
f) exposing a sidewall of the second polysilicon layer by etching the second nitride layer and the second polysilicon layer while retaining a substantial portion of the initial nitride layer;
g) oxidizing the exposed sidewall of the second polysilicon layer;
h) stripping any exposed nitride remaining from the first and second nitride depositions;
i) sputter depositing titanium onto a substantial portion of the wafer after the deposition of the silicon;
j ) sintering the titanium in a low temperature sintering step, the deposition and sintering effecting a reaction of the titanium with elemental silicon to form iSi2; and
k) removing unreacted titanium and removing any TiN which may be left behind after said low temperature sintering, said removal being accomplished after said sintering step.
9. Method as described in claim 8, further characterized by:
applying said polysilicon by chemical vapor deposition.
10. Method as described in claim 8, further characterized by:
using a local interconnect mask to define an interconnect pattern.
11. Method of forming a nitride/poly/nitride stack to prepare said poly for sidewall oxidation. the method comprising:
a) preparing a silicon substrate;
b) defining active areas, forming a first layer of polysilicon, and defining field isolation regions;
c) depositing an initial nitride layer over active areas, first layer of polysilicon, and field isolation regions;
d) depositing a second polysilicon layer over the initial nitride layer;
e) depositing a second nitride layer over the second polysilicon layer;
f) exposing a sidewall of the second polysilicon layer by etching the second nitride layer and the second polysilicon layer while retaining a substantial portion of the initial nitride layer;
g) oxidizing the exposed sidewall of the second polysilicon "layer;
h) further etching the initial and second nitride layers; and
i) saliciding the exposed active areas and all polysilicon layers subsequent to said further etching.
PCT/US1988/002726 1988-08-12 1988-08-12 Self-aligned silicide process in forming semiconductor sidewalls WO1990001795A1 (en)

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US4080719A (en) * 1975-09-17 1978-03-28 U.S. Philips Corporation Method of manufacturing a semiconductor device and device manufactured according to the method
US4625391A (en) * 1981-06-23 1986-12-02 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US4753709A (en) * 1987-02-05 1988-06-28 Texas Instuments Incorporated Method for etching contact vias in a semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4080719A (en) * 1975-09-17 1978-03-28 U.S. Philips Corporation Method of manufacturing a semiconductor device and device manufactured according to the method
US4625391A (en) * 1981-06-23 1986-12-02 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
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