SE0004027D0 - Integration of high voltage self-aligned MOS components - Google Patents

Integration of high voltage self-aligned MOS components

Info

Publication number
SE0004027D0
SE0004027D0 SE0004027A SE0004027A SE0004027D0 SE 0004027 D0 SE0004027 D0 SE 0004027D0 SE 0004027 A SE0004027 A SE 0004027A SE 0004027 A SE0004027 A SE 0004027A SE 0004027 D0 SE0004027 D0 SE 0004027D0
Authority
SE
Sweden
Prior art keywords
high voltage
integration
mos transistor
voltage self
transistor
Prior art date
Application number
SE0004027A
Other languages
English (en)
Other versions
SE519382C2 (sv
SE0004027L (sv
Inventor
Anders Soederbaerg
Peter Olofsson
Andrej Litwin
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE0004027A priority Critical patent/SE519382C2/sv
Publication of SE0004027D0 publication Critical patent/SE0004027D0/sv
Priority to TW089124467A priority patent/TW486751B/zh
Priority to CN01818221.6A priority patent/CN1228816C/zh
Priority to PCT/SE2001/002405 priority patent/WO2002037547A1/en
Priority to EP01979204A priority patent/EP1330837A1/en
Priority to AU2002211190A priority patent/AU2002211190A1/en
Priority to US09/985,447 priority patent/US6686233B2/en
Publication of SE0004027L publication Critical patent/SE0004027L/sv
Publication of SE519382C2 publication Critical patent/SE519382C2/sv

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
SE0004027A 2000-11-03 2000-11-03 Integrering av självinriktade MOS-högspänningskomponenter samt halvledarstruktur innefattande sådana SE519382C2 (sv)

Priority Applications (7)

Application Number Priority Date Filing Date Title
SE0004027A SE519382C2 (sv) 2000-11-03 2000-11-03 Integrering av självinriktade MOS-högspänningskomponenter samt halvledarstruktur innefattande sådana
TW089124467A TW486751B (en) 2000-11-03 2000-11-18 Integration of high voltage self-aligned MOS components
CN01818221.6A CN1228816C (zh) 2000-11-03 2001-11-01 高电压自定位mos元件的集成
PCT/SE2001/002405 WO2002037547A1 (en) 2000-11-03 2001-11-01 Integration of high voltage self-aligned mos components
EP01979204A EP1330837A1 (en) 2000-11-03 2001-11-01 Integration of high voltage self-aligned mos components
AU2002211190A AU2002211190A1 (en) 2000-11-03 2001-11-01 Integration of high voltage self-aligned mos components
US09/985,447 US6686233B2 (en) 2000-11-03 2001-11-02 Integration of high voltage self-aligned MOS components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE0004027A SE519382C2 (sv) 2000-11-03 2000-11-03 Integrering av självinriktade MOS-högspänningskomponenter samt halvledarstruktur innefattande sådana

Publications (3)

Publication Number Publication Date
SE0004027D0 true SE0004027D0 (sv) 2000-11-03
SE0004027L SE0004027L (sv) 2002-05-04
SE519382C2 SE519382C2 (sv) 2003-02-25

Family

ID=20281691

Family Applications (1)

Application Number Title Priority Date Filing Date
SE0004027A SE519382C2 (sv) 2000-11-03 2000-11-03 Integrering av självinriktade MOS-högspänningskomponenter samt halvledarstruktur innefattande sådana

Country Status (7)

Country Link
US (1) US6686233B2 (sv)
EP (1) EP1330837A1 (sv)
CN (1) CN1228816C (sv)
AU (1) AU2002211190A1 (sv)
SE (1) SE519382C2 (sv)
TW (1) TW486751B (sv)
WO (1) WO2002037547A1 (sv)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4139105B2 (ja) * 2001-12-20 2008-08-27 株式会社ルネサステクノロジ 半導体装置の製造方法
US6861341B2 (en) * 2002-02-22 2005-03-01 Xerox Corporation Systems and methods for integration of heterogeneous circuit devices
US6855985B2 (en) * 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
SE527082C2 (sv) * 2003-08-27 2005-12-20 Infineon Technologies Ag Monolitiskt integrerad effektförstärkaranordning
SE0302594D0 (sv) * 2003-09-30 2003-09-30 Infineon Technologies Ag Vertical DMOS transistor device, integrated circuit, and fabrication method thereof
SE0303106D0 (sv) * 2003-11-21 2003-11-21 Infineon Technologies Ag Ldmos transistor device, integrated circuit, and fabrication method thereof
SE0303099D0 (sv) * 2003-11-21 2003-11-21 Infineon Technologies Ag Method in the fabrication of a monolithically integrated high frequency circuit
KR100670401B1 (ko) * 2003-12-27 2007-01-16 동부일렉트로닉스 주식회사 반도체 소자의 게이트 산화막 형성 방법
DE102004009521B4 (de) * 2004-02-27 2020-06-10 Austriamicrosystems Ag Hochvolt-PMOS-Transistor, Maske zur Herstellung einer Wanne und Verfahren zur Herstellung eines Hochvolt-PMOS-Transistors
KR100624912B1 (ko) * 2005-03-22 2006-09-19 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
US7329618B2 (en) * 2005-06-28 2008-02-12 Micron Technology, Inc. Ion implanting methods
EP1804285B1 (en) * 2005-12-27 2018-10-24 Semiconductor Components Industries, LLC Method for manufacturing a transistor with self-aligned channel
KR100741882B1 (ko) * 2005-12-29 2007-07-23 동부일렉트로닉스 주식회사 고전압 소자 및 그 제조방법
US7465623B2 (en) * 2006-08-28 2008-12-16 Advanced Micro Devices, Inc. Methods for fabricating a semiconductor device on an SOI substrate
KR100865548B1 (ko) * 2006-12-28 2008-10-28 주식회사 하이닉스반도체 반도체 메모리장치의 제조방법
US7781843B1 (en) * 2007-01-11 2010-08-24 Hewlett-Packard Development Company, L.P. Integrating high-voltage CMOS devices with low-voltage CMOS
KR100836766B1 (ko) * 2007-01-22 2008-06-10 삼성전자주식회사 고전압 반도체 소자의 제조방법 및 이를 이용한 고전압반도체 소자
KR100917813B1 (ko) 2007-10-05 2009-09-18 주식회사 동부하이텍 반도체 소자 및 이의 제조 방법
KR100903483B1 (ko) 2007-11-26 2009-06-18 주식회사 동부하이텍 반도체 소자의 제조방법
JP5283916B2 (ja) * 2008-02-01 2013-09-04 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置の製造方法
US20100117153A1 (en) * 2008-11-07 2010-05-13 Honeywell International Inc. High voltage soi cmos device and method of manufacture
CN101752254B (zh) * 2008-12-22 2012-12-19 中芯国际集成电路制造(上海)有限公司 形成离子注入区的方法、mos晶体管及其制造方法
SG164319A1 (en) * 2009-07-10 2010-09-29 Chartered Semiconductor Mfg High voltage device
CN101789432B (zh) * 2010-01-27 2011-11-16 崇贸科技股份有限公司 高压侧半导体结构
US9209098B2 (en) 2011-05-19 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. HVMOS reliability evaluation using bulk resistances as indices
CN102683186A (zh) * 2012-05-09 2012-09-19 上海宏力半导体制造有限公司 抑制热载流子注入的方法及BiCMOS器件制造方法
US20140167142A1 (en) 2012-12-14 2014-06-19 Spansion Llc Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells
DE102015004235B4 (de) 2014-04-14 2019-01-03 Elmos Semiconductor Ag Verfahren zum Schutz eines CMOS Schaltkreises auf einem N-Substrat vor Verpolung
DE102014017146A1 (de) 2014-04-14 2015-10-15 Elmos Semiconductor Aktiengesellschaft Rail-to-Rail-Verpolschutz für den kombinierten Ein-/Ausgang eine integrierten CMOS Schaltkreises auf einem P-Substrat
US9412736B2 (en) 2014-06-05 2016-08-09 Globalfoundries Inc. Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias
US10038063B2 (en) 2014-06-10 2018-07-31 International Business Machines Corporation Tunable breakdown voltage RF FET devices
CN105789267B (zh) * 2014-12-22 2019-04-26 旺宏电子股份有限公司 半导体元件
CN105810583B (zh) * 2014-12-30 2019-03-15 无锡华润上华科技有限公司 横向绝缘栅双极型晶体管的制造方法
US9780250B2 (en) * 2016-01-14 2017-10-03 Varian Semiconductor Equipment Associates, Inc. Self-aligned mask for ion implantation
KR101822016B1 (ko) * 2016-09-13 2018-01-26 매그나칩반도체 유한회사 Dmos 트랜지스터 및 cmos 트랜지스터 제조 방법
CN107785324A (zh) * 2017-09-19 2018-03-09 上海华虹宏力半导体制造有限公司 高压工艺集成电路方法
CN109786328A (zh) * 2017-11-10 2019-05-21 中芯国际集成电路制造(上海)有限公司 半导体器件及其制造方法
CN109950151B (zh) * 2017-12-20 2022-02-15 中芯国际集成电路制造(上海)有限公司 Pmos晶体管及其形成方法
US11228174B1 (en) 2019-05-30 2022-01-18 Silicet, LLC Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
US10892362B1 (en) 2019-11-06 2021-01-12 Silicet, LLC Devices for LDMOS and other MOS transistors with hybrid contact
CN116508135B (zh) 2020-12-04 2024-06-04 安普莱西娅有限责任公司 具有自对准体和混合源的ldmos
TWI768654B (zh) * 2021-01-14 2022-06-21 世界先進積體電路股份有限公司 半導體結構及其形成方法
US11742389B2 (en) 2021-05-18 2023-08-29 Vanguard International Semiconductor Corporation Semiconductor structure and method for forming the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5061975A (en) * 1988-02-19 1991-10-29 Mitsubishi Denki Kabushiki Kaisha MOS type field effect transistor having LDD structure
US5047358A (en) * 1989-03-17 1991-09-10 Delco Electronics Corporation Process for forming high and low voltage CMOS transistors on a single integrated circuit chip
US5532176A (en) * 1992-04-17 1996-07-02 Nippondenso Co., Ltd. Process for fabricating a complementary MIS transistor
SE506433C2 (sv) 1994-03-24 1997-12-15 Anders Soederbaerg Metod för tillverkning av integrerade komponenter
US5498554A (en) * 1994-04-08 1996-03-12 Texas Instruments Incorporated Method of making extended drain resurf lateral DMOS devices
FR2735904B1 (fr) * 1995-06-21 1997-07-18 Commissariat Energie Atomique Procede de realisation d'un semi-conducteur avec une zone fortement dopee situee entre des zones faiblement dopees, pour la fabrication de transistors
US5817551A (en) * 1995-08-25 1998-10-06 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
JPH10189762A (ja) * 1996-12-20 1998-07-21 Nec Corp 半導体装置およびその製造方法
US5891782A (en) * 1997-08-21 1999-04-06 Sharp Microelectronics Technology, Inc. Method for fabricating an asymmetric channel doped MOS structure
JP2000077532A (ja) * 1998-09-03 2000-03-14 Mitsubishi Electric Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
EP1330837A1 (en) 2003-07-30
US6686233B2 (en) 2004-02-03
CN1228816C (zh) 2005-11-23
WO2002037547A1 (en) 2002-05-10
US20020055220A1 (en) 2002-05-09
CN1471724A (zh) 2004-01-28
TW486751B (en) 2002-05-11
SE519382C2 (sv) 2003-02-25
AU2002211190A1 (en) 2002-05-15
SE0004027L (sv) 2002-05-04

Similar Documents

Publication Publication Date Title
SE0004027D0 (sv) Integration of high voltage self-aligned MOS components
JP2697392B2 (ja) 相補型半導体装置の製造方法
SE0104164L (sv) Högspännings-mos-transistor
US6358787B2 (en) Method of forming CMOS integrated circuitry
TW355822B (en) Manufacturing method of a semiconductor device
TW200644092A (en) Self-aligned high-energy implantation for deep junction structure
US20080283922A1 (en) Semiconductor device and manufacturing method thereof
US6979609B2 (en) Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks
US5547894A (en) CMOS processing with low and high-current FETs
DE60139068D1 (de) Herstellungsverfahren für halbleiterbauelement
JPH08204025A (ja) Cmos半導体装置の製造方法
JP2790050B2 (ja) 半導体装置の製造方法
US8053305B2 (en) Method for producing semiconductor device
KR20000053400A (ko) 실리콘 엠오에스에프이티 트랜지스터 및 그 제조 방법
US6043533A (en) Method of integrating Ldd implantation for CMOS device fabrication
US20020052083A1 (en) Cost effective split-gate process that can independently optimize the low voltage(LV) and high voltage (HV) transistors to minimize reverse short channel effects
KR20040021722A (ko) 반도체소자 및 이를 제조하는 방법
US6617218B2 (en) Manufacturing method for semiconductor device
EP1225627A2 (en) Semiconductor integrated circuit device and manufacture method therefor
JP2000269357A (ja) 半導体装置の製造方法
KR950012035B1 (ko) 상보 모스 트랜지스터 제조방법
KR970053097A (ko) 모스전계효과트랜지스터 제조방법
KR960043050A (ko) 반도체 소자의 트랜지스터 제조방법
TW200514202A (en) Method for forming CMOS transistor
US6573165B2 (en) Method of providing polysilicon spacer for implantation

Legal Events

Date Code Title Description
NUG Patent has lapsed