MX171852B - Combinacion de marco conductor para la construccion de un paquete de circuito integrado y metodo para producir un dispositivo semiconductor de empaque de cavidad - Google Patents
Combinacion de marco conductor para la construccion de un paquete de circuito integrado y metodo para producir un dispositivo semiconductor de empaque de cavidadInfo
- Publication number
- MX171852B MX171852B MX020869A MX2086990A MX171852B MX 171852 B MX171852 B MX 171852B MX 020869 A MX020869 A MX 020869A MX 2086990 A MX2086990 A MX 2086990A MX 171852 B MX171852 B MX 171852B
- Authority
- MX
- Mexico
- Prior art keywords
- chip
- filler
- integrated circuit
- conductive frame
- conductive
- Prior art date
Links
- 238000010276 construction Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 title 1
- 238000004806 packaging method and process Methods 0.000 title 1
- 239000000945 filler Substances 0.000 abstract 6
- 239000002184 metal Substances 0.000 abstract 2
- 239000004020 conductor Substances 0.000 abstract 1
- 238000012856 packing Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/607—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of mechanical vibrations, e.g. ultrasonic vibrations
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/041—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
La presente invención se refiere a una combinación de marco conductor, para la construcción de un paquete de circuito integrado, en el que un relleno para unión de chips y al menos un chip de circuito integrado de semiconductor en el relleno de unión de chip, son centrados aproximadamente dentro de un paquete, para reducir las tensiones ejercidas en cuando menos un chip y el relleno de unión de chips, la combinación está caracterizada porque comprende: (a) un marco conductor de metal, que tiene una pluralidad de conductores de tipo dedo y un relleno de barra; (b) una cinta polimérica unida al marco conductor de metal; (c) un de anillo empaque moldeado en el marco conductor, de tal manera que el anillo de empaque rodee y agarre una porción de cada dedo conductor y forme un círculo en el relleno de unión de chip, cuyo costado interno se define por una cinta polimérica, que define una cavidad principal dentro del anillo, mdentro del cual el relleno de unión de chip está aproximadamente centrado, sin el relleno de barra tocar directamente el anillo de empaque.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US35923989A | 1989-05-31 | 1989-05-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
MX171852B true MX171852B (es) | 1993-11-19 |
Family
ID=23412950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
MX020869A MX171852B (es) | 1989-05-31 | 1990-05-24 | Combinacion de marco conductor para la construccion de un paquete de circuito integrado y metodo para producir un dispositivo semiconductor de empaque de cavidad |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0401017B1 (es) |
JP (1) | JP2982971B2 (es) |
KR (1) | KR0183009B1 (es) |
DE (1) | DE69031248T2 (es) |
MX (1) | MX171852B (es) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4325712C2 (de) * | 1993-07-30 | 1996-03-21 | Siemens Ag | Verfahren zum Verkapseln von elektrischen oder elektronischen Bauelementen oder Baugruppen und Verkapselung von elektrischen oder elektronischen Bauelementen oder Baugruppen |
KR970010676B1 (ko) * | 1994-03-29 | 1997-06-30 | 엘지반도체 주식회사 | 반도체 패키지 및 이에 사용되는 리드 프레임 |
DE19528731C2 (de) * | 1995-08-04 | 2000-06-08 | Hirschmann Richard Gmbh Co | Verfahren zum Schützen von Bauteilen |
CN2457740Y (zh) * | 2001-01-09 | 2001-10-31 | 台湾沛晶股份有限公司 | 集成电路晶片的构装 |
DE10221857A1 (de) * | 2002-05-16 | 2003-11-27 | Osram Opto Semiconductors Gmbh | Verfahren zum Befestigen eines Halbleiterchips in einem Kunststoffgehäusekörper, optoelektronisches Halbleiterbauelement und Verfahren zu dessen Herstellung |
CN104795377B (zh) | 2014-01-17 | 2019-02-19 | 恩智浦美国有限公司 | 具有引线网的半导体器件 |
CN112215046A (zh) * | 2019-07-12 | 2021-01-12 | 格科微电子(上海)有限公司 | 光学指纹识别模组及其形成方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4303934A (en) * | 1979-08-30 | 1981-12-01 | Burr-Brown Research Corp. | Molded lead frame dual in line package including a hybrid circuit |
-
1990
- 1990-05-24 MX MX020869A patent/MX171852B/es unknown
- 1990-05-30 KR KR1019900007841A patent/KR0183009B1/ko not_active IP Right Cessation
- 1990-05-31 DE DE69031248T patent/DE69031248T2/de not_active Expired - Fee Related
- 1990-05-31 EP EP90305939A patent/EP0401017B1/en not_active Expired - Lifetime
- 1990-05-31 JP JP2143280A patent/JP2982971B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0401017A2 (en) | 1990-12-05 |
KR900019183A (ko) | 1990-12-24 |
KR0183009B1 (ko) | 1999-04-15 |
EP0401017B1 (en) | 1997-08-13 |
JPH03201463A (ja) | 1991-09-03 |
JP2982971B2 (ja) | 1999-11-29 |
EP0401017A3 (en) | 1991-07-17 |
DE69031248T2 (de) | 1997-12-18 |
DE69031248D1 (de) | 1997-09-18 |
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