JPS554917A - Resin-enclosed semi-conductor device - Google Patents
Resin-enclosed semi-conductor deviceInfo
- Publication number
- JPS554917A JPS554917A JP7647278A JP7647278A JPS554917A JP S554917 A JPS554917 A JP S554917A JP 7647278 A JP7647278 A JP 7647278A JP 7647278 A JP7647278 A JP 7647278A JP S554917 A JPS554917 A JP S554917A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- resin
- manner
- insulating
- stress
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
- H01L2224/48996—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/48998—Alignment aids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
PURPOSE: To prevent stress from gathering onto chip by providing a tab with an insulating stress relief barrier in such a manner as to surround outside of the semi- conductor chip.
CONSTITUTION: An insulating frame 18 or a frame 22 of an insulating plate 22 is provided on the top of a tab 10 in other to relieve stress gathering onto surrounding area of an IC chip when a resin-enclosed body 20 is solidifying and shrinking. It is recormmendable to arrange a relief barrier in such a manner as to surround the IC chip keeping a fixed distance of d so that it becomes d<0.5mm. It is possible, in this manner, to prevent the chip from crack and the resin and the wire from exfoliation.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7647278A JPS554917A (en) | 1978-06-26 | 1978-06-26 | Resin-enclosed semi-conductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7647278A JPS554917A (en) | 1978-06-26 | 1978-06-26 | Resin-enclosed semi-conductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS554917A true JPS554917A (en) | 1980-01-14 |
JPS6118862B2 JPS6118862B2 (en) | 1986-05-14 |
Family
ID=13606109
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7647278A Granted JPS554917A (en) | 1978-06-26 | 1978-06-26 | Resin-enclosed semi-conductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS554917A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5744558U (en) * | 1980-08-27 | 1982-03-11 | ||
JPS57125541U (en) * | 1981-01-30 | 1982-08-05 | ||
JPS58441U (en) * | 1981-06-25 | 1983-01-05 | 富士通株式会社 | plastic packaging |
US7789316B2 (en) | 2007-03-23 | 2010-09-07 | Fujitsu Limited | Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device |
US7960215B2 (en) | 2007-03-23 | 2011-06-14 | Fujitsu Limited | Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device |
US7982295B2 (en) | 2007-03-23 | 2011-07-19 | Fujitsu Limited | Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device |
-
1978
- 1978-06-26 JP JP7647278A patent/JPS554917A/en active Granted
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5744558U (en) * | 1980-08-27 | 1982-03-11 | ||
JPS57125541U (en) * | 1981-01-30 | 1982-08-05 | ||
JPS58441U (en) * | 1981-06-25 | 1983-01-05 | 富士通株式会社 | plastic packaging |
US7789316B2 (en) | 2007-03-23 | 2010-09-07 | Fujitsu Limited | Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device |
US7960215B2 (en) | 2007-03-23 | 2011-06-14 | Fujitsu Limited | Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device |
US7982295B2 (en) | 2007-03-23 | 2011-07-19 | Fujitsu Limited | Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device |
Also Published As
Publication number | Publication date |
---|---|
JPS6118862B2 (en) | 1986-05-14 |
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