JPS554917A - Resin-enclosed semi-conductor device - Google Patents

Resin-enclosed semi-conductor device

Info

Publication number
JPS554917A
JPS554917A JP7647278A JP7647278A JPS554917A JP S554917 A JPS554917 A JP S554917A JP 7647278 A JP7647278 A JP 7647278A JP 7647278 A JP7647278 A JP 7647278A JP S554917 A JPS554917 A JP S554917A
Authority
JP
Japan
Prior art keywords
chip
resin
manner
insulating
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7647278A
Other languages
Japanese (ja)
Other versions
JPS6118862B2 (en
Inventor
Yoshiaki Wakashima
Hideo Inayoshi
Kunihiko Nishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7647278A priority Critical patent/JPS554917A/en
Publication of JPS554917A publication Critical patent/JPS554917A/en
Publication of JPS6118862B2 publication Critical patent/JPS6118862B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48996Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/48998Alignment aids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: To prevent stress from gathering onto chip by providing a tab with an insulating stress relief barrier in such a manner as to surround outside of the semi- conductor chip.
CONSTITUTION: An insulating frame 18 or a frame 22 of an insulating plate 22 is provided on the top of a tab 10 in other to relieve stress gathering onto surrounding area of an IC chip when a resin-enclosed body 20 is solidifying and shrinking. It is recormmendable to arrange a relief barrier in such a manner as to surround the IC chip keeping a fixed distance of d so that it becomes d<0.5mm. It is possible, in this manner, to prevent the chip from crack and the resin and the wire from exfoliation.
COPYRIGHT: (C)1980,JPO&Japio
JP7647278A 1978-06-26 1978-06-26 Resin-enclosed semi-conductor device Granted JPS554917A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7647278A JPS554917A (en) 1978-06-26 1978-06-26 Resin-enclosed semi-conductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7647278A JPS554917A (en) 1978-06-26 1978-06-26 Resin-enclosed semi-conductor device

Publications (2)

Publication Number Publication Date
JPS554917A true JPS554917A (en) 1980-01-14
JPS6118862B2 JPS6118862B2 (en) 1986-05-14

Family

ID=13606109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7647278A Granted JPS554917A (en) 1978-06-26 1978-06-26 Resin-enclosed semi-conductor device

Country Status (1)

Country Link
JP (1) JPS554917A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5744558U (en) * 1980-08-27 1982-03-11
JPS57125541U (en) * 1981-01-30 1982-08-05
JPS58441U (en) * 1981-06-25 1983-01-05 富士通株式会社 plastic packaging
US7789316B2 (en) 2007-03-23 2010-09-07 Fujitsu Limited Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device
US7960215B2 (en) 2007-03-23 2011-06-14 Fujitsu Limited Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device
US7982295B2 (en) 2007-03-23 2011-07-19 Fujitsu Limited Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5744558U (en) * 1980-08-27 1982-03-11
JPS57125541U (en) * 1981-01-30 1982-08-05
JPS58441U (en) * 1981-06-25 1983-01-05 富士通株式会社 plastic packaging
US7789316B2 (en) 2007-03-23 2010-09-07 Fujitsu Limited Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device
US7960215B2 (en) 2007-03-23 2011-06-14 Fujitsu Limited Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device
US7982295B2 (en) 2007-03-23 2011-07-19 Fujitsu Limited Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device

Also Published As

Publication number Publication date
JPS6118862B2 (en) 1986-05-14

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