JPS5272572A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5272572A
JPS5272572A JP50149353A JP14935375A JPS5272572A JP S5272572 A JPS5272572 A JP S5272572A JP 50149353 A JP50149353 A JP 50149353A JP 14935375 A JP14935375 A JP 14935375A JP S5272572 A JPS5272572 A JP S5272572A
Authority
JP
Japan
Prior art keywords
semiconductor device
bump
chip
shortcircuiting
decreased
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50149353A
Other languages
Japanese (ja)
Inventor
Koichi Oguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP50149353A priority Critical patent/JPS5272572A/en
Publication of JPS5272572A publication Critical patent/JPS5272572A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/79—Apparatus for Tape Automated Bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To obtain the structure of such an IC chip wherein shortcircuiting between the Si exposed part of the IC chip and the lead wires on a flexible tape does not occur even if the height of bump is decreased or the bump is eliminated.
COPYRIGHT: (C)1977,JPO&Japio
JP50149353A 1975-12-15 1975-12-15 Semiconductor device Pending JPS5272572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50149353A JPS5272572A (en) 1975-12-15 1975-12-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50149353A JPS5272572A (en) 1975-12-15 1975-12-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5272572A true JPS5272572A (en) 1977-06-17

Family

ID=15473260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50149353A Pending JPS5272572A (en) 1975-12-15 1975-12-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5272572A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5429561A (en) * 1977-08-09 1979-03-05 Oki Electric Ind Co Ltd Semiconductor device
JPS5444867A (en) * 1977-09-16 1979-04-09 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS55113339A (en) * 1979-02-22 1980-09-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor integrated circuit device
JPH0328769A (en) * 1989-06-27 1991-02-06 Mitsubishi Electric Corp Acceleration sensor
WO2001015224A1 (en) * 1999-08-25 2001-03-01 Gemplus Method for protecting integrated circuit chips by depositing a thin insulation layer
FR2797995A1 (en) * 1999-08-25 2001-03-02 Gemplus Card Int Protection of integrated circuit chips on silicon wafer involves depositing a thin insulation layer
WO2001086719A1 (en) * 2000-05-10 2001-11-15 Gemplus Thin layer chip insulation for conductive polymer connection

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5429561A (en) * 1977-08-09 1979-03-05 Oki Electric Ind Co Ltd Semiconductor device
JPS5444867A (en) * 1977-09-16 1979-04-09 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS55113339A (en) * 1979-02-22 1980-09-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor integrated circuit device
JPH0328769A (en) * 1989-06-27 1991-02-06 Mitsubishi Electric Corp Acceleration sensor
JPH0830714B2 (en) * 1989-06-27 1996-03-27 三菱電機株式会社 Acceleration sensor
WO2001015224A1 (en) * 1999-08-25 2001-03-01 Gemplus Method for protecting integrated circuit chips by depositing a thin insulation layer
FR2797995A1 (en) * 1999-08-25 2001-03-02 Gemplus Card Int Protection of integrated circuit chips on silicon wafer involves depositing a thin insulation layer
FR2797996A1 (en) * 1999-08-25 2001-03-02 Gemplus Card Int METHOD OF PROTECTING INTEGRATED CIRCUIT CHIPS BY INSULATING THIN FILM DEPOSITION
WO2001086719A1 (en) * 2000-05-10 2001-11-15 Gemplus Thin layer chip insulation for conductive polymer connection
FR2808920A1 (en) * 2000-05-10 2001-11-16 Gemplus Card Int Method for protecting chips arranged on a wafer comprises cutting wafer to loosen chips, depositing electrically insulating layer on active surface and flanks of at least one chip, and clearing at least one opening in the insulating layer

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