JPS55113339A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS55113339A
JPS55113339A JP2039979A JP2039979A JPS55113339A JP S55113339 A JPS55113339 A JP S55113339A JP 2039979 A JP2039979 A JP 2039979A JP 2039979 A JP2039979 A JP 2039979A JP S55113339 A JPS55113339 A JP S55113339A
Authority
JP
Japan
Prior art keywords
chip
edge
circuit device
frame
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2039979A
Other languages
Japanese (ja)
Inventor
Mitsuru Nitta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP2039979A priority Critical patent/JPS55113339A/en
Publication of JPS55113339A publication Critical patent/JPS55113339A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To prevent the occurrence of short-circuiting accurately between a lead frame and the edge of an IC chip by providing resin coating between them in a tape carrier type IC device.
CONSTITUTION: Lead frame 2 is fixed on film-type tape 1, and the end of finger 21 provided on this is connected to bump 31 of IC chip 3. In this way, chip 3 is fixed to frame 2. But, at this time, liquid rsin, such as epoxy resin, silicone rubber, phenol resin, polyurethane resin is dripped on chip 3 surrounding edge 32 of chip 3 and finger 21., and it is solidified. By this, when the circuit device is fabricated, even if the frame is deformed, it does not come into contact with edge 32 of chip 3, and no edge touch occurs.
COPYRIGHT: (C)1980,JPO&Japio
JP2039979A 1979-02-22 1979-02-22 Semiconductor integrated circuit device Pending JPS55113339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2039979A JPS55113339A (en) 1979-02-22 1979-02-22 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2039979A JPS55113339A (en) 1979-02-22 1979-02-22 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS55113339A true JPS55113339A (en) 1980-09-01

Family

ID=12025934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2039979A Pending JPS55113339A (en) 1979-02-22 1979-02-22 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS55113339A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01104031U (en) * 1987-12-25 1989-07-13
US4984059A (en) * 1982-10-08 1991-01-08 Fujitsu Limited Semiconductor device and a method for fabricating the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5272572A (en) * 1975-12-15 1977-06-17 Seiko Epson Corp Semiconductor device
JPS5341176A (en) * 1976-09-28 1978-04-14 Seiko Epson Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5272572A (en) * 1975-12-15 1977-06-17 Seiko Epson Corp Semiconductor device
JPS5341176A (en) * 1976-09-28 1978-04-14 Seiko Epson Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4984059A (en) * 1982-10-08 1991-01-08 Fujitsu Limited Semiconductor device and a method for fabricating the same
USRE35109E (en) * 1982-10-08 1995-12-05 Fujitsu Limited Semiconductor device and method for fabricating the same
JPH01104031U (en) * 1987-12-25 1989-07-13

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