JPS5429561A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5429561A
JPS5429561A JP9462677A JP9462677A JPS5429561A JP S5429561 A JPS5429561 A JP S5429561A JP 9462677 A JP9462677 A JP 9462677A JP 9462677 A JP9462677 A JP 9462677A JP S5429561 A JPS5429561 A JP S5429561A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrodes
forming
substrate
tilt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9462677A
Other languages
Japanese (ja)
Inventor
Toshiyuki Iwabuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP9462677A priority Critical patent/JPS5429561A/en
Publication of JPS5429561A publication Critical patent/JPS5429561A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Abstract

PURPOSE: To avoid the contact between the beam terminals mounted on the electrodes and the substrate, by forming steps or tilt at the end of the semiconductor substrate forming the electrodes on its surface and by lowering the ends from the electrode forming surface in level.
COPYRIGHT: (C)1979,JPO&Japio
JP9462677A 1977-08-09 1977-08-09 Semiconductor device Pending JPS5429561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9462677A JPS5429561A (en) 1977-08-09 1977-08-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9462677A JPS5429561A (en) 1977-08-09 1977-08-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5429561A true JPS5429561A (en) 1979-03-05

Family

ID=14115461

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9462677A Pending JPS5429561A (en) 1977-08-09 1977-08-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5429561A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63150509U (en) * 1987-03-24 1988-10-04
JPS63175907U (en) * 1987-05-07 1988-11-15

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5272572A (en) * 1975-12-15 1977-06-17 Seiko Epson Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5272572A (en) * 1975-12-15 1977-06-17 Seiko Epson Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63150509U (en) * 1987-03-24 1988-10-04
JPS63175907U (en) * 1987-05-07 1988-11-15

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