MX167351B - Sistema y metodo de memoria de autoverificacion - Google Patents

Sistema y metodo de memoria de autoverificacion

Info

Publication number
MX167351B
MX167351B MX011487A MX1148788A MX167351B MX 167351 B MX167351 B MX 167351B MX 011487 A MX011487 A MX 011487A MX 1148788 A MX1148788 A MX 1148788A MX 167351 B MX167351 B MX 167351B
Authority
MX
Mexico
Prior art keywords
memory banks
content
elements
locations
memory
Prior art date
Application number
MX011487A
Other languages
English (en)
Inventor
Jesse B Lipcon
Bary A Maskas
David K Morgan
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of MX167351B publication Critical patent/MX167351B/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

La presente invención se refiere a una memoria que se prueba así misma compuesta de una pluralidad de bancos de memoria, está caracterizada porque comprende; elementos para describir simultáneamente los mismos patrones de prueba de ubicaciones correspondientes en cada una de la pluralidad de bancos de memoria, elementos para accesar el contenido de ubicaciones correspondientes en cada uno de los bancos de memoria, elementos para seleccionar uno de los bancos de memoria; elementos para comparar simultáneamente el contenido en las ubicaciones del banco de memoria seleccionaco con el contendio en ubicaciones correspondientes de los otros bancos de memoria; elementos para registrar casos de errores los eventos cuando el contenido en las ubicaciones de los bandos de memoria seleccionados son diferentes a los contenidos en las ubicaciones correspondientes de cualquiera de los otros bancos de memoria.
MX011487A 1987-05-14 1988-05-13 Sistema y metodo de memoria de autoverificacion MX167351B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/049,812 US4782486A (en) 1987-05-14 1987-05-14 Self-testing memory

Publications (1)

Publication Number Publication Date
MX167351B true MX167351B (es) 1993-03-18

Family

ID=21961873

Family Applications (1)

Application Number Title Priority Date Filing Date
MX011487A MX167351B (es) 1987-05-14 1988-05-13 Sistema y metodo de memoria de autoverificacion

Country Status (10)

Country Link
US (1) US4782486A (es)
EP (2) EP0362197A1 (es)
JP (1) JPS6464051A (es)
KR (1) KR930004330B1 (es)
CN (1) CN1016910B (es)
AU (2) AU607932B2 (es)
CA (1) CA1286781C (es)
DE (1) DE3884454D1 (es)
MX (1) MX167351B (es)
WO (1) WO1988009038A1 (es)

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US6000048A (en) * 1996-08-14 1999-12-07 Cirrus Logic, Inc. Combined logic and memory circuit with built-in memory test
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US5959911A (en) * 1997-09-29 1999-09-28 Siemens Aktiengesellschaft Apparatus and method for implementing a bank interlock scheme and related test mode for multibank memory devices
US6001662A (en) * 1997-12-02 1999-12-14 International Business Machines Corporation Method and system for providing a reusable configurable self-test controller for manufactured integrated circuits
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US7159161B2 (en) * 1999-01-29 2007-01-02 National Science Council Test method and architecture for circuits having inputs
US6889334B1 (en) * 2001-10-02 2005-05-03 Advanced Micro Devices, Inc. Multimode system for calibrating a data strobe delay for a memory read operation
US7184916B2 (en) * 2003-05-20 2007-02-27 Cray Inc. Apparatus and method for testing memory cards
US7320100B2 (en) 2003-05-20 2008-01-15 Cray Inc. Apparatus and method for memory with bit swapping on the fly and testing
US7539909B2 (en) * 2003-09-30 2009-05-26 Intel Corporation Distributed memory initialization and test methods and apparatus
US8060799B2 (en) * 2004-06-11 2011-11-15 Samsung Electronics Co., Ltd. Hub, memory module, memory system and methods for reading and writing to the same
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US7865740B2 (en) * 2005-09-27 2011-01-04 Intel Corporation Logging changes to blocks in a non-volatile memory
US7802157B2 (en) * 2006-06-22 2010-09-21 Micron Technology, Inc. Test mode for multi-chip integrated circuit packages
CN103744752B (zh) * 2013-12-20 2015-09-30 北京交控科技有限公司 一种内存的在线故障检测方法和装置
CN107315649A (zh) * 2016-04-26 2017-11-03 新华三技术有限公司 一种表项校验方法和装置
GB2567189B (en) * 2017-10-05 2020-10-21 Advanced Risc Mach Ltd Handling errors in buffers
KR20240092313A (ko) * 2022-12-14 2024-06-24 리벨리온 주식회사 뉴럴 프로세서 및 이에 포함된 뉴럴 코어에 대한 컨피그 아이디 할당 방법

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Also Published As

Publication number Publication date
EP0292206A1 (en) 1988-11-23
KR930004330B1 (ko) 1993-05-26
EP0362197A1 (en) 1990-04-11
CN1016910B (zh) 1992-06-03
AU7750887A (en) 1988-12-06
US4782486A (en) 1988-11-01
DE3884454D1 (de) 1993-11-04
CA1286781C (en) 1991-07-23
AU607932B2 (en) 1991-03-21
JPS6464051A (en) 1989-03-09
AU1557288A (en) 1988-11-17
EP0292206B1 (en) 1993-09-29
CN1031148A (zh) 1989-02-15
KR880014464A (ko) 1988-12-23
WO1988009038A1 (en) 1988-11-17

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