JPS5654698A - Test method of memory device - Google Patents

Test method of memory device

Info

Publication number
JPS5654698A
JPS5654698A JP13012479A JP13012479A JPS5654698A JP S5654698 A JPS5654698 A JP S5654698A JP 13012479 A JP13012479 A JP 13012479A JP 13012479 A JP13012479 A JP 13012479A JP S5654698 A JPS5654698 A JP S5654698A
Authority
JP
Japan
Prior art keywords
memory device
partial memory
data
test
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13012479A
Other languages
Japanese (ja)
Inventor
Tatsuo Seki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13012479A priority Critical patent/JPS5654698A/en
Publication of JPS5654698A publication Critical patent/JPS5654698A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the test time, by writing the test data simultaneously into several partial memory devices and then carrying out a simultaneous checking to several reading data.
CONSTITUTION: The memory device is divided into the partial memory devices 1W 4 having the same capacity each in the address direction. At the same time, the following means are provided: the address allotting means 5W6 which secures the same address constitution for each partial memory device during the test; the means 10W13 which are provided in each partial memory device for a comparison between the writing data and the reading data; and the means 22 which detects the error data position based on the comparison output. Then the test data are read out of the partial memory devices at one time after writing the test data to each partial memory device. And a simultaneous checking is carried out to several reading data.
COPYRIGHT: (C)1981,JPO&Japio
JP13012479A 1979-10-09 1979-10-09 Test method of memory device Pending JPS5654698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13012479A JPS5654698A (en) 1979-10-09 1979-10-09 Test method of memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13012479A JPS5654698A (en) 1979-10-09 1979-10-09 Test method of memory device

Publications (1)

Publication Number Publication Date
JPS5654698A true JPS5654698A (en) 1981-05-14

Family

ID=15026514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13012479A Pending JPS5654698A (en) 1979-10-09 1979-10-09 Test method of memory device

Country Status (1)

Country Link
JP (1) JPS5654698A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57201015U (en) * 1981-06-17 1982-12-21
JPS621200A (en) * 1985-02-28 1987-01-07 Nec Corp Semiconductor memory
JPS6464051A (en) * 1987-05-14 1989-03-09 Digital Equipment Corp Automatically sizing memory system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57201015U (en) * 1981-06-17 1982-12-21
JPS621200A (en) * 1985-02-28 1987-01-07 Nec Corp Semiconductor memory
JPS6464051A (en) * 1987-05-14 1989-03-09 Digital Equipment Corp Automatically sizing memory system

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