KR970077222A - 반도체소자의 제조방법 - Google Patents

반도체소자의 제조방법 Download PDF

Info

Publication number
KR970077222A
KR970077222A KR1019960018366A KR19960018366A KR970077222A KR 970077222 A KR970077222 A KR 970077222A KR 1019960018366 A KR1019960018366 A KR 1019960018366A KR 19960018366 A KR19960018366 A KR 19960018366A KR 970077222 A KR970077222 A KR 970077222A
Authority
KR
South Korea
Prior art keywords
polysilicon
gate oxide
oxide film
polysilicon layer
nitriding
Prior art date
Application number
KR1019960018366A
Other languages
English (en)
Other versions
KR100399957B1 (ko
Inventor
최병대
김의식
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960018366A priority Critical patent/KR100399957B1/ko
Publication of KR970077222A publication Critical patent/KR970077222A/ko
Application granted granted Critical
Publication of KR100399957B1 publication Critical patent/KR100399957B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

본 발명은 폴리실리콘을 이온주입을 이용하여 게이트전극화하는 방법에 관한 것으로, 반도체기판상에 게이트산화막을 형성하는 단계와, 상기 게이트산화막의 상부 소정부분을 질화시키고 시간지연없이 연속적으로 폴리실리콘을 증착하는 단계, 상기 폴리실리콘층에 소정의 도판트를 이온주입하는 단계, 상기 폴리실리콘층을 안정화시키면서 주입된 도판트들을 활성화시키는 단계를 포함하는 반도체소자 제조방법을 제공함으로써 게이트전극으로 사용되는 폴리실리콘을 전극화하기 위해 진행해야 하는 고온, 장시간의 폴리실리콘 도핑 공정을 이용하지 않고 이온주입을 이용함으로써 공정시간을 단축하고 공정온도를 감소시킨다.

Description

반도체소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 반도체소자의 게이트 제조방법을 도시한 공정순서도이다.

Claims (5)

  1. 반도체기판상에 게이트산화막을 형성하는 단계와, 상기 게이트산화막의 상부 소정부분을 질화시키고 시간지연없이 연속적응로 폴리실리콘을 증착하는 단계, 상기 폴리실리콘층에 소정의 도판트를 이온주입하는 단계, 상기 폴리실리콘층을 안정화시키면서 주입된 도판트들을 활성화시키는 단계를 포함하는 것을 특징으로 하는 반도체소자 제조방법.
  2. 제1항에 있어서, 상기 게이트산호막은 습식산화 방식에 의해 형성하는 것을 특징으로 하는 반도체소자 제조방법.
  3. 제1항에 있어서, 상기 게이트산화막의 질화는 N2O 분위기에서의 어닐링에 의해 행하는 것을 특징으로 하는 반도체소자 제조방법.
  4. 제1항에 있어서, 상기 질화에 의해 상기 게이트산화막 윗부분에 SixNyOz가 형성되는 것을 특징으로 하는 반도체소자 제조방법.
  5. 제1항에 있어서, 상기 폴리실리콘층을 안정화시키면서 도판트를 활성화시키는 단계는 고온에서의 폴리실리콘 산화공정 또는 어닐링에 의해 행하는 것을 특징으로 하는 반도체소자 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960018366A 1996-05-28 1996-05-28 반도체소자의제조방법 KR100399957B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960018366A KR100399957B1 (ko) 1996-05-28 1996-05-28 반도체소자의제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960018366A KR100399957B1 (ko) 1996-05-28 1996-05-28 반도체소자의제조방법

Publications (2)

Publication Number Publication Date
KR970077222A true KR970077222A (ko) 1997-12-12
KR100399957B1 KR100399957B1 (ko) 2003-12-24

Family

ID=37422300

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960018366A KR100399957B1 (ko) 1996-05-28 1996-05-28 반도체소자의제조방법

Country Status (1)

Country Link
KR (1) KR100399957B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005052358A1 (de) * 2005-09-01 2007-03-15 Osram Opto Semiconductors Gmbh Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement

Also Published As

Publication number Publication date
KR100399957B1 (ko) 2003-12-24

Similar Documents

Publication Publication Date Title
US6184072B1 (en) Process for forming a high-K gate dielectric
KR970024304A (ko) 박막 트랜지스터 제조방법
JPH0794503A (ja) シリコン基板の酸化方法
KR970077222A (ko) 반도체소자의 제조방법
US5970350A (en) Semiconductor device having a thin gate oxide and method of manufacture thereof
WO1999065070A3 (en) Method of manufacturing a semiconductor device comprising a mos transistor
KR100336572B1 (ko) 폴리 실리콘-저마늄을 게이트 전극으로 사용하는 반도체소자의 형성방법
KR950030336A (ko) 캐패시터의 유전체막 형성방법
KR940016961A (ko) 모스(mos) 트랜지스터 및 그 제조 방법
KR100701691B1 (ko) 핀 전계 효과 트랜지스터 제조방법
KR940004711A (ko) 폴리실리콘층 형성방법
KR970053071A (ko) 모스펫의 제조방법
KR920007181A (ko) 앤-모스 ldd트랜지스터의 제조방법
KR970054268A (ko) 반도체 에스 오 아이 소자의 제조방법
KR970003690A (ko) 초고집적화용 낮은 접합 형성방법
KR940016901A (ko) 모스(mos) 트랜지스터 제조방법
KR970013426A (ko) 박막트랜지스터 제조방법
KR970072172A (ko) 게이트 절연막으로 확산방지막을 사용하는 반도체장치의 제조방법
KR950021113A (ko) 반도체 소자의 게이트 전극 형성 방법
KR960026448A (ko) 트랜지스터 제조 방법
KR930015081A (ko) 얕은 접합 모스패트 제조방법
KR960026179A (ko) 반도체 소자의 콘택구조 및 콘택형성방법
JPH0823097A (ja) 半導体装置の製造方法
KR920005373A (ko) 수직모스 트랜지스터 제조방법
KR910003786A (ko) 게이트전극 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100825

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee