KR970054334A - 박막트랜지스터 및 그의 제조방법 - Google Patents

박막트랜지스터 및 그의 제조방법 Download PDF

Info

Publication number
KR970054334A
KR970054334A KR1019950056315A KR19950056315A KR970054334A KR 970054334 A KR970054334 A KR 970054334A KR 1019950056315 A KR1019950056315 A KR 1019950056315A KR 19950056315 A KR19950056315 A KR 19950056315A KR 970054334 A KR970054334 A KR 970054334A
Authority
KR
South Korea
Prior art keywords
gate electrode
layer
thin film
film transistor
active layer
Prior art date
Application number
KR1019950056315A
Other languages
English (en)
Other versions
KR100205442B1 (ko
Inventor
양해창
Original Assignee
문정환
Lg 반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체 주식회사 filed Critical 문정환
Priority to KR1019950056315A priority Critical patent/KR100205442B1/ko
Priority to US08/634,037 priority patent/US5637884A/en
Priority to JP8294653A priority patent/JPH09186341A/ja
Priority to US08/808,166 priority patent/US5811324A/en
Publication of KR970054334A publication Critical patent/KR970054334A/ko
Application granted granted Critical
Publication of KR100205442B1 publication Critical patent/KR100205442B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices
    • H10B10/12Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903FET configuration adapted for use as static memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 박막트랜지스터 및 그의 제조방법에 관한 것으로, 구체적으로는 온 커렌트(On Current)를 증가시켜서 온/오프 커렌트비와 값을 향상시키도록 한 듀얼채널 구조의 박막트랜지스터 및 그의 제조방법에 관한 것이다.
이를 위한 본 발명의 박막트랜지스터는 기판상에 형성된 제1활성층, 제1활성층의 중앙부와 기판상에 형성되고 양측면, 상부면, 그리고 상기 제1활성층의 중앙부와 접하는 하부면을 가지는 게이트 전극, 제1활성층과 전기적으로 연결되고 게이트 전극의 양측면 및 상부면에 형성된 제2활성층, 게이트 전극의 양측면의 제1 및 제2활성층에 형성된 불순물 영역을 포함하는 것을 특징으로 하고, 본 발명의 박막트랜지스터의 제조방법은 기판상에 패턴화된 임의층을 형성하는 공정, 상기 임의층과 교차되도록 상기 기판 및 임의층상에 게이트 전극을 형성하는 공정, 상기 임의층을 제거하는 공정, 상기 임의층이 제거된 부분을 포함한 상기 게이트 전극의 표면에 게이트 절연막을 형성하는 공정, 상기 게이트 전극과 교차되도록 기판 및 임의층이 제거된 게이트 전극의 하부, 그리고 게이트 전극의 상부에 활성층을 형성하는 공정, 상기 게이트 전극 양측의 활성층에 불순물 영역을 형성하는 공정으로 이루어진다.

Description

박막트랜지스터 및 그의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 (a) 및 제2도 (b)는 본원 발명의 박막트랜지스터의 단면도 및 사시도.

Claims (14)

  1. 기판상에 형성된 제1활성층, 제1활성층의 중앙부와 기판상에 형성되고 양측면, 상부면, 그리고 상기 제1활성층의 중앙부와 접하는 하부면을 가지는 게이트 전극, 제1활성층과 전기적으로 연결되고 게이트 전극의 양측면 및 상부면에 형성된 제2활성층, 게이트 전극의 양측면의 제1 및 제2활성층에 형성된 불순물 영역을 포함하는 박막트랜지스터.
  2. 제1항에 있어서, 제1 및 제2활성층은 보다 다결정 실리콘을 포함하는 것을 특징으로 하는 박막 트랜지스터.
  3. 제2항에 있어서, 다결정 실리콘은 P형임을 특징으로 하는 박막트랜지스터.
  4. 제1항에 있어서, 게이트 전극의 하부면에 대응되는 제1활성층에 형성되는 제1채널영역과 게이트 전극의 상부면에 대응되는 제2활성층에 형성되는 제2채널영역을 더 포함하는 것을 특징으로 하는 박막트랜지스터.
  5. 제1항에 있어서, 게이트 전극의 일측면의 제1 및 제2활성층에 형성되고 게이트 전극과 불순물 영역 사이에 위치하는 오프셋 영역을 더 포함하는 것을 특징으로 하는 박막트랜지스터.
  6. 제1항에 있어서, 상기 게이트 전극은 다결정 실리콘을 포함함을 특징으로 하는 박막트랜지스터.
  7. 기판상에 패턴화된 임의층을 형성하는 공정, 상기 임의층과 교차되도록 상기 기판 및 임의층상에 게이트 전극을 형성하는 공정, 상기 임의층을 제거하는 공정, 상기 임의층이 제거된 부분을 포함한 상기 게이트 전극의 표면에 게이트 절연막을 형성하는 공정, 상기 게이트 전극과 교차되도록 기판 및 임의층이 제거된 게이트 전극의 하부, 그리고 게이트 전극의 상부에 활성층을 형성하는 공정, 상기 게이트 전극 양측의 활성층에 불순물 영역을 형성하는 공정을 포함함을 특징으로 하는 박막트랜지스터의 제조방법.
  8. 제7항에 있어서, 상기 임의층과 상기 게이트 전극은 식각비가 상이함을 특징으로 하는 박막트랜지스터의 제조방법.
  9. 제7항에 있어서, 상기 게이트 전극은 다결정 실리콘층으로 형성됨을 특징으로 하는 박막트랜지스터의 제조방법.
  10. 제7항에 있어서, 상기 활성층은 보디 다결정 실리콘층으로 형성됨을 특징으로 하는 박막트랜지스터의 제조방법.
  11. 제10항에 있어서, 상기 보디 다결정 실리콘은 P형임을 특징으로 하는박막트랜지스터의 제조방법.
  12. 제7항에 있어서, 상기 임의층은 질화막으로 형성됨을 특징으로 하는 박막트랜지스터의 제조방법.
  13. 제7항에 있어서, 상기 게이트 전극 양측의 활성층에 불순물 영역을 형성하는 공정은 경사이온 주입을 포함함을 특징으로 하는 박막트랜지스터의 제조방법.
  14. 제7항에 있어서, 상기 게이트 전극 일측의 불순물 영역은 게이트 전극과 오버-랩되고 다른 일측의 불순물 영역은 상기 게이트 전극과 오프-셋 되도록 형성함을 특징으로 하는 박막 트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950056315A 1995-12-26 1995-12-26 박막트랜지스터 및 그의 제조방법 KR100205442B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019950056315A KR100205442B1 (ko) 1995-12-26 1995-12-26 박막트랜지스터 및 그의 제조방법
US08/634,037 US5637884A (en) 1995-12-26 1996-04-17 Thin film transistor having increased on current
JP8294653A JPH09186341A (ja) 1995-12-26 1996-10-17 薄膜トランジスタ及びその製造方法
US08/808,166 US5811324A (en) 1995-12-26 1997-02-28 Method for manufacturing thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950056315A KR100205442B1 (ko) 1995-12-26 1995-12-26 박막트랜지스터 및 그의 제조방법

Publications (2)

Publication Number Publication Date
KR970054334A true KR970054334A (ko) 1997-07-31
KR100205442B1 KR100205442B1 (ko) 1999-07-01

Family

ID=19444274

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950056315A KR100205442B1 (ko) 1995-12-26 1995-12-26 박막트랜지스터 및 그의 제조방법

Country Status (3)

Country Link
US (2) US5637884A (ko)
JP (1) JPH09186341A (ko)
KR (1) KR100205442B1 (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476398B1 (ko) * 1997-12-30 2005-07-05 주식회사 하이닉스반도체 반도체소자의박막트랜지스터및그형성방법
US9601518B2 (en) 2015-04-08 2017-03-21 Samsung Display Co., Ltd. Thin film transistor display panel and method for manufacturing the same

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10012112C2 (de) * 2000-03-13 2002-01-10 Infineon Technologies Ag Steg-Feldeffekttransistor und Verfahren zum Herstellen eines Steg-Feldeffekttransistors
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
FR2860099B1 (fr) * 2003-09-18 2006-01-06 St Microelectronics Sa Procede de realisation d'un transistor a effet de champ et transistor ainsi obtenu
US8052676B2 (en) * 2003-12-02 2011-11-08 Boston Scientific Scimed, Inc. Surgical methods and apparatus for stimulating tissue
US7608072B2 (en) 2003-12-02 2009-10-27 Boston Scientific Scimed, Inc. Surgical methods and apparatus for maintaining contact between tissue and electrophysiology elements and confirming whether a therapeutic lesion has been formed
US7371233B2 (en) * 2004-02-19 2008-05-13 Boston Scientific Scimed, Inc. Cooled probes and apparatus for maintaining contact between cooled probes and tissue
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
KR100663360B1 (ko) * 2005-04-20 2007-01-02 삼성전자주식회사 박막 트랜지스터를 갖는 반도체 소자들 및 그 제조방법들
US8016822B2 (en) * 2005-05-28 2011-09-13 Boston Scientific Scimed, Inc. Fluid injecting devices and methods and apparatus for maintaining contact between fluid injecting devices and tissue
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7709313B2 (en) * 2005-07-19 2010-05-04 International Business Machines Corporation High performance capacitors in planar back gates CMOS
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57211779A (en) * 1981-06-23 1982-12-25 Nec Corp Field effect transistor
JPH02302044A (ja) * 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
JP2941908B2 (ja) * 1989-07-31 1999-08-30 キヤノン株式会社 薄膜トランジスタ及びその製造方法並びにそれを有する装置
JPH03101270A (ja) * 1989-09-14 1991-04-26 Sony Corp ポリシリコン薄膜トランジスタ
JPH0411771A (ja) * 1990-04-28 1992-01-16 Nec Corp 多結晶シリコントランジスタ及び半導体記憶装置
US5095347A (en) * 1990-08-01 1992-03-10 Motorola, Inc. Plural transistor silicon on insulator structure with shared electrodes
JPH04114437A (ja) * 1990-09-04 1992-04-15 Fujitsu Ltd 半導体装置及びその製造方法
US5420055A (en) * 1992-01-22 1995-05-30 Kopin Corporation Reduction of parasitic effects in floating body MOSFETs
JPH0629535A (ja) * 1992-07-09 1994-02-04 Casio Comput Co Ltd 薄膜トランジスタ
JP3460863B2 (ja) * 1993-09-17 2003-10-27 三菱電機株式会社 半導体装置の製造方法
US5497019A (en) * 1994-09-22 1996-03-05 The Aerospace Corporation Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods
JPH08148693A (ja) * 1994-09-22 1996-06-07 Sanyo Electric Co Ltd 薄膜トランジスタ及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476398B1 (ko) * 1997-12-30 2005-07-05 주식회사 하이닉스반도체 반도체소자의박막트랜지스터및그형성방법
US9601518B2 (en) 2015-04-08 2017-03-21 Samsung Display Co., Ltd. Thin film transistor display panel and method for manufacturing the same

Also Published As

Publication number Publication date
US5811324A (en) 1998-09-22
KR100205442B1 (ko) 1999-07-01
US5637884A (en) 1997-06-10
JPH09186341A (ja) 1997-07-15

Similar Documents

Publication Publication Date Title
KR970054334A (ko) 박막트랜지스터 및 그의 제조방법
KR0139573B1 (ko) 이중 채널 박막트랜지스터 및 그 제조방법
KR960030441A (ko) 전계효과트랜지스터 및 그 제조방법
KR980005441A (ko) 반도체 소자의 제조 방법
KR960039222A (ko) 반도체장치 및 그 제조방법
KR930005120A (ko) 반도체 장치의 제조방법
KR890012400A (ko) 트랜치를 갖는 반도체 장치와 그의 제조방법
KR950034667A (ko) 반도체 소자 및 그 제조방법
KR970054180A (ko) 반도체소자 및 제조방법
KR870002657A (ko) 독출전용 반도체기억장치와 그 제조방법
KR930009116A (ko) 박막트랜지스터와 그의 제조방법
KR950009922A (ko) 반도체소자의 콘택구조 및 그 제조방법
KR970054507A (ko) 박막 트랜지스터 및 그 제조 방법
KR970053807A (ko) 바이폴라 트랜지스터 구조를 이용한 접합 축전기 및 그 제조 방법
KR970054218A (ko) 고전압 트랜지스터 제조방법
KR970018704A (ko) 수직구조의 mos트랜지스터를 갖는 반도체장치 및 그 제조방법
KR960026848A (ko) 반도체소자의 캐패시터 제조방법
KR950025994A (ko) 반도체 기억소자의 캐패시터 형성 방법
KR970008644A (ko) 고전압용 모스 트랜지스터 및 그 제조방법
KR910020920A (ko) 전계효과트랜지스터 및 그 제조방법
KR970018695A (ko) 박막 트랜지스터 및 그 제조방법
KR980006529A (ko) 박막 트랜지스터 및 그 제조방법
KR970003788A (ko) 반도체 소자의 제조방법
KR970030498A (ko) 반도체장치의 제조방법
KR970072492A (ko) 박막트랜지스터 및 그 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120323

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee